thread_context.hh revision 3686
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 32#define __CPU_O3_THREAD_CONTEXT_HH__ 33 34#include "cpu/thread_context.hh" 35#include "cpu/o3/isa_specific.hh" 36 37class EndQuiesceEvent; 38namespace Kernel { 39 class Statistics; 40}; 41 42class TranslatingPort; 43 44/** 45 * Derived ThreadContext class for use with the O3CPU. It 46 * provides the interface for any external objects to access a 47 * single thread's state and some general CPU state. Any time 48 * external objects try to update state through this interface, 49 * the CPU will create an event to squash all in-flight 50 * instructions in order to ensure state is maintained correctly. 51 * It must be defined specifically for the O3CPU because 52 * not all architectural state is located within the O3ThreadState 53 * (such as the commit PC, and registers), and specific actions 54 * must be taken when using this interface (such as squashing all 55 * in-flight instructions when doing a write to this interface). 56 */ 57template <class Impl> 58class O3ThreadContext : public ThreadContext 59{ 60 public: 61 typedef typename Impl::O3CPU O3CPU; 62 63 /** Pointer to the CPU. */ 64 O3CPU *cpu; 65 66 /** Pointer to the thread state that this TC corrseponds to. */ 67 O3ThreadState<Impl> *thread; 68 69 /** Returns a pointer to this CPU. */ 70 virtual BaseCPU *getCpuPtr() { return cpu; } 71 72 /** Sets this CPU's ID. */ 73 virtual void setCpuId(int id) { cpu->setCpuId(id); } 74 75 /** Reads this CPU's ID. */ 76 virtual int readCpuId() { return cpu->readCpuId(); } 77 78#if FULL_SYSTEM 79 /** Returns a pointer to the system. */ 80 virtual System *getSystemPtr() { return cpu->system; } 81 82 /** Returns a pointer to physical memory. */ 83 virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } 84 85 /** Returns a pointer to this thread's kernel statistics. */ 86 virtual TheISA::Kernel::Statistics *getKernelStats() 87 { return thread->kernelStats; } 88 89 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } 90 91 virtual VirtualPort *getVirtPort(ThreadContext *src_tc = NULL); 92 93 void delVirtPort(VirtualPort *vp); 94 95 virtual void connectMemPorts() { thread->connectMemPorts(); } 96#else 97 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); } 98 99 /** Returns a pointer to this thread's process. */ 100 virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 101#endif 102 /** Returns this thread's status. */ 103 virtual Status status() const { return thread->status(); } 104 105 /** Sets this thread's status. */ 106 virtual void setStatus(Status new_status) 107 { thread->setStatus(new_status); } 108 109 /** Set the status to Active. Optional delay indicates number of 110 * cycles to wait before beginning execution. */ 111 virtual void activate(int delay = 1); 112 113 /** Set the status to Suspended. */ 114 virtual void suspend(); 115 116 /** Set the status to Unallocated. */ 117 virtual void deallocate(int delay = 0); 118 119 /** Set the status to Halted. */ 120 virtual void halt(); 121 122#if FULL_SYSTEM 123 /** Dumps the function profiling information. 124 * @todo: Implement. 125 */ 126 virtual void dumpFuncProfile(); 127#endif 128 /** Takes over execution of a thread from another CPU. */ 129 virtual void takeOverFrom(ThreadContext *old_context); 130 131 /** Registers statistics associated with this TC. */ 132 virtual void regStats(const std::string &name); 133 134 /** Serializes state. */ 135 virtual void serialize(std::ostream &os); 136 /** Unserializes state. */ 137 virtual void unserialize(Checkpoint *cp, const std::string §ion); 138 139#if FULL_SYSTEM 140 /** Reads the last tick that this thread was activated on. */ 141 virtual Tick readLastActivate(); 142 /** Reads the last tick that this thread was suspended on. */ 143 virtual Tick readLastSuspend(); 144 145 /** Clears the function profiling information. */ 146 virtual void profileClear(); 147 /** Samples the function profiling information. */ 148 virtual void profileSample(); 149#endif 150 /** Returns this thread's ID number. */ 151 virtual int getThreadNum() { return thread->readTid(); } 152 153 /** Returns the instruction this thread is currently committing. 154 * Only used when an instruction faults. 155 */ 156 virtual TheISA::MachInst getInst(); 157 158 /** Copies the architectural registers from another TC into this TC. */ 159 virtual void copyArchRegs(ThreadContext *tc); 160 161 /** Resets all architectural registers to 0. */ 162 virtual void clearArchRegs(); 163 164 /** Reads an integer register. */ 165 virtual uint64_t readIntReg(int reg_idx); 166 167 virtual FloatReg readFloatReg(int reg_idx, int width); 168 169 virtual FloatReg readFloatReg(int reg_idx); 170 171 virtual FloatRegBits readFloatRegBits(int reg_idx, int width); 172 173 virtual FloatRegBits readFloatRegBits(int reg_idx); 174 175 /** Sets an integer register to a value. */ 176 virtual void setIntReg(int reg_idx, uint64_t val); 177 178 virtual void setFloatReg(int reg_idx, FloatReg val, int width); 179 180 virtual void setFloatReg(int reg_idx, FloatReg val); 181 182 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); 183 184 virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 185 186 /** Reads this thread's PC. */ 187 virtual uint64_t readPC() 188 { return cpu->readPC(thread->readTid()); } 189 190 /** Sets this thread's PC. */ 191 virtual void setPC(uint64_t val); 192 193 /** Reads this thread's next PC. */ 194 virtual uint64_t readNextPC() 195 { return cpu->readNextPC(thread->readTid()); } 196 197 /** Sets this thread's next PC. */ 198 virtual void setNextPC(uint64_t val); 199 200 /** Reads a miscellaneous register. */ 201 virtual MiscReg readMiscReg(int misc_reg) 202 { return cpu->readMiscReg(misc_reg, thread->readTid()); } 203 204 /** Reads a misc. register, including any side-effects the 205 * read might have as defined by the architecture. */ 206 virtual MiscReg readMiscRegWithEffect(int misc_reg) 207 { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } 208 209 /** Sets a misc. register. */ 210 virtual void setMiscReg(int misc_reg, const MiscReg &val); 211 212 /** Sets a misc. register, including any side-effects the 213 * write might have as defined by the architecture. */ 214 virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 215 216 /** Returns the number of consecutive store conditional failures. */ 217 // @todo: Figure out where these store cond failures should go. 218 virtual unsigned readStCondFailures() 219 { return thread->storeCondFailures; } 220 221 /** Sets the number of consecutive store conditional failures. */ 222 virtual void setStCondFailures(unsigned sc_failures) 223 { thread->storeCondFailures = sc_failures; } 224 225 // Only really makes sense for old CPU model. Lots of code 226 // outside the CPU still checks this function, so it will 227 // always return false to keep everything working. 228 /** Checks if the thread is misspeculating. Because it is 229 * very difficult to determine if the thread is 230 * misspeculating, this is set as false. */ 231 virtual bool misspeculating() { return false; } 232 233#if !FULL_SYSTEM 234 /** Gets a syscall argument by index. */ 235 virtual IntReg getSyscallArg(int i); 236 237 /** Sets a syscall argument. */ 238 virtual void setSyscallArg(int i, IntReg val); 239 240 /** Sets the syscall return value. */ 241 virtual void setSyscallReturn(SyscallReturn return_value); 242 243 /** Executes a syscall in SE mode. */ 244 virtual void syscall(int64_t callnum) 245 { return cpu->syscall(callnum, thread->readTid()); } 246 247 /** Reads the funcExeInst counter. */ 248 virtual Counter readFuncExeInst() { return thread->funcExeInst; } 249#endif 250}; 251 252#endif 253