thread_context.hh revision 8852
12817Sksewell@umich.edu/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392817Sksewell@umich.edu * 402817Sksewell@umich.edu * Authors: Kevin Lim 412817Sksewell@umich.edu */ 422817Sksewell@umich.edu 432817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 442817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu 466658Snate@binkert.org#include "config/the_isa.hh" 478733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 542834Sksewell@umich.edu}; 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 826022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 856022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 878733Sgeoffrey.blake@arm.com#if USE_CHECKER 888733Sgeoffrey.blake@arm.com BaseCPU *getCheckerCpuPtr() { return NULL; } 898733Sgeoffrey.blake@arm.com#endif 908733Sgeoffrey.blake@arm.com 918541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } 928541Sgblack@eecs.umich.edu 932817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 942817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 952817Sksewell@umich.edu 962817Sksewell@umich.edu /** Reads this CPU's ID. */ 975712Shsul@eecs.umich.edu virtual int cpuId() { return cpu->cpuId(); } 982817Sksewell@umich.edu 995714Shsul@eecs.umich.edu virtual int contextId() { return thread->contextId(); } 1005714Shsul@eecs.umich.edu 1015714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1025714Shsul@eecs.umich.edu 1035715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 1045715Shsul@eecs.umich.edu virtual int threadId() { return thread->threadId(); } 1055715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1065715Shsul@eecs.umich.edu 1072817Sksewell@umich.edu /** Returns a pointer to the system. */ 1082817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 1092817Sksewell@umich.edu 1102817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1113548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1122817Sksewell@umich.edu { return thread->kernelStats; } 1132817Sksewell@umich.edu 1148541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1158541Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1168754Sgblack@eecs.umich.edu 1178852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1182817Sksewell@umich.edu 1198852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy(); 1203675Sktlim@umich.edu 1218706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) 1228706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1238799Sgblack@eecs.umich.edu 1248852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() 1258706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1262817Sksewell@umich.edu 1272817Sksewell@umich.edu /** Returns this thread's status. */ 1282817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1292817Sksewell@umich.edu 1302817Sksewell@umich.edu /** Sets this thread's status. */ 1312817Sksewell@umich.edu virtual void setStatus(Status new_status) 1322817Sksewell@umich.edu { thread->setStatus(new_status); } 1332817Sksewell@umich.edu 1342817Sksewell@umich.edu /** Set the status to Active. Optional delay indicates number of 1352817Sksewell@umich.edu * cycles to wait before beginning execution. */ 1362817Sksewell@umich.edu virtual void activate(int delay = 1); 1372817Sksewell@umich.edu 1382817Sksewell@umich.edu /** Set the status to Suspended. */ 1395250Sksewell@umich.edu virtual void suspend(int delay = 0); 1402817Sksewell@umich.edu 1412817Sksewell@umich.edu /** Set the status to Halted. */ 1425250Sksewell@umich.edu virtual void halt(int delay = 0); 1432817Sksewell@umich.edu 1442817Sksewell@umich.edu /** Dumps the function profiling information. 1452817Sksewell@umich.edu * @todo: Implement. 1462817Sksewell@umich.edu */ 1472817Sksewell@umich.edu virtual void dumpFuncProfile(); 1488777Sgblack@eecs.umich.edu 1492817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1502817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1512817Sksewell@umich.edu 1522817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1532817Sksewell@umich.edu virtual void regStats(const std::string &name); 1542817Sksewell@umich.edu 1552817Sksewell@umich.edu /** Serializes state. */ 1562817Sksewell@umich.edu virtual void serialize(std::ostream &os); 1572817Sksewell@umich.edu /** Unserializes state. */ 1582817Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1592817Sksewell@umich.edu 1602817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1612817Sksewell@umich.edu virtual Tick readLastActivate(); 1622817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1632817Sksewell@umich.edu virtual Tick readLastSuspend(); 1642817Sksewell@umich.edu 1652817Sksewell@umich.edu /** Clears the function profiling information. */ 1662817Sksewell@umich.edu virtual void profileClear(); 1672817Sksewell@umich.edu /** Samples the function profiling information. */ 1682817Sksewell@umich.edu virtual void profileSample(); 1692817Sksewell@umich.edu 1702817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1712817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1722817Sksewell@umich.edu 1732817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1742817Sksewell@umich.edu virtual void clearArchRegs(); 1752817Sksewell@umich.edu 1762817Sksewell@umich.edu /** Reads an integer register. */ 1772817Sksewell@umich.edu virtual uint64_t readIntReg(int reg_idx); 1782817Sksewell@umich.edu 1792817Sksewell@umich.edu virtual FloatReg readFloatReg(int reg_idx); 1802817Sksewell@umich.edu 1812817Sksewell@umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx); 1822817Sksewell@umich.edu 1832817Sksewell@umich.edu /** Sets an integer register to a value. */ 1842817Sksewell@umich.edu virtual void setIntReg(int reg_idx, uint64_t val); 1852817Sksewell@umich.edu 1862817Sksewell@umich.edu virtual void setFloatReg(int reg_idx, FloatReg val); 1872817Sksewell@umich.edu 1882817Sksewell@umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val); 1892817Sksewell@umich.edu 1907720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 1917720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 1927720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 1937720Sgblack@eecs.umich.edu 1947720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 1957720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 1967720Sgblack@eecs.umich.edu 1978733Sgeoffrey.blake@arm.com#if USE_CHECKER 1988733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val); 1998733Sgeoffrey.blake@arm.com#endif 2008733Sgeoffrey.blake@arm.com 2012817Sksewell@umich.edu /** Reads this thread's PC. */ 2027720Sgblack@eecs.umich.edu virtual Addr instAddr() 2037720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 2042817Sksewell@umich.edu 2052817Sksewell@umich.edu /** Reads this thread's next PC. */ 2067720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 2077720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 2082817Sksewell@umich.edu 2097720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 2107720Sgblack@eecs.umich.edu virtual MicroPC microPC() 2117720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 2125259Sksewell@umich.edu 2132817Sksewell@umich.edu /** Reads a miscellaneous register. */ 2144172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) 2155715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 2164172Ssaidi@eecs.umich.edu 2174172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2184172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 2192817Sksewell@umich.edu virtual MiscReg readMiscReg(int misc_reg) 2205715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2212817Sksewell@umich.edu 2222817Sksewell@umich.edu /** Sets a misc. register. */ 2234172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2242817Sksewell@umich.edu 2252817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 2262817Sksewell@umich.edu * write might have as defined by the architecture. */ 2274172Ssaidi@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2282817Sksewell@umich.edu 2296313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2306313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2316313Sgblack@eecs.umich.edu 2322817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 2332817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 2342817Sksewell@umich.edu virtual unsigned readStCondFailures() 2352817Sksewell@umich.edu { return thread->storeCondFailures; } 2362817Sksewell@umich.edu 2372817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 2382817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 2392817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 2402817Sksewell@umich.edu 2412817Sksewell@umich.edu // Only really makes sense for old CPU model. Lots of code 2422817Sksewell@umich.edu // outside the CPU still checks this function, so it will 2432817Sksewell@umich.edu // always return false to keep everything working. 2442817Sksewell@umich.edu /** Checks if the thread is misspeculating. Because it is 2452817Sksewell@umich.edu * very difficult to determine if the thread is 2462817Sksewell@umich.edu * misspeculating, this is set as false. */ 2472817Sksewell@umich.edu virtual bool misspeculating() { return false; } 2482817Sksewell@umich.edu 2492817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 2502817Sksewell@umich.edu virtual void syscall(int64_t callnum) 2515715Shsul@eecs.umich.edu { return cpu->syscall(callnum, thread->threadId()); } 2522817Sksewell@umich.edu 2532817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 2542817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2558777Sgblack@eecs.umich.edu 2565595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2575595Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2585595Sgblack@eecs.umich.edu { 2595595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2605595Sgblack@eecs.umich.edu } 2615595Sgblack@eecs.umich.edu 2622817Sksewell@umich.edu}; 2632817Sksewell@umich.edu 2642817Sksewell@umich.edu#endif 265