thread_context.hh revision 13582
12817Sksewell@umich.edu/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2011-2012, 2016 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 442817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462817Sksewell@umich.edu 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 548902Sandreas.hansson@arm.com} 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 8212406Sgabeblack@google.com BaseTLB *getITBPtr() { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 8512406Sgabeblack@google.com BaseTLB *getDTBPtr() { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 878887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 888733Sgeoffrey.blake@arm.com 899023Sgblack@eecs.umich.edu TheISA::Decoder * 909023Sgblack@eecs.umich.edu getDecoderPtr() 919023Sgblack@eecs.umich.edu { 929023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 939023Sgblack@eecs.umich.edu } 948541Sgblack@eecs.umich.edu 952817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 962817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 972817Sksewell@umich.edu 982817Sksewell@umich.edu /** Reads this CPU's ID. */ 9910110Sandreas.hansson@arm.com virtual int cpuId() const { return cpu->cpuId(); } 1002817Sksewell@umich.edu 10110190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 10210190Sakash.bagdia@arm.com virtual uint32_t socketId() const { return cpu->socketId(); } 10310190Sakash.bagdia@arm.com 10411005Sandreas.sandberg@arm.com virtual ContextID contextId() const { return thread->contextId(); } 1055714Shsul@eecs.umich.edu 1065714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1075714Shsul@eecs.umich.edu 1085715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 10910110Sandreas.hansson@arm.com virtual int threadId() const { return thread->threadId(); } 1105715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1115715Shsul@eecs.umich.edu 1122817Sksewell@umich.edu /** Returns a pointer to the system. */ 1132817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 1142817Sksewell@umich.edu 1152817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1163548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1172817Sksewell@umich.edu { return thread->kernelStats; } 1182817Sksewell@umich.edu 1198541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1208541Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1218754Sgblack@eecs.umich.edu 12211886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) { thread->setProcessPtr(p); } 12311886Sbrandon.potter@amd.com 1248852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1252817Sksewell@umich.edu 1268852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy(); 1273675Sktlim@umich.edu 1288706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) 1298706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1308799Sgblack@eecs.umich.edu 1318852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() 1328706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1332817Sksewell@umich.edu 1342817Sksewell@umich.edu /** Returns this thread's status. */ 1352817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1362817Sksewell@umich.edu 1372817Sksewell@umich.edu /** Sets this thread's status. */ 1382817Sksewell@umich.edu virtual void setStatus(Status new_status) 1392817Sksewell@umich.edu { thread->setStatus(new_status); } 1402817Sksewell@umich.edu 14110407Smitch.hayenga@arm.com /** Set the status to Active. */ 14210407Smitch.hayenga@arm.com virtual void activate(); 1432817Sksewell@umich.edu 1442817Sksewell@umich.edu /** Set the status to Suspended. */ 14510407Smitch.hayenga@arm.com virtual void suspend(); 1462817Sksewell@umich.edu 1472817Sksewell@umich.edu /** Set the status to Halted. */ 14810407Smitch.hayenga@arm.com virtual void halt(); 1492817Sksewell@umich.edu 1502817Sksewell@umich.edu /** Dumps the function profiling information. 1512817Sksewell@umich.edu * @todo: Implement. 1522817Sksewell@umich.edu */ 1532817Sksewell@umich.edu virtual void dumpFuncProfile(); 1548777Sgblack@eecs.umich.edu 1552817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1562817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1572817Sksewell@umich.edu 1582817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1592817Sksewell@umich.edu virtual void regStats(const std::string &name); 1602817Sksewell@umich.edu 1612817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1622817Sksewell@umich.edu virtual Tick readLastActivate(); 1632817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1642817Sksewell@umich.edu virtual Tick readLastSuspend(); 1652817Sksewell@umich.edu 1662817Sksewell@umich.edu /** Clears the function profiling information. */ 1672817Sksewell@umich.edu virtual void profileClear(); 1682817Sksewell@umich.edu /** Samples the function profiling information. */ 1692817Sksewell@umich.edu virtual void profileSample(); 1702817Sksewell@umich.edu 1712817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1722817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1732817Sksewell@umich.edu 1742817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1752817Sksewell@umich.edu virtual void clearArchRegs(); 1762817Sksewell@umich.edu 1772817Sksewell@umich.edu /** Reads an integer register. */ 17813557Sgabeblack@google.com virtual RegVal 17913557Sgabeblack@google.com readReg(int reg_idx) 18013557Sgabeblack@google.com { 18112106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 18212106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 18312106SRekai.GonzalezAlberquilla@arm.com } 18413557Sgabeblack@google.com virtual RegVal 18513557Sgabeblack@google.com readIntReg(int reg_idx) 18613557Sgabeblack@google.com { 18712106SRekai.GonzalezAlberquilla@arm.com return readIntRegFlat(flattenRegId(RegId(IntRegClass, 18812106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 1899426SAndreas.Sandberg@ARM.com } 1902817Sksewell@umich.edu 19113557Sgabeblack@google.com virtual RegVal 19213557Sgabeblack@google.com readFloatRegBits(int reg_idx) 19313557Sgabeblack@google.com { 19412106SRekai.GonzalezAlberquilla@arm.com return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 19512106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 1969426SAndreas.Sandberg@ARM.com } 1972817Sksewell@umich.edu 19813557Sgabeblack@google.com virtual const VecRegContainer & 19913557Sgabeblack@google.com readVecReg(const RegId& id) const 20013557Sgabeblack@google.com { 20112109SRekai.GonzalezAlberquilla@arm.com return readVecRegFlat(flattenRegId(id).index()); 20212109SRekai.GonzalezAlberquilla@arm.com } 20312109SRekai.GonzalezAlberquilla@arm.com 20412109SRekai.GonzalezAlberquilla@arm.com /** 20512109SRekai.GonzalezAlberquilla@arm.com * Read vector register operand for modification, hierarchical indexing. 20612109SRekai.GonzalezAlberquilla@arm.com */ 20713557Sgabeblack@google.com virtual VecRegContainer & 20813557Sgabeblack@google.com getWritableVecReg(const RegId& id) 20913557Sgabeblack@google.com { 21012109SRekai.GonzalezAlberquilla@arm.com return getWritableVecRegFlat(flattenRegId(id).index()); 21112109SRekai.GonzalezAlberquilla@arm.com } 21212109SRekai.GonzalezAlberquilla@arm.com 21312109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 21412109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 21512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 21612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 21712109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& id) const 21812109SRekai.GonzalezAlberquilla@arm.com { 21912109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint8_t>(flattenRegId(id).index(), 22012109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 22112109SRekai.GonzalezAlberquilla@arm.com } 22212109SRekai.GonzalezAlberquilla@arm.com 22312109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22412109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 22512109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& id) const 22612109SRekai.GonzalezAlberquilla@arm.com { 22712109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint16_t>(flattenRegId(id).index(), 22812109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 22912109SRekai.GonzalezAlberquilla@arm.com } 23012109SRekai.GonzalezAlberquilla@arm.com 23112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 23212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 23312109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& id) const 23412109SRekai.GonzalezAlberquilla@arm.com { 23512109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint32_t>(flattenRegId(id).index(), 23612109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 23712109SRekai.GonzalezAlberquilla@arm.com } 23812109SRekai.GonzalezAlberquilla@arm.com 23912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 24012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 24112109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& id) const 24212109SRekai.GonzalezAlberquilla@arm.com { 24312109SRekai.GonzalezAlberquilla@arm.com return readVecLaneFlat<uint64_t>(flattenRegId(id).index(), 24412109SRekai.GonzalezAlberquilla@arm.com id.elemIndex()); 24512109SRekai.GonzalezAlberquilla@arm.com } 24612109SRekai.GonzalezAlberquilla@arm.com 24712109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 24812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 25012109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 25112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 25312109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 25412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 25612109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 25712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 25812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 25912109SRekai.GonzalezAlberquilla@arm.com { return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val); } 26012109SRekai.GonzalezAlberquilla@arm.com /** @} */ 26112109SRekai.GonzalezAlberquilla@arm.com 26212109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const { 26312109SRekai.GonzalezAlberquilla@arm.com return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex()); 26412109SRekai.GonzalezAlberquilla@arm.com } 26512109SRekai.GonzalezAlberquilla@arm.com 2669920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) { 26712106SRekai.GonzalezAlberquilla@arm.com return readCCRegFlat(flattenRegId(RegId(CCRegClass, 26812106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index()); 2699920Syasuko.eckert@amd.com } 2709920Syasuko.eckert@amd.com 2712817Sksewell@umich.edu /** Sets an integer register to a value. */ 27213557Sgabeblack@google.com virtual void 27313557Sgabeblack@google.com setIntReg(int reg_idx, RegVal val) 27413557Sgabeblack@google.com { 27512106SRekai.GonzalezAlberquilla@arm.com setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val); 2769426SAndreas.Sandberg@ARM.com } 2772817Sksewell@umich.edu 27813557Sgabeblack@google.com virtual void 27913557Sgabeblack@google.com setFloatRegBits(int reg_idx, RegVal val) 28013557Sgabeblack@google.com { 28112106SRekai.GonzalezAlberquilla@arm.com setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass, 28212106SRekai.GonzalezAlberquilla@arm.com reg_idx)).index(), val); 2839426SAndreas.Sandberg@ARM.com } 2842817Sksewell@umich.edu 28513557Sgabeblack@google.com virtual void 28613557Sgabeblack@google.com setVecReg(const RegId& reg, const VecRegContainer& val) 28713557Sgabeblack@google.com { 28812109SRekai.GonzalezAlberquilla@arm.com setVecRegFlat(flattenRegId(reg).index(), val); 28912109SRekai.GonzalezAlberquilla@arm.com } 29012109SRekai.GonzalezAlberquilla@arm.com 29113557Sgabeblack@google.com virtual void 29213557Sgabeblack@google.com setVecElem(const RegId& reg, const VecElem& val) 29313557Sgabeblack@google.com { 29412109SRekai.GonzalezAlberquilla@arm.com setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val); 29512109SRekai.GonzalezAlberquilla@arm.com } 29612109SRekai.GonzalezAlberquilla@arm.com 29713557Sgabeblack@google.com virtual void 29813557Sgabeblack@google.com setCCReg(int reg_idx, CCReg val) 29913557Sgabeblack@google.com { 30012106SRekai.GonzalezAlberquilla@arm.com setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val); 3019920Syasuko.eckert@amd.com } 3029920Syasuko.eckert@amd.com 3037720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 3047720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 3057720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 3067720Sgblack@eecs.umich.edu 3077720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 3087720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 3097720Sgblack@eecs.umich.edu 3108733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val); 3118733Sgeoffrey.blake@arm.com 3122817Sksewell@umich.edu /** Reads this thread's PC. */ 3137720Sgblack@eecs.umich.edu virtual Addr instAddr() 3147720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 3152817Sksewell@umich.edu 3162817Sksewell@umich.edu /** Reads this thread's next PC. */ 3177720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 3187720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 3192817Sksewell@umich.edu 3207720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 3217720Sgblack@eecs.umich.edu virtual MicroPC microPC() 3227720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 3235259Sksewell@umich.edu 3242817Sksewell@umich.edu /** Reads a miscellaneous register. */ 32513557Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(int misc_reg) const 3265715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 3274172Ssaidi@eecs.umich.edu 3284172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 3294172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 33013557Sgabeblack@google.com virtual RegVal readMiscReg(int misc_reg) 3315715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 3322817Sksewell@umich.edu 3332817Sksewell@umich.edu /** Sets a misc. register. */ 33413582Sgabeblack@google.com virtual void setMiscRegNoEffect(int misc_reg, RegVal val); 3352817Sksewell@umich.edu 3362817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 3372817Sksewell@umich.edu * write might have as defined by the architecture. */ 33813582Sgabeblack@google.com virtual void setMiscReg(int misc_reg, RegVal val); 3392817Sksewell@umich.edu 34012106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const; 3416313Sgblack@eecs.umich.edu 3422817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 3432817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 3442817Sksewell@umich.edu virtual unsigned readStCondFailures() 3452817Sksewell@umich.edu { return thread->storeCondFailures; } 3462817Sksewell@umich.edu 3472817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 3482817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 3492817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 3502817Sksewell@umich.edu 3512817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 35211877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) 35311877Sbrandon.potter@amd.com { return cpu->syscall(callnum, thread->threadId(), fault); } 3542817Sksewell@umich.edu 3552817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 3562817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 3578777Sgblack@eecs.umich.edu 3585595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 35913557Sgabeblack@google.com virtual EndQuiesceEvent * 36013557Sgabeblack@google.com getQuiesceEvent() 3615595Sgblack@eecs.umich.edu { 3625595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 3635595Sgblack@eecs.umich.edu } 3649382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 3659382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 3669382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 3679382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 3689382SAli.Saidi@ARM.com */ 36913557Sgabeblack@google.com inline void 37013557Sgabeblack@google.com conditionalSquash() 3719382SAli.Saidi@ARM.com { 3729382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 3739382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 3749382SAli.Saidi@ARM.com } 3755595Sgblack@eecs.umich.edu 37613557Sgabeblack@google.com virtual RegVal readIntRegFlat(int idx); 37713557Sgabeblack@google.com virtual void setIntRegFlat(int idx, RegVal val); 3789426SAndreas.Sandberg@ARM.com 37913557Sgabeblack@google.com virtual RegVal readFloatRegBitsFlat(int idx); 38013557Sgabeblack@google.com virtual void setFloatRegBitsFlat(int idx, RegVal val); 3819920Syasuko.eckert@amd.com 38212109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecRegFlat(int idx) const; 38312109SRekai.GonzalezAlberquilla@arm.com /** Read vector register operand for modification, flat indexing. */ 38412109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecRegFlat(int idx); 38512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecRegFlat(int idx, const VecRegContainer& val); 38612109SRekai.GonzalezAlberquilla@arm.com 38712109SRekai.GonzalezAlberquilla@arm.com template <typename VecElem> 38813557Sgabeblack@google.com VecLaneT<VecElem, true> 38913557Sgabeblack@google.com readVecLaneFlat(int idx, int lId) const 39012109SRekai.GonzalezAlberquilla@arm.com { 39112109SRekai.GonzalezAlberquilla@arm.com return cpu->template readArchVecLane<VecElem>(idx, lId, 39212109SRekai.GonzalezAlberquilla@arm.com thread->threadId()); 39312109SRekai.GonzalezAlberquilla@arm.com } 39412109SRekai.GonzalezAlberquilla@arm.com 39512109SRekai.GonzalezAlberquilla@arm.com template <typename LD> 39612109SRekai.GonzalezAlberquilla@arm.com void setVecLaneFlat(int idx, int lId, const LD& val) 39712109SRekai.GonzalezAlberquilla@arm.com { 39812109SRekai.GonzalezAlberquilla@arm.com cpu->template setArchVecLane(idx, lId, thread->threadId(), val); 39912109SRekai.GonzalezAlberquilla@arm.com } 40012109SRekai.GonzalezAlberquilla@arm.com 40112109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElemFlat(const RegIndex& idx, 40212109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const; 40312109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 40412109SRekai.GonzalezAlberquilla@arm.com const VecElem& val); 40512109SRekai.GonzalezAlberquilla@arm.com 4069920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx); 4079920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val); 4082817Sksewell@umich.edu}; 4092817Sksewell@umich.edu 4102817Sksewell@umich.edu#endif 411