thread_context.hh revision 11877
12817Sksewell@umich.edu/* 29426SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152817Sksewell@umich.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 162817Sksewell@umich.edu * All rights reserved. 172817Sksewell@umich.edu * 182817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 192817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 202817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 212817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 222817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 232817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 242817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 252817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 262817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272817Sksewell@umich.edu * this software without specific prior written permission. 282817Sksewell@umich.edu * 292817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302817Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342817Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362817Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372817Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382817Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392817Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402817Sksewell@umich.edu * 412817Sksewell@umich.edu * Authors: Kevin Lim 422817Sksewell@umich.edu */ 432817Sksewell@umich.edu 442817Sksewell@umich.edu#ifndef __CPU_O3_THREAD_CONTEXT_HH__ 452817Sksewell@umich.edu#define __CPU_O3_THREAD_CONTEXT_HH__ 462817Sksewell@umich.edu 476658Snate@binkert.org#include "config/the_isa.hh" 488229Snate@binkert.org#include "cpu/o3/isa_specific.hh" 492935Sksewell@umich.edu#include "cpu/thread_context.hh" 502817Sksewell@umich.edu 512834Sksewell@umich.educlass EndQuiesceEvent; 522834Sksewell@umich.edunamespace Kernel { 532834Sksewell@umich.edu class Statistics; 548902Sandreas.hansson@arm.com} 552834Sksewell@umich.edu 562817Sksewell@umich.edu/** 572817Sksewell@umich.edu * Derived ThreadContext class for use with the O3CPU. It 582817Sksewell@umich.edu * provides the interface for any external objects to access a 592817Sksewell@umich.edu * single thread's state and some general CPU state. Any time 602817Sksewell@umich.edu * external objects try to update state through this interface, 612817Sksewell@umich.edu * the CPU will create an event to squash all in-flight 622817Sksewell@umich.edu * instructions in order to ensure state is maintained correctly. 632817Sksewell@umich.edu * It must be defined specifically for the O3CPU because 642817Sksewell@umich.edu * not all architectural state is located within the O3ThreadState 652817Sksewell@umich.edu * (such as the commit PC, and registers), and specific actions 662817Sksewell@umich.edu * must be taken when using this interface (such as squashing all 672817Sksewell@umich.edu * in-flight instructions when doing a write to this interface). 682817Sksewell@umich.edu */ 692817Sksewell@umich.edutemplate <class Impl> 702817Sksewell@umich.educlass O3ThreadContext : public ThreadContext 712817Sksewell@umich.edu{ 722817Sksewell@umich.edu public: 732817Sksewell@umich.edu typedef typename Impl::O3CPU O3CPU; 742817Sksewell@umich.edu 752817Sksewell@umich.edu /** Pointer to the CPU. */ 762817Sksewell@umich.edu O3CPU *cpu; 772817Sksewell@umich.edu 782817Sksewell@umich.edu /** Pointer to the thread state that this TC corrseponds to. */ 792817Sksewell@umich.edu O3ThreadState<Impl> *thread; 802817Sksewell@umich.edu 813784Sgblack@eecs.umich.edu /** Returns a pointer to the ITB. */ 826022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return cpu->itb; } 833784Sgblack@eecs.umich.edu 843784Sgblack@eecs.umich.edu /** Returns a pointer to the DTB. */ 856022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return cpu->dtb; } 863784Sgblack@eecs.umich.edu 878887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return NULL; } 888733Sgeoffrey.blake@arm.com 899023Sgblack@eecs.umich.edu TheISA::Decoder * 909023Sgblack@eecs.umich.edu getDecoderPtr() 919023Sgblack@eecs.umich.edu { 929023Sgblack@eecs.umich.edu return cpu->fetch.decoder[thread->threadId()]; 939023Sgblack@eecs.umich.edu } 948541Sgblack@eecs.umich.edu 952817Sksewell@umich.edu /** Returns a pointer to this CPU. */ 962817Sksewell@umich.edu virtual BaseCPU *getCpuPtr() { return cpu; } 972817Sksewell@umich.edu 982817Sksewell@umich.edu /** Reads this CPU's ID. */ 9910110Sandreas.hansson@arm.com virtual int cpuId() const { return cpu->cpuId(); } 1002817Sksewell@umich.edu 10110190Sakash.bagdia@arm.com /** Reads this CPU's Socket ID. */ 10210190Sakash.bagdia@arm.com virtual uint32_t socketId() const { return cpu->socketId(); } 10310190Sakash.bagdia@arm.com 10411005Sandreas.sandberg@arm.com virtual ContextID contextId() const { return thread->contextId(); } 1055714Shsul@eecs.umich.edu 1065714Shsul@eecs.umich.edu virtual void setContextId(int id) { thread->setContextId(id); } 1075714Shsul@eecs.umich.edu 1085715Shsul@eecs.umich.edu /** Returns this thread's ID number. */ 10910110Sandreas.hansson@arm.com virtual int threadId() const { return thread->threadId(); } 1105715Shsul@eecs.umich.edu virtual void setThreadId(int id) { return thread->setThreadId(id); } 1115715Shsul@eecs.umich.edu 1122817Sksewell@umich.edu /** Returns a pointer to the system. */ 1132817Sksewell@umich.edu virtual System *getSystemPtr() { return cpu->system; } 1142817Sksewell@umich.edu 1152817Sksewell@umich.edu /** Returns a pointer to this thread's kernel statistics. */ 1163548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() 1172817Sksewell@umich.edu { return thread->kernelStats; } 1182817Sksewell@umich.edu 1198541Sgblack@eecs.umich.edu /** Returns a pointer to this thread's process. */ 1208541Sgblack@eecs.umich.edu virtual Process *getProcessPtr() { return thread->getProcessPtr(); } 1218754Sgblack@eecs.umich.edu 1228852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); } 1232817Sksewell@umich.edu 1248852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy(); 1253675Sktlim@umich.edu 1268706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) 1278706Sandreas.hansson@arm.com { thread->initMemProxies(tc); } 1288799Sgblack@eecs.umich.edu 1298852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() 1308706Sandreas.hansson@arm.com { return thread->getMemProxy(); } 1312817Sksewell@umich.edu 1322817Sksewell@umich.edu /** Returns this thread's status. */ 1332817Sksewell@umich.edu virtual Status status() const { return thread->status(); } 1342817Sksewell@umich.edu 1352817Sksewell@umich.edu /** Sets this thread's status. */ 1362817Sksewell@umich.edu virtual void setStatus(Status new_status) 1372817Sksewell@umich.edu { thread->setStatus(new_status); } 1382817Sksewell@umich.edu 13910407Smitch.hayenga@arm.com /** Set the status to Active. */ 14010407Smitch.hayenga@arm.com virtual void activate(); 1412817Sksewell@umich.edu 1422817Sksewell@umich.edu /** Set the status to Suspended. */ 14310407Smitch.hayenga@arm.com virtual void suspend(); 1442817Sksewell@umich.edu 1452817Sksewell@umich.edu /** Set the status to Halted. */ 14610407Smitch.hayenga@arm.com virtual void halt(); 1472817Sksewell@umich.edu 1482817Sksewell@umich.edu /** Dumps the function profiling information. 1492817Sksewell@umich.edu * @todo: Implement. 1502817Sksewell@umich.edu */ 1512817Sksewell@umich.edu virtual void dumpFuncProfile(); 1528777Sgblack@eecs.umich.edu 1532817Sksewell@umich.edu /** Takes over execution of a thread from another CPU. */ 1542817Sksewell@umich.edu virtual void takeOverFrom(ThreadContext *old_context); 1552817Sksewell@umich.edu 1562817Sksewell@umich.edu /** Registers statistics associated with this TC. */ 1572817Sksewell@umich.edu virtual void regStats(const std::string &name); 1582817Sksewell@umich.edu 1592817Sksewell@umich.edu /** Reads the last tick that this thread was activated on. */ 1602817Sksewell@umich.edu virtual Tick readLastActivate(); 1612817Sksewell@umich.edu /** Reads the last tick that this thread was suspended on. */ 1622817Sksewell@umich.edu virtual Tick readLastSuspend(); 1632817Sksewell@umich.edu 1642817Sksewell@umich.edu /** Clears the function profiling information. */ 1652817Sksewell@umich.edu virtual void profileClear(); 1662817Sksewell@umich.edu /** Samples the function profiling information. */ 1672817Sksewell@umich.edu virtual void profileSample(); 1682817Sksewell@umich.edu 1692817Sksewell@umich.edu /** Copies the architectural registers from another TC into this TC. */ 1702817Sksewell@umich.edu virtual void copyArchRegs(ThreadContext *tc); 1712817Sksewell@umich.edu 1722817Sksewell@umich.edu /** Resets all architectural registers to 0. */ 1732817Sksewell@umich.edu virtual void clearArchRegs(); 1742817Sksewell@umich.edu 1752817Sksewell@umich.edu /** Reads an integer register. */ 1769426SAndreas.Sandberg@ARM.com virtual uint64_t readIntReg(int reg_idx) { 1779426SAndreas.Sandberg@ARM.com return readIntRegFlat(flattenIntIndex(reg_idx)); 1789426SAndreas.Sandberg@ARM.com } 1792817Sksewell@umich.edu 1809426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatReg(int reg_idx) { 1819426SAndreas.Sandberg@ARM.com return readFloatRegFlat(flattenFloatIndex(reg_idx)); 1829426SAndreas.Sandberg@ARM.com } 1832817Sksewell@umich.edu 1849426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBits(int reg_idx) { 1859426SAndreas.Sandberg@ARM.com return readFloatRegBitsFlat(flattenFloatIndex(reg_idx)); 1869426SAndreas.Sandberg@ARM.com } 1872817Sksewell@umich.edu 1889920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) { 1899920Syasuko.eckert@amd.com return readCCRegFlat(flattenCCIndex(reg_idx)); 1909920Syasuko.eckert@amd.com } 1919920Syasuko.eckert@amd.com 1922817Sksewell@umich.edu /** Sets an integer register to a value. */ 1939426SAndreas.Sandberg@ARM.com virtual void setIntReg(int reg_idx, uint64_t val) { 1949426SAndreas.Sandberg@ARM.com setIntRegFlat(flattenIntIndex(reg_idx), val); 1959426SAndreas.Sandberg@ARM.com } 1962817Sksewell@umich.edu 1979426SAndreas.Sandberg@ARM.com virtual void setFloatReg(int reg_idx, FloatReg val) { 1989426SAndreas.Sandberg@ARM.com setFloatRegFlat(flattenFloatIndex(reg_idx), val); 1999426SAndreas.Sandberg@ARM.com } 2002817Sksewell@umich.edu 2019426SAndreas.Sandberg@ARM.com virtual void setFloatRegBits(int reg_idx, FloatRegBits val) { 2029426SAndreas.Sandberg@ARM.com setFloatRegBitsFlat(flattenFloatIndex(reg_idx), val); 2039426SAndreas.Sandberg@ARM.com } 2042817Sksewell@umich.edu 2059920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) { 2069920Syasuko.eckert@amd.com setCCRegFlat(flattenCCIndex(reg_idx), val); 2079920Syasuko.eckert@amd.com } 2089920Syasuko.eckert@amd.com 2097720Sgblack@eecs.umich.edu /** Reads this thread's PC state. */ 2107720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() 2117720Sgblack@eecs.umich.edu { return cpu->pcState(thread->threadId()); } 2127720Sgblack@eecs.umich.edu 2137720Sgblack@eecs.umich.edu /** Sets this thread's PC state. */ 2147720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val); 2157720Sgblack@eecs.umich.edu 2168733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val); 2178733Sgeoffrey.blake@arm.com 2182817Sksewell@umich.edu /** Reads this thread's PC. */ 2197720Sgblack@eecs.umich.edu virtual Addr instAddr() 2207720Sgblack@eecs.umich.edu { return cpu->instAddr(thread->threadId()); } 2212817Sksewell@umich.edu 2222817Sksewell@umich.edu /** Reads this thread's next PC. */ 2237720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() 2247720Sgblack@eecs.umich.edu { return cpu->nextInstAddr(thread->threadId()); } 2252817Sksewell@umich.edu 2267720Sgblack@eecs.umich.edu /** Reads this thread's next PC. */ 2277720Sgblack@eecs.umich.edu virtual MicroPC microPC() 2287720Sgblack@eecs.umich.edu { return cpu->microPC(thread->threadId()); } 2295259Sksewell@umich.edu 2302817Sksewell@umich.edu /** Reads a miscellaneous register. */ 23110698Sandreas.hansson@arm.com virtual MiscReg readMiscRegNoEffect(int misc_reg) const 2325715Shsul@eecs.umich.edu { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); } 2334172Ssaidi@eecs.umich.edu 2344172Ssaidi@eecs.umich.edu /** Reads a misc. register, including any side-effects the 2354172Ssaidi@eecs.umich.edu * read might have as defined by the architecture. */ 2362817Sksewell@umich.edu virtual MiscReg readMiscReg(int misc_reg) 2375715Shsul@eecs.umich.edu { return cpu->readMiscReg(misc_reg, thread->threadId()); } 2382817Sksewell@umich.edu 2392817Sksewell@umich.edu /** Sets a misc. register. */ 2404172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val); 2412817Sksewell@umich.edu 2422817Sksewell@umich.edu /** Sets a misc. register, including any side-effects the 2432817Sksewell@umich.edu * write might have as defined by the architecture. */ 2444172Ssaidi@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val); 2452817Sksewell@umich.edu 2466313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg); 2476313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg); 2489920Syasuko.eckert@amd.com virtual int flattenCCIndex(int reg); 24910033SAli.Saidi@ARM.com virtual int flattenMiscIndex(int reg); 2506313Sgblack@eecs.umich.edu 2512817Sksewell@umich.edu /** Returns the number of consecutive store conditional failures. */ 2522817Sksewell@umich.edu // @todo: Figure out where these store cond failures should go. 2532817Sksewell@umich.edu virtual unsigned readStCondFailures() 2542817Sksewell@umich.edu { return thread->storeCondFailures; } 2552817Sksewell@umich.edu 2562817Sksewell@umich.edu /** Sets the number of consecutive store conditional failures. */ 2572817Sksewell@umich.edu virtual void setStCondFailures(unsigned sc_failures) 2582817Sksewell@umich.edu { thread->storeCondFailures = sc_failures; } 2592817Sksewell@umich.edu 2602817Sksewell@umich.edu /** Executes a syscall in SE mode. */ 26111877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) 26211877Sbrandon.potter@amd.com { return cpu->syscall(callnum, thread->threadId(), fault); } 2632817Sksewell@umich.edu 2642817Sksewell@umich.edu /** Reads the funcExeInst counter. */ 2652817Sksewell@umich.edu virtual Counter readFuncExeInst() { return thread->funcExeInst; } 2668777Sgblack@eecs.umich.edu 2675595Sgblack@eecs.umich.edu /** Returns pointer to the quiesce event. */ 2685595Sgblack@eecs.umich.edu virtual EndQuiesceEvent *getQuiesceEvent() 2695595Sgblack@eecs.umich.edu { 2705595Sgblack@eecs.umich.edu return this->thread->quiesceEvent; 2715595Sgblack@eecs.umich.edu } 2729382SAli.Saidi@ARM.com /** check if the cpu is currently in state update mode and squash if not. 2739382SAli.Saidi@ARM.com * This function will return true if a trap is pending or if a fault or 2749382SAli.Saidi@ARM.com * similar is currently writing to the thread context and doesn't want 2759382SAli.Saidi@ARM.com * reset all the state (see noSquashFromTC). 2769382SAli.Saidi@ARM.com */ 2779382SAli.Saidi@ARM.com inline void conditionalSquash() 2789382SAli.Saidi@ARM.com { 2799382SAli.Saidi@ARM.com if (!thread->trapPending && !thread->noSquashFromTC) 2809382SAli.Saidi@ARM.com cpu->squashFromTC(thread->threadId()); 2819382SAli.Saidi@ARM.com } 2825595Sgblack@eecs.umich.edu 2839426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx); 2849426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val); 2859426SAndreas.Sandberg@ARM.com 2869426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx); 2879426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val); 2889426SAndreas.Sandberg@ARM.com 2899426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx); 2909426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val); 2919920Syasuko.eckert@amd.com 2929920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx); 2939920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val); 2942817Sksewell@umich.edu}; 2952817Sksewell@umich.edu 2962817Sksewell@umich.edu#endif 297