scoreboard.hh revision 12105
12292SN/A/* 22689Sktlim@umich.edu * Copyright (c) 2005-2006 The Regents of The University of Michigan 39916Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 42292SN/A * All rights reserved. 52292SN/A * 62292SN/A * Redistribution and use in source and binary forms, with or without 72292SN/A * modification, are permitted provided that the following conditions are 82292SN/A * met: redistributions of source code must retain the above copyright 92292SN/A * notice, this list of conditions and the following disclaimer; 102292SN/A * redistributions in binary form must reproduce the above copyright 112292SN/A * notice, this list of conditions and the following disclaimer in the 122292SN/A * documentation and/or other materials provided with the distribution; 132292SN/A * neither the name of the copyright holders nor the names of its 142292SN/A * contributors may be used to endorse or promote products derived from 152292SN/A * this software without specific prior written permission. 162292SN/A * 172292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282689Sktlim@umich.edu * 292689Sktlim@umich.edu * Authors: Korey Sewell 302689Sktlim@umich.edu * Kevin Lim 319916Ssteve.reinhardt@amd.com * Steve Reinhardt 322292SN/A */ 332292SN/A 342292SN/A#ifndef __CPU_O3_SCOREBOARD_HH__ 352292SN/A#define __CPU_O3_SCOREBOARD_HH__ 362292SN/A 372292SN/A#include <iostream> 382292SN/A#include <utility> 392292SN/A#include <vector> 408229Snate@binkert.org 412292SN/A#include "base/trace.hh" 429916Ssteve.reinhardt@amd.com#include "config/the_isa.hh" 432292SN/A#include "cpu/o3/comm.hh" 449916Ssteve.reinhardt@amd.com#include "debug/Scoreboard.hh" 452292SN/A 462292SN/A/** 479916Ssteve.reinhardt@amd.com * Implements a simple scoreboard to track which registers are 489916Ssteve.reinhardt@amd.com * ready. This class operates on the unified physical register space, 4912105Snathanael.premillieu@arm.com * because the different classes of registers do not need to be distinguished. 5012105Snathanael.premillieu@arm.com * Registers being part of a fixed mapping are always considered ready. 512292SN/A */ 522292SN/Aclass Scoreboard 532292SN/A{ 549916Ssteve.reinhardt@amd.com private: 559916Ssteve.reinhardt@amd.com /** The object name, for DPRINTF. We have to declare this 569916Ssteve.reinhardt@amd.com * explicitly because Scoreboard is not a SimObject. */ 579916Ssteve.reinhardt@amd.com const std::string _name; 589916Ssteve.reinhardt@amd.com 599916Ssteve.reinhardt@amd.com /** Scoreboard of physical integer registers, saying whether or not they 609916Ssteve.reinhardt@amd.com * are ready. */ 619916Ssteve.reinhardt@amd.com std::vector<bool> regScoreBoard; 629916Ssteve.reinhardt@amd.com 639916Ssteve.reinhardt@amd.com /** The number of actual physical registers */ 649916Ssteve.reinhardt@amd.com unsigned numPhysRegs; 659916Ssteve.reinhardt@amd.com 662292SN/A public: 672292SN/A /** Constructs a scoreboard. 689916Ssteve.reinhardt@amd.com * @param _numPhysicalRegs Number of physical registers. 692292SN/A * @param _numMiscRegs Number of miscellaneous registers. 702292SN/A */ 719916Ssteve.reinhardt@amd.com Scoreboard(const std::string &_my_name, 7212105Snathanael.premillieu@arm.com unsigned _numPhysicalRegs); 732292SN/A 742292SN/A /** Destructor. */ 752292SN/A ~Scoreboard() {} 762292SN/A 772292SN/A /** Returns the name of the scoreboard. */ 789916Ssteve.reinhardt@amd.com std::string name() const { return _name; }; 792292SN/A 802292SN/A /** Checks if the register is ready. */ 8112105Snathanael.premillieu@arm.com bool getReg(PhysRegIdPtr phys_reg) const 829916Ssteve.reinhardt@amd.com { 8312105Snathanael.premillieu@arm.com assert(phys_reg->flatIdx < numPhysRegs); 849916Ssteve.reinhardt@amd.com 8512105Snathanael.premillieu@arm.com if (phys_reg->isFixedMapping()) { 8612105Snathanael.premillieu@arm.com // Fixed mapping regs are always ready 879916Ssteve.reinhardt@amd.com return true; 889916Ssteve.reinhardt@amd.com } 899916Ssteve.reinhardt@amd.com 9012105Snathanael.premillieu@arm.com bool ready = regScoreBoard[phys_reg->flatIdx]; 919916Ssteve.reinhardt@amd.com 9212105Snathanael.premillieu@arm.com if (phys_reg->isZeroReg()) 939916Ssteve.reinhardt@amd.com assert(ready); 949916Ssteve.reinhardt@amd.com 959916Ssteve.reinhardt@amd.com return ready; 969916Ssteve.reinhardt@amd.com } 972292SN/A 982292SN/A /** Sets the register as ready. */ 9912105Snathanael.premillieu@arm.com void setReg(PhysRegIdPtr phys_reg) 1009916Ssteve.reinhardt@amd.com { 10112105Snathanael.premillieu@arm.com assert(phys_reg->flatIdx < numPhysRegs); 1029916Ssteve.reinhardt@amd.com 10312105Snathanael.premillieu@arm.com if (phys_reg->isFixedMapping()) { 10412105Snathanael.premillieu@arm.com // Fixed mapping regs are always ready, ignore attempts to change 10512105Snathanael.premillieu@arm.com // that 1069916Ssteve.reinhardt@amd.com return; 1079916Ssteve.reinhardt@amd.com } 1089916Ssteve.reinhardt@amd.com 10912105Snathanael.premillieu@arm.com DPRINTF(Scoreboard, "Setting reg %i (%s) as ready\n", phys_reg->regIdx, 11012105Snathanael.premillieu@arm.com RegClassStrings[phys_reg->regClass]); 1119916Ssteve.reinhardt@amd.com 11212105Snathanael.premillieu@arm.com regScoreBoard[phys_reg->flatIdx] = true; 1139916Ssteve.reinhardt@amd.com } 1142292SN/A 1152292SN/A /** Sets the register as not ready. */ 11612105Snathanael.premillieu@arm.com void unsetReg(PhysRegIdPtr phys_reg) 1179916Ssteve.reinhardt@amd.com { 11812105Snathanael.premillieu@arm.com assert(phys_reg->flatIdx < numPhysRegs); 1192292SN/A 12012105Snathanael.premillieu@arm.com if (phys_reg->isFixedMapping()) { 12112105Snathanael.premillieu@arm.com // Fixed mapping regs are always ready, ignore attempts to 12212105Snathanael.premillieu@arm.com // change that 1239916Ssteve.reinhardt@amd.com return; 1249916Ssteve.reinhardt@amd.com } 1252292SN/A 1269916Ssteve.reinhardt@amd.com // zero reg should never be marked unready 12712105Snathanael.premillieu@arm.com if (phys_reg->isZeroReg()) 1289916Ssteve.reinhardt@amd.com return; 1292292SN/A 13012105Snathanael.premillieu@arm.com regScoreBoard[phys_reg->flatIdx] = false; 1317699Sgblack@eecs.umich.edu } 1327699Sgblack@eecs.umich.edu 1332292SN/A}; 1342292SN/A 1352292SN/A#endif 136