rob_impl.hh revision 9944
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412831Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 449944Smatt.horsnell@ARM.com#ifndef __CPU_O3_ROB_IMPL_HH__ 459944Smatt.horsnell@ARM.com#define __CPU_O3_ROB_IMPL_HH__ 469944Smatt.horsnell@ARM.com 476221Snate@binkert.org#include <list> 486221Snate@binkert.org 491717SN/A#include "cpu/o3/rob.hh" 508232Snate@binkert.org#include "debug/Fetch.hh" 518232Snate@binkert.org#include "debug/ROB.hh" 521060SN/A 536221Snate@binkert.orgusing namespace std; 542292SN/A 551061SN/Atemplate <class Impl> 564329Sktlim@umich.eduROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth, 572980Sgblack@eecs.umich.edu std::string _smtROBPolicy, unsigned _smtROBThreshold, 586221Snate@binkert.org ThreadID _numThreads) 594329Sktlim@umich.edu : cpu(_cpu), 604329Sktlim@umich.edu numEntries(_numEntries), 611060SN/A squashWidth(_squashWidth), 621060SN/A numInstsInROB(0), 632292SN/A numThreads(_numThreads) 641060SN/A{ 652980Sgblack@eecs.umich.edu std::string policy = _smtROBPolicy; 662292SN/A 672292SN/A //Convert string to lowercase 682292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 692292SN/A (int(*)(int)) tolower); 702292SN/A 712292SN/A //Figure out rob policy 722292SN/A if (policy == "dynamic") { 732292SN/A robPolicy = Dynamic; 742292SN/A 752292SN/A //Set Max Entries to Total ROB Capacity 766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 776221Snate@binkert.org maxEntries[tid] = numEntries; 782292SN/A } 792292SN/A 802292SN/A } else if (policy == "partitioned") { 812292SN/A robPolicy = Partitioned; 824329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 832292SN/A 842292SN/A //@todo:make work if part_amt doesnt divide evenly. 852292SN/A int part_amt = numEntries / numThreads; 862292SN/A 872292SN/A //Divide ROB up evenly 886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 896221Snate@binkert.org maxEntries[tid] = part_amt; 902292SN/A } 912292SN/A 922292SN/A } else if (policy == "threshold") { 932292SN/A robPolicy = Threshold; 944329Sktlim@umich.edu DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 952292SN/A 962292SN/A int threshold = _smtROBThreshold;; 972292SN/A 982292SN/A //Divide up by threshold amount 996221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1006221Snate@binkert.org maxEntries[tid] = threshold; 1012292SN/A } 1022292SN/A } else { 1032292SN/A assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 1042292SN/A "Partitioned, Threshold}"); 1052292SN/A } 1061060SN/A 1079444SAndreas.Sandberg@ARM.com resetState(); 1089444SAndreas.Sandberg@ARM.com} 1099444SAndreas.Sandberg@ARM.com 1109444SAndreas.Sandberg@ARM.comtemplate <class Impl> 1119444SAndreas.Sandberg@ARM.comvoid 1129444SAndreas.Sandberg@ARM.comROB<Impl>::resetState() 1139444SAndreas.Sandberg@ARM.com{ 1149444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 1159444SAndreas.Sandberg@ARM.com doneSquashing[tid] = true; 1169444SAndreas.Sandberg@ARM.com threadEntries[tid] = 0; 1176221Snate@binkert.org squashIt[tid] = instList[tid].end(); 1189444SAndreas.Sandberg@ARM.com squashedSeqNum[tid] = 0; 1192292SN/A } 1209444SAndreas.Sandberg@ARM.com numInstsInROB = 0; 1211060SN/A 1222292SN/A // Initialize the "universal" ROB head & tail point to invalid 1232292SN/A // pointers 1242292SN/A head = instList[0].end(); 1252292SN/A tail = instList[0].end(); 1262292SN/A} 1272292SN/A 1282292SN/Atemplate <class Impl> 1294329Sktlim@umich.edustd::string 1304329Sktlim@umich.eduROB<Impl>::name() const 1314329Sktlim@umich.edu{ 1324329Sktlim@umich.edu return cpu->name() + ".rob"; 1334329Sktlim@umich.edu} 1344329Sktlim@umich.edu 1354329Sktlim@umich.edutemplate <class Impl> 1362292SN/Avoid 1376221Snate@binkert.orgROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 1382292SN/A{ 1392292SN/A DPRINTF(ROB, "Setting active threads list pointer.\n"); 1402292SN/A activeThreads = at_ptr; 1412292SN/A} 1422292SN/A 1432307SN/Atemplate <class Impl> 1442307SN/Avoid 1459444SAndreas.Sandberg@ARM.comROB<Impl>::drainSanityCheck() const 1462307SN/A{ 1479444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) 1489444SAndreas.Sandberg@ARM.com assert(instList[tid].empty()); 1499444SAndreas.Sandberg@ARM.com assert(isEmpty()); 1502307SN/A} 1512307SN/A 1522307SN/Atemplate <class Impl> 1532307SN/Avoid 1542307SN/AROB<Impl>::takeOverFrom() 1552307SN/A{ 1569444SAndreas.Sandberg@ARM.com resetState(); 1572307SN/A} 1582292SN/A 1592292SN/Atemplate <class Impl> 1602292SN/Avoid 1612292SN/AROB<Impl>::resetEntries() 1622292SN/A{ 1632292SN/A if (robPolicy != Dynamic || numThreads > 1) { 1643867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 1652292SN/A 1666221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 1676221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 1682292SN/A 1693867Sbinkertn@umich.edu while (threads != end) { 1706221Snate@binkert.org ThreadID tid = *threads++; 1713867Sbinkertn@umich.edu 1722292SN/A if (robPolicy == Partitioned) { 1733867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 1742292SN/A } else if (robPolicy == Threshold && active_threads == 1) { 1753867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 1762292SN/A } 1772292SN/A } 1782292SN/A } 1792292SN/A} 1802292SN/A 1812292SN/Atemplate <class Impl> 1822292SN/Aint 1836221Snate@binkert.orgROB<Impl>::entryAmount(ThreadID num_threads) 1842292SN/A{ 1852292SN/A if (robPolicy == Partitioned) { 1862292SN/A return numEntries / num_threads; 1872292SN/A } else { 1882292SN/A return 0; 1892292SN/A } 1901060SN/A} 1911060SN/A 1921061SN/Atemplate <class Impl> 1931060SN/Aint 1941060SN/AROB<Impl>::countInsts() 1951060SN/A{ 1966221Snate@binkert.org int total = 0; 1971061SN/A 1986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 1996221Snate@binkert.org total += countInsts(tid); 2001060SN/A 2012292SN/A return total; 2022292SN/A} 2031060SN/A 2042292SN/Atemplate <class Impl> 2052292SN/Aint 2066221Snate@binkert.orgROB<Impl>::countInsts(ThreadID tid) 2072292SN/A{ 2082292SN/A return instList[tid].size(); 2091060SN/A} 2101060SN/A 2111061SN/Atemplate <class Impl> 2121060SN/Avoid 2131061SN/AROB<Impl>::insertInst(DynInstPtr &inst) 2141060SN/A{ 2151060SN/A assert(inst); 2161060SN/A 2177897Shestness@cs.utexas.edu robWrites++; 2187897Shestness@cs.utexas.edu 2197720Sgblack@eecs.umich.edu DPRINTF(ROB, "Adding inst PC %s to the ROB.\n", inst->pcState()); 2201060SN/A 2211060SN/A assert(numInstsInROB != numEntries); 2221060SN/A 2236221Snate@binkert.org ThreadID tid = inst->threadNumber; 2241060SN/A 2252292SN/A instList[tid].push_back(inst); 2262292SN/A 2272292SN/A //Set Up head iterator if this is the 1st instruction in the ROB 2282292SN/A if (numInstsInROB == 0) { 2292292SN/A head = instList[tid].begin(); 2302292SN/A assert((*head) == inst); 2311060SN/A } 2321060SN/A 2332292SN/A //Must Decrement for iterator to actually be valid since __.end() 2342292SN/A //actually points to 1 after the last inst 2352292SN/A tail = instList[tid].end(); 2362292SN/A tail--; 2372292SN/A 2382292SN/A inst->setInROB(); 2392292SN/A 2402292SN/A ++numInstsInROB; 2412292SN/A ++threadEntries[tid]; 2422292SN/A 2431060SN/A assert((*tail) == inst); 2441060SN/A 2452292SN/A DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 2461060SN/A} 2471060SN/A 2482292SN/Atemplate <class Impl> 2492292SN/Avoid 2506221Snate@binkert.orgROB<Impl>::retireHead(ThreadID tid) 2512292SN/A{ 2527897Shestness@cs.utexas.edu robWrites++; 2537897Shestness@cs.utexas.edu 2541061SN/A assert(numInstsInROB > 0); 2551060SN/A 2561060SN/A // Get the head ROB instruction. 2572292SN/A InstIt head_it = instList[tid].begin(); 2581060SN/A 2592292SN/A DynInstPtr head_inst = (*head_it); 2601858SN/A 2611060SN/A assert(head_inst->readyToCommit()); 2621060SN/A 2632292SN/A DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 2647720Sgblack@eecs.umich.edu "instruction PC %s, [sn:%lli]\n", tid, head_inst->pcState(), 2651060SN/A head_inst->seqNum); 2661060SN/A 2671060SN/A --numInstsInROB; 2682292SN/A --threadEntries[tid]; 2691060SN/A 2702731Sktlim@umich.edu head_inst->clearInROB(); 2712292SN/A head_inst->setCommitted(); 2722292SN/A 2732292SN/A instList[tid].erase(head_it); 2742292SN/A 2752292SN/A //Update "Global" Head of ROB 2762292SN/A updateHead(); 2772292SN/A 2782329SN/A // @todo: A special case is needed if the instruction being 2792329SN/A // retired is the only instruction in the ROB; otherwise the tail 2802329SN/A // iterator will become invalidated. 2811681SN/A cpu->removeFrontInst(head_inst); 2821060SN/A} 2832292SN/A 2842292SN/Atemplate <class Impl> 2852292SN/Abool 2866221Snate@binkert.orgROB<Impl>::isHeadReady(ThreadID tid) 2872292SN/A{ 2887897Shestness@cs.utexas.edu robReads++; 2892292SN/A if (threadEntries[tid] != 0) { 2902292SN/A return instList[tid].front()->readyToCommit(); 2912292SN/A } 2922292SN/A 2932292SN/A return false; 2942292SN/A} 2952292SN/A 2962292SN/Atemplate <class Impl> 2972292SN/Abool 2982292SN/AROB<Impl>::canCommit() 2992292SN/A{ 3002292SN/A //@todo: set ActiveThreads through ROB or CPU 3016221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3026221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3032292SN/A 3043867Sbinkertn@umich.edu while (threads != end) { 3056221Snate@binkert.org ThreadID tid = *threads++; 3062292SN/A 3072292SN/A if (isHeadReady(tid)) { 3082292SN/A return true; 3092292SN/A } 3101060SN/A } 3111060SN/A 3121060SN/A return false; 3131060SN/A} 3141060SN/A 3151061SN/Atemplate <class Impl> 3161060SN/Aunsigned 3171060SN/AROB<Impl>::numFreeEntries() 3181060SN/A{ 3191060SN/A return numEntries - numInstsInROB; 3201060SN/A} 3211060SN/A 3221061SN/Atemplate <class Impl> 3232292SN/Aunsigned 3246221Snate@binkert.orgROB<Impl>::numFreeEntries(ThreadID tid) 3251060SN/A{ 3262292SN/A return maxEntries[tid] - threadEntries[tid]; 3271060SN/A} 3281060SN/A 3291061SN/Atemplate <class Impl> 3301060SN/Avoid 3316221Snate@binkert.orgROB<Impl>::doSquash(ThreadID tid) 3321060SN/A{ 3337897Shestness@cs.utexas.edu robWrites++; 3342292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 3352877Sksewell@umich.edu tid, squashedSeqNum[tid]); 3361858SN/A 3372292SN/A assert(squashIt[tid] != instList[tid].end()); 3382292SN/A 3392877Sksewell@umich.edu if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 3402292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3412292SN/A tid); 3422292SN/A 3432292SN/A squashIt[tid] = instList[tid].end(); 3442292SN/A 3452292SN/A doneSquashing[tid] = true; 3462292SN/A return; 3472292SN/A } 3482292SN/A 3492292SN/A bool robTailUpdate = false; 3501858SN/A 3511858SN/A for (int numSquashed = 0; 3522292SN/A numSquashed < squashWidth && 3532292SN/A squashIt[tid] != instList[tid].end() && 3542877Sksewell@umich.edu (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 3551858SN/A ++numSquashed) 3561858SN/A { 3577720Sgblack@eecs.umich.edu DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %s, seq num %i.\n", 3582292SN/A (*squashIt[tid])->threadNumber, 3597720Sgblack@eecs.umich.edu (*squashIt[tid])->pcState(), 3602292SN/A (*squashIt[tid])->seqNum); 3611858SN/A 3621858SN/A // Mark the instruction as squashed, and ready to commit so that 3631858SN/A // it can drain out of the pipeline. 3642292SN/A (*squashIt[tid])->setSquashed(); 3651858SN/A 3662292SN/A (*squashIt[tid])->setCanCommit(); 3671858SN/A 3682292SN/A 3692292SN/A if (squashIt[tid] == instList[tid].begin()) { 3702292SN/A DPRINTF(ROB, "Reached head of instruction list while " 3711858SN/A "squashing.\n"); 3721858SN/A 3732292SN/A squashIt[tid] = instList[tid].end(); 3741858SN/A 3752292SN/A doneSquashing[tid] = true; 3761858SN/A 3771858SN/A return; 3781858SN/A } 3791858SN/A 3802292SN/A InstIt tail_thread = instList[tid].end(); 3812292SN/A tail_thread--; 3822292SN/A 3832292SN/A if ((*squashIt[tid]) == (*tail_thread)) 3842292SN/A robTailUpdate = true; 3852292SN/A 3862292SN/A squashIt[tid]--; 3871858SN/A } 3881858SN/A 3891858SN/A 3901858SN/A // Check if ROB is done squashing. 3912877Sksewell@umich.edu if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 3922292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3932292SN/A tid); 3941858SN/A 3952292SN/A squashIt[tid] = instList[tid].end(); 3961858SN/A 3972292SN/A doneSquashing[tid] = true; 3982292SN/A } 3992292SN/A 4002292SN/A if (robTailUpdate) { 4012292SN/A updateTail(); 4022292SN/A } 4032292SN/A} 4042292SN/A 4052292SN/A 4062292SN/Atemplate <class Impl> 4072292SN/Avoid 4082292SN/AROB<Impl>::updateHead() 4092292SN/A{ 4102292SN/A InstSeqNum lowest_num = 0; 4112292SN/A bool first_valid = true; 4122292SN/A 4132292SN/A // @todo: set ActiveThreads through ROB or CPU 4146221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4156221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4162292SN/A 4173867Sbinkertn@umich.edu while (threads != end) { 4186221Snate@binkert.org ThreadID tid = *threads++; 4192292SN/A 4203867Sbinkertn@umich.edu if (instList[tid].empty()) 4212292SN/A continue; 4222292SN/A 4232292SN/A if (first_valid) { 4243867Sbinkertn@umich.edu head = instList[tid].begin(); 4252292SN/A lowest_num = (*head)->seqNum; 4262292SN/A first_valid = false; 4272292SN/A continue; 4282292SN/A } 4292292SN/A 4303867Sbinkertn@umich.edu InstIt head_thread = instList[tid].begin(); 4312292SN/A 4322292SN/A DynInstPtr head_inst = (*head_thread); 4332292SN/A 4342292SN/A assert(head_inst != 0); 4352292SN/A 4362292SN/A if (head_inst->seqNum < lowest_num) { 4372292SN/A head = head_thread; 4382292SN/A lowest_num = head_inst->seqNum; 4392292SN/A } 4402292SN/A } 4412292SN/A 4422292SN/A if (first_valid) { 4432292SN/A head = instList[0].end(); 4442292SN/A } 4452292SN/A 4462292SN/A} 4472292SN/A 4482292SN/Atemplate <class Impl> 4492292SN/Avoid 4502292SN/AROB<Impl>::updateTail() 4512292SN/A{ 4522292SN/A tail = instList[0].end(); 4532292SN/A bool first_valid = true; 4542292SN/A 4556221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4566221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4572292SN/A 4583867Sbinkertn@umich.edu while (threads != end) { 4596221Snate@binkert.org ThreadID tid = *threads++; 4602292SN/A 4612292SN/A if (instList[tid].empty()) { 4622292SN/A continue; 4632292SN/A } 4642292SN/A 4652292SN/A // If this is the first valid then assign w/out 4662292SN/A // comparison 4672292SN/A if (first_valid) { 4682292SN/A tail = instList[tid].end(); 4692292SN/A tail--; 4702292SN/A first_valid = false; 4712292SN/A continue; 4722292SN/A } 4732292SN/A 4742292SN/A // Assign new tail if this thread's tail is younger 4752292SN/A // than our current "tail high" 4762292SN/A InstIt tail_thread = instList[tid].end(); 4772292SN/A tail_thread--; 4782292SN/A 4792292SN/A if ((*tail_thread)->seqNum > (*tail)->seqNum) { 4802292SN/A tail = tail_thread; 4812292SN/A } 4822292SN/A } 4832292SN/A} 4842292SN/A 4852292SN/A 4862292SN/Atemplate <class Impl> 4872292SN/Avoid 4886221Snate@binkert.orgROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) 4892292SN/A{ 4902292SN/A if (isEmpty()) { 4912292SN/A DPRINTF(ROB, "Does not need to squash due to being empty " 4922292SN/A "[sn:%i]\n", 4932292SN/A squash_num); 4942292SN/A 4952292SN/A return; 4962292SN/A } 4972292SN/A 4982292SN/A DPRINTF(ROB, "Starting to squash within the ROB.\n"); 4992292SN/A 5002292SN/A robStatus[tid] = ROBSquashing; 5012292SN/A 5022292SN/A doneSquashing[tid] = false; 5031060SN/A 5042877Sksewell@umich.edu squashedSeqNum[tid] = squash_num; 5051060SN/A 5062292SN/A if (!instList[tid].empty()) { 5072292SN/A InstIt tail_thread = instList[tid].end(); 5082292SN/A tail_thread--; 5091060SN/A 5102292SN/A squashIt[tid] = tail_thread; 5111060SN/A 5122292SN/A doSquash(tid); 5131858SN/A } 5141060SN/A} 5152877Sksewell@umich.edu 5162292SN/Atemplate <class Impl> 5172292SN/Atypename Impl::DynInstPtr 5186221Snate@binkert.orgROB<Impl>::readHeadInst(ThreadID tid) 5192292SN/A{ 5202292SN/A if (threadEntries[tid] != 0) { 5212292SN/A InstIt head_thread = instList[tid].begin(); 5221060SN/A 5232292SN/A assert((*head_thread)->isInROB()==true); 5241858SN/A 5252292SN/A return *head_thread; 5262292SN/A } else { 5272292SN/A return dummyInst; 5282292SN/A } 5291858SN/A} 5302877Sksewell@umich.edu 5312292SN/Atemplate <class Impl> 5322292SN/Atypename Impl::DynInstPtr 5336221Snate@binkert.orgROB<Impl>::readTailInst(ThreadID tid) 5342292SN/A{ 5352292SN/A InstIt tail_thread = instList[tid].end(); 5362292SN/A tail_thread--; 5372292SN/A 5382292SN/A return *tail_thread; 5392292SN/A} 5402292SN/A 5417897Shestness@cs.utexas.edutemplate <class Impl> 5427897Shestness@cs.utexas.eduvoid 5437897Shestness@cs.utexas.eduROB<Impl>::regStats() 5447897Shestness@cs.utexas.edu{ 5457897Shestness@cs.utexas.edu using namespace Stats; 5467897Shestness@cs.utexas.edu robReads 5477897Shestness@cs.utexas.edu .name(name() + ".rob_reads") 5487897Shestness@cs.utexas.edu .desc("The number of ROB reads"); 5497897Shestness@cs.utexas.edu 5507897Shestness@cs.utexas.edu robWrites 5517897Shestness@cs.utexas.edu .name(name() + ".rob_writes") 5527897Shestness@cs.utexas.edu .desc("The number of ROB writes"); 5537897Shestness@cs.utexas.edu} 5547897Shestness@cs.utexas.edu 5558822Snilay@cs.wisc.edutemplate <class Impl> 5568822Snilay@cs.wisc.edutypename Impl::DynInstPtr 5578822Snilay@cs.wisc.eduROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst) 5588822Snilay@cs.wisc.edu{ 5598822Snilay@cs.wisc.edu for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) { 5608822Snilay@cs.wisc.edu if ((*it)->seqNum == squash_inst) { 5618822Snilay@cs.wisc.edu return *it; 5628822Snilay@cs.wisc.edu } 5638822Snilay@cs.wisc.edu } 5648822Snilay@cs.wisc.edu return NULL; 5658822Snilay@cs.wisc.edu} 5669944Smatt.horsnell@ARM.com 5679944Smatt.horsnell@ARM.com#endif//__CPU_O3_ROB_IMPL_HH__ 568