rob_impl.hh revision 4329
11689SN/A/*
22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
292831Sksewell@umich.edu *          Korey Sewell
301689SN/A */
311689SN/A
321858SN/A#include "config/full_system.hh"
331717SN/A#include "cpu/o3/rob.hh"
341060SN/A
352980Sgblack@eecs.umich.edu#include <list>
362292SN/A
371061SN/Atemplate <class Impl>
384329Sktlim@umich.eduROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
392980Sgblack@eecs.umich.edu               std::string _smtROBPolicy, unsigned _smtROBThreshold,
402292SN/A               unsigned _numThreads)
414329Sktlim@umich.edu    : cpu(_cpu),
424329Sktlim@umich.edu      numEntries(_numEntries),
431060SN/A      squashWidth(_squashWidth),
441060SN/A      numInstsInROB(0),
452292SN/A      numThreads(_numThreads)
461060SN/A{
472292SN/A    for (int tid=0; tid  < numThreads; tid++) {
482877Sksewell@umich.edu        squashedSeqNum[tid] = 0;
492292SN/A        doneSquashing[tid] = true;
502292SN/A        threadEntries[tid] = 0;
512292SN/A    }
522292SN/A
532980Sgblack@eecs.umich.edu    std::string policy = _smtROBPolicy;
542292SN/A
552292SN/A    //Convert string to lowercase
562292SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
572292SN/A                   (int(*)(int)) tolower);
582292SN/A
592292SN/A    //Figure out rob policy
602292SN/A    if (policy == "dynamic") {
612292SN/A        robPolicy = Dynamic;
622292SN/A
632292SN/A        //Set Max Entries to Total ROB Capacity
642292SN/A        for (int i = 0; i < numThreads; i++) {
652292SN/A            maxEntries[i]=numEntries;
662292SN/A        }
672292SN/A
682292SN/A    } else if (policy == "partitioned") {
692292SN/A        robPolicy = Partitioned;
704329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
712292SN/A
722292SN/A        //@todo:make work if part_amt doesnt divide evenly.
732292SN/A        int part_amt = numEntries / numThreads;
742292SN/A
752292SN/A        //Divide ROB up evenly
762292SN/A        for (int i = 0; i < numThreads; i++) {
772292SN/A            maxEntries[i]=part_amt;
782292SN/A        }
792292SN/A
802292SN/A    } else if (policy == "threshold") {
812292SN/A        robPolicy = Threshold;
824329Sktlim@umich.edu        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
832292SN/A
842292SN/A        int threshold =  _smtROBThreshold;;
852292SN/A
862292SN/A        //Divide up by threshold amount
872292SN/A        for (int i = 0; i < numThreads; i++) {
882292SN/A            maxEntries[i]=threshold;
892292SN/A        }
902292SN/A    } else {
912292SN/A        assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
922292SN/A                    "Partitioned, Threshold}");
932292SN/A    }
941060SN/A
952292SN/A    // Set the per-thread iterators to the end of the instruction list.
962292SN/A    for (int i=0; i < numThreads;i++) {
972292SN/A        squashIt[i] = instList[i].end();
982292SN/A    }
991060SN/A
1002292SN/A    // Initialize the "universal" ROB head & tail point to invalid
1012292SN/A    // pointers
1022292SN/A    head = instList[0].end();
1032292SN/A    tail = instList[0].end();
1042292SN/A}
1052292SN/A
1062292SN/Atemplate <class Impl>
1074329Sktlim@umich.edustd::string
1084329Sktlim@umich.eduROB<Impl>::name() const
1094329Sktlim@umich.edu{
1104329Sktlim@umich.edu    return cpu->name() + ".rob";
1114329Sktlim@umich.edu}
1124329Sktlim@umich.edu
1134329Sktlim@umich.edutemplate <class Impl>
1142292SN/Avoid
1152980Sgblack@eecs.umich.eduROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
1162292SN/A{
1172292SN/A    DPRINTF(ROB, "Setting active threads list pointer.\n");
1182292SN/A    activeThreads = at_ptr;
1192292SN/A}
1202292SN/A
1212307SN/Atemplate <class Impl>
1222307SN/Avoid
1232307SN/AROB<Impl>::switchOut()
1242307SN/A{
1252307SN/A    for (int tid = 0; tid < numThreads; tid++) {
1262307SN/A        instList[tid].clear();
1272307SN/A    }
1282307SN/A}
1292307SN/A
1302307SN/Atemplate <class Impl>
1312307SN/Avoid
1322307SN/AROB<Impl>::takeOverFrom()
1332307SN/A{
1342307SN/A    for (int tid=0; tid  < numThreads; tid++) {
1352307SN/A        doneSquashing[tid] = true;
1362307SN/A        threadEntries[tid] = 0;
1372307SN/A        squashIt[tid] = instList[tid].end();
1382307SN/A    }
1392307SN/A    numInstsInROB = 0;
1402307SN/A
1412307SN/A    // Initialize the "universal" ROB head & tail point to invalid
1422307SN/A    // pointers
1432307SN/A    head = instList[0].end();
1442307SN/A    tail = instList[0].end();
1452307SN/A}
1462292SN/A
1472292SN/Atemplate <class Impl>
1482292SN/Avoid
1492292SN/AROB<Impl>::resetEntries()
1502292SN/A{
1512292SN/A    if (robPolicy != Dynamic || numThreads > 1) {
1523867Sbinkertn@umich.edu        int active_threads = activeThreads->size();
1532292SN/A
1543867Sbinkertn@umich.edu        std::list<unsigned>::iterator threads = activeThreads->begin();
1553867Sbinkertn@umich.edu        std::list<unsigned>::iterator end = activeThreads->end();
1562292SN/A
1573867Sbinkertn@umich.edu        while (threads != end) {
1583867Sbinkertn@umich.edu            unsigned tid = *threads++;
1593867Sbinkertn@umich.edu
1602292SN/A            if (robPolicy == Partitioned) {
1613867Sbinkertn@umich.edu                maxEntries[tid] = numEntries / active_threads;
1622292SN/A            } else if (robPolicy == Threshold && active_threads == 1) {
1633867Sbinkertn@umich.edu                maxEntries[tid] = numEntries;
1642292SN/A            }
1652292SN/A        }
1662292SN/A    }
1672292SN/A}
1682292SN/A
1692292SN/Atemplate <class Impl>
1702292SN/Aint
1712292SN/AROB<Impl>::entryAmount(int num_threads)
1722292SN/A{
1732292SN/A    if (robPolicy == Partitioned) {
1742292SN/A        return numEntries / num_threads;
1752292SN/A    } else {
1762292SN/A        return 0;
1772292SN/A    }
1781060SN/A}
1791060SN/A
1801061SN/Atemplate <class Impl>
1811060SN/Aint
1821060SN/AROB<Impl>::countInsts()
1831060SN/A{
1842292SN/A    int total=0;
1851061SN/A
1862292SN/A    for (int i=0;i < numThreads;i++)
1872292SN/A        total += countInsts(i);
1881060SN/A
1892292SN/A    return total;
1902292SN/A}
1911060SN/A
1922292SN/Atemplate <class Impl>
1932292SN/Aint
1942292SN/AROB<Impl>::countInsts(unsigned tid)
1952292SN/A{
1962292SN/A    return instList[tid].size();
1971060SN/A}
1981060SN/A
1991061SN/Atemplate <class Impl>
2001060SN/Avoid
2011061SN/AROB<Impl>::insertInst(DynInstPtr &inst)
2021060SN/A{
2032292SN/A    //assert(numInstsInROB == countInsts());
2041060SN/A    assert(inst);
2051060SN/A
2062292SN/A    DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC());
2071060SN/A
2081060SN/A    assert(numInstsInROB != numEntries);
2091060SN/A
2102292SN/A    int tid = inst->threadNumber;
2111060SN/A
2122292SN/A    instList[tid].push_back(inst);
2132292SN/A
2142292SN/A    //Set Up head iterator if this is the 1st instruction in the ROB
2152292SN/A    if (numInstsInROB == 0) {
2162292SN/A        head = instList[tid].begin();
2172292SN/A        assert((*head) == inst);
2181060SN/A    }
2191060SN/A
2202292SN/A    //Must Decrement for iterator to actually be valid  since __.end()
2212292SN/A    //actually points to 1 after the last inst
2222292SN/A    tail = instList[tid].end();
2232292SN/A    tail--;
2242292SN/A
2252292SN/A    inst->setInROB();
2262292SN/A
2272292SN/A    ++numInstsInROB;
2282292SN/A    ++threadEntries[tid];
2292292SN/A
2301060SN/A    assert((*tail) == inst);
2311060SN/A
2322292SN/A    DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
2331060SN/A}
2341060SN/A
2351060SN/A// Whatever calls this function needs to ensure that it properly frees up
2361060SN/A// registers prior to this function.
2372329SN/A/*
2381061SN/Atemplate <class Impl>
2391060SN/Avoid
2401060SN/AROB<Impl>::retireHead()
2411060SN/A{
2422292SN/A    //assert(numInstsInROB == countInsts());
2432292SN/A    assert(numInstsInROB > 0);
2442292SN/A
2452292SN/A    int tid = (*head)->threadNumber;
2462292SN/A
2472292SN/A    retireHead(tid);
2482292SN/A
2492292SN/A    if (numInstsInROB == 0) {
2502292SN/A        tail = instList[tid].end();
2512292SN/A    }
2522292SN/A}
2532329SN/A*/
2542292SN/A
2552292SN/Atemplate <class Impl>
2562292SN/Avoid
2572292SN/AROB<Impl>::retireHead(unsigned tid)
2582292SN/A{
2592292SN/A    //assert(numInstsInROB == countInsts());
2601061SN/A    assert(numInstsInROB > 0);
2611060SN/A
2621060SN/A    // Get the head ROB instruction.
2632292SN/A    InstIt head_it = instList[tid].begin();
2641060SN/A
2652292SN/A    DynInstPtr head_inst = (*head_it);
2661858SN/A
2671060SN/A    assert(head_inst->readyToCommit());
2681060SN/A
2692292SN/A    DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
2702292SN/A            "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(),
2711060SN/A            head_inst->seqNum);
2721060SN/A
2731060SN/A    --numInstsInROB;
2742292SN/A    --threadEntries[tid];
2751060SN/A
2762731Sktlim@umich.edu    head_inst->clearInROB();
2772292SN/A    head_inst->setCommitted();
2782292SN/A
2792292SN/A    instList[tid].erase(head_it);
2802292SN/A
2812292SN/A    //Update "Global" Head of ROB
2822292SN/A    updateHead();
2832292SN/A
2842329SN/A    // @todo: A special case is needed if the instruction being
2852329SN/A    // retired is the only instruction in the ROB; otherwise the tail
2862329SN/A    // iterator will become invalidated.
2871681SN/A    cpu->removeFrontInst(head_inst);
2881060SN/A}
2892329SN/A/*
2901061SN/Atemplate <class Impl>
2911060SN/Abool
2921060SN/AROB<Impl>::isHeadReady()
2931060SN/A{
2941060SN/A    if (numInstsInROB != 0) {
2952292SN/A        return (*head)->readyToCommit();
2962292SN/A    }
2972292SN/A
2982292SN/A    return false;
2992292SN/A}
3002329SN/A*/
3012292SN/Atemplate <class Impl>
3022292SN/Abool
3032292SN/AROB<Impl>::isHeadReady(unsigned tid)
3042292SN/A{
3052292SN/A    if (threadEntries[tid] != 0) {
3062292SN/A        return instList[tid].front()->readyToCommit();
3072292SN/A    }
3082292SN/A
3092292SN/A    return false;
3102292SN/A}
3112292SN/A
3122292SN/Atemplate <class Impl>
3132292SN/Abool
3142292SN/AROB<Impl>::canCommit()
3152292SN/A{
3162292SN/A    //@todo: set ActiveThreads through ROB or CPU
3173867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
3183867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
3192292SN/A
3203867Sbinkertn@umich.edu    while (threads != end) {
3212292SN/A        unsigned tid = *threads++;
3222292SN/A
3232292SN/A        if (isHeadReady(tid)) {
3242292SN/A            return true;
3252292SN/A        }
3261060SN/A    }
3271060SN/A
3281060SN/A    return false;
3291060SN/A}
3301060SN/A
3311061SN/Atemplate <class Impl>
3321060SN/Aunsigned
3331060SN/AROB<Impl>::numFreeEntries()
3341060SN/A{
3352292SN/A    //assert(numInstsInROB == countInsts());
3361060SN/A
3371060SN/A    return numEntries - numInstsInROB;
3381060SN/A}
3391060SN/A
3401061SN/Atemplate <class Impl>
3412292SN/Aunsigned
3422292SN/AROB<Impl>::numFreeEntries(unsigned tid)
3431060SN/A{
3442292SN/A    return maxEntries[tid] - threadEntries[tid];
3451060SN/A}
3461060SN/A
3471061SN/Atemplate <class Impl>
3481060SN/Avoid
3492292SN/AROB<Impl>::doSquash(unsigned tid)
3501060SN/A{
3512292SN/A    DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
3522877Sksewell@umich.edu            tid, squashedSeqNum[tid]);
3531858SN/A
3542292SN/A    assert(squashIt[tid] != instList[tid].end());
3552292SN/A
3562877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) {
3572292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
3582292SN/A                tid);
3592292SN/A
3602292SN/A        squashIt[tid] = instList[tid].end();
3612292SN/A
3622292SN/A        doneSquashing[tid] = true;
3632292SN/A        return;
3642292SN/A    }
3652292SN/A
3662292SN/A    bool robTailUpdate = false;
3671858SN/A
3681858SN/A    for (int numSquashed = 0;
3692292SN/A         numSquashed < squashWidth &&
3702292SN/A         squashIt[tid] != instList[tid].end() &&
3712877Sksewell@umich.edu         (*squashIt[tid])->seqNum > squashedSeqNum[tid];
3721858SN/A         ++numSquashed)
3731858SN/A    {
3742292SN/A        DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n",
3752292SN/A                (*squashIt[tid])->threadNumber,
3762292SN/A                (*squashIt[tid])->readPC(),
3772292SN/A                (*squashIt[tid])->seqNum);
3781858SN/A
3791858SN/A        // Mark the instruction as squashed, and ready to commit so that
3801858SN/A        // it can drain out of the pipeline.
3812292SN/A        (*squashIt[tid])->setSquashed();
3821858SN/A
3832292SN/A        (*squashIt[tid])->setCanCommit();
3841858SN/A
3852292SN/A
3862292SN/A        if (squashIt[tid] == instList[tid].begin()) {
3872292SN/A            DPRINTF(ROB, "Reached head of instruction list while "
3881858SN/A                    "squashing.\n");
3891858SN/A
3902292SN/A            squashIt[tid] = instList[tid].end();
3911858SN/A
3922292SN/A            doneSquashing[tid] = true;
3931858SN/A
3941858SN/A            return;
3951858SN/A        }
3961858SN/A
3972292SN/A        InstIt tail_thread = instList[tid].end();
3982292SN/A        tail_thread--;
3992292SN/A
4002292SN/A        if ((*squashIt[tid]) == (*tail_thread))
4012292SN/A            robTailUpdate = true;
4022292SN/A
4032292SN/A        squashIt[tid]--;
4041858SN/A    }
4051858SN/A
4061858SN/A
4071858SN/A    // Check if ROB is done squashing.
4082877Sksewell@umich.edu    if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) {
4092292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
4102292SN/A                tid);
4111858SN/A
4122292SN/A        squashIt[tid] = instList[tid].end();
4131858SN/A
4142292SN/A        doneSquashing[tid] = true;
4152292SN/A    }
4162292SN/A
4172292SN/A    if (robTailUpdate) {
4182292SN/A        updateTail();
4192292SN/A    }
4202292SN/A}
4212292SN/A
4222292SN/A
4232292SN/Atemplate <class Impl>
4242292SN/Avoid
4252292SN/AROB<Impl>::updateHead()
4262292SN/A{
4272292SN/A    DynInstPtr head_inst;
4282292SN/A    InstSeqNum lowest_num = 0;
4292292SN/A    bool first_valid = true;
4302292SN/A
4312292SN/A    // @todo: set ActiveThreads through ROB or CPU
4323867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
4333867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
4342292SN/A
4353867Sbinkertn@umich.edu    while (threads != end) {
4363867Sbinkertn@umich.edu        unsigned tid = *threads++;
4372292SN/A
4383867Sbinkertn@umich.edu        if (instList[tid].empty())
4392292SN/A            continue;
4402292SN/A
4412292SN/A        if (first_valid) {
4423867Sbinkertn@umich.edu            head = instList[tid].begin();
4432292SN/A            lowest_num = (*head)->seqNum;
4442292SN/A            first_valid = false;
4452292SN/A            continue;
4462292SN/A        }
4472292SN/A
4483867Sbinkertn@umich.edu        InstIt head_thread = instList[tid].begin();
4492292SN/A
4502292SN/A        DynInstPtr head_inst = (*head_thread);
4512292SN/A
4522292SN/A        assert(head_inst != 0);
4532292SN/A
4542292SN/A        if (head_inst->seqNum < lowest_num) {
4552292SN/A            head = head_thread;
4562292SN/A            lowest_num = head_inst->seqNum;
4572292SN/A        }
4582292SN/A    }
4592292SN/A
4602292SN/A    if (first_valid) {
4612292SN/A        head = instList[0].end();
4622292SN/A    }
4632292SN/A
4642292SN/A}
4652292SN/A
4662292SN/Atemplate <class Impl>
4672292SN/Avoid
4682292SN/AROB<Impl>::updateTail()
4692292SN/A{
4702292SN/A    tail = instList[0].end();
4712292SN/A    bool first_valid = true;
4722292SN/A
4733867Sbinkertn@umich.edu    std::list<unsigned>::iterator threads = activeThreads->begin();
4743867Sbinkertn@umich.edu    std::list<unsigned>::iterator end = activeThreads->end();
4752292SN/A
4763867Sbinkertn@umich.edu    while (threads != end) {
4772292SN/A        unsigned tid = *threads++;
4782292SN/A
4792292SN/A        if (instList[tid].empty()) {
4802292SN/A            continue;
4812292SN/A        }
4822292SN/A
4832292SN/A        // If this is the first valid then assign w/out
4842292SN/A        // comparison
4852292SN/A        if (first_valid) {
4862292SN/A            tail = instList[tid].end();
4872292SN/A            tail--;
4882292SN/A            first_valid = false;
4892292SN/A            continue;
4902292SN/A        }
4912292SN/A
4922292SN/A        // Assign new tail if this thread's tail is younger
4932292SN/A        // than our current "tail high"
4942292SN/A        InstIt tail_thread = instList[tid].end();
4952292SN/A        tail_thread--;
4962292SN/A
4972292SN/A        if ((*tail_thread)->seqNum > (*tail)->seqNum) {
4982292SN/A            tail = tail_thread;
4992292SN/A        }
5002292SN/A    }
5012292SN/A}
5022292SN/A
5032292SN/A
5042292SN/Atemplate <class Impl>
5052292SN/Avoid
5062292SN/AROB<Impl>::squash(InstSeqNum squash_num,unsigned tid)
5072292SN/A{
5082292SN/A    if (isEmpty()) {
5092292SN/A        DPRINTF(ROB, "Does not need to squash due to being empty "
5102292SN/A                "[sn:%i]\n",
5112292SN/A                squash_num);
5122292SN/A
5132292SN/A        return;
5142292SN/A    }
5152292SN/A
5162292SN/A    DPRINTF(ROB, "Starting to squash within the ROB.\n");
5172292SN/A
5182292SN/A    robStatus[tid] = ROBSquashing;
5192292SN/A
5202292SN/A    doneSquashing[tid] = false;
5211060SN/A
5222877Sksewell@umich.edu    squashedSeqNum[tid] = squash_num;
5231060SN/A
5242292SN/A    if (!instList[tid].empty()) {
5252292SN/A        InstIt tail_thread = instList[tid].end();
5262292SN/A        tail_thread--;
5271060SN/A
5282292SN/A        squashIt[tid] = tail_thread;
5291060SN/A
5302292SN/A        doSquash(tid);
5311858SN/A    }
5321060SN/A}
5332329SN/A/*
5341858SN/Atemplate <class Impl>
5352292SN/Atypename Impl::DynInstPtr
5362292SN/AROB<Impl>::readHeadInst()
5371858SN/A{
5382292SN/A    if (numInstsInROB != 0) {
5392292SN/A        assert((*head)->isInROB()==true);
5402292SN/A        return *head;
5412292SN/A    } else {
5422292SN/A        return dummyInst;
5432292SN/A    }
5442292SN/A}
5452329SN/A*/
5462877Sksewell@umich.edu
5472292SN/Atemplate <class Impl>
5482292SN/Atypename Impl::DynInstPtr
5492292SN/AROB<Impl>::readHeadInst(unsigned tid)
5502292SN/A{
5512292SN/A    if (threadEntries[tid] != 0) {
5522292SN/A        InstIt head_thread = instList[tid].begin();
5531060SN/A
5542292SN/A        assert((*head_thread)->isInROB()==true);
5551858SN/A
5562292SN/A        return *head_thread;
5572292SN/A    } else {
5582292SN/A        return dummyInst;
5592292SN/A    }
5601858SN/A}
5612877Sksewell@umich.edu
5622329SN/A/*
5631061SN/Atemplate <class Impl>
5641060SN/Auint64_t
5651060SN/AROB<Impl>::readHeadPC()
5661060SN/A{
5672292SN/A    //assert(numInstsInROB == countInsts());
5681060SN/A
5692292SN/A    DynInstPtr head_inst = *head;
5701060SN/A
5711060SN/A    return head_inst->readPC();
5721060SN/A}
5731060SN/A
5741061SN/Atemplate <class Impl>
5751060SN/Auint64_t
5762292SN/AROB<Impl>::readHeadPC(unsigned tid)
5772292SN/A{
5782292SN/A    //assert(numInstsInROB == countInsts());
5792292SN/A    InstIt head_thread = instList[tid].begin();
5802292SN/A
5812292SN/A    return (*head_thread)->readPC();
5822292SN/A}
5832292SN/A
5842292SN/A
5852292SN/Atemplate <class Impl>
5862292SN/Auint64_t
5871060SN/AROB<Impl>::readHeadNextPC()
5881060SN/A{
5892292SN/A    //assert(numInstsInROB == countInsts());
5901060SN/A
5912292SN/A    DynInstPtr head_inst = *head;
5921060SN/A
5931060SN/A    return head_inst->readNextPC();
5941060SN/A}
5951060SN/A
5961061SN/Atemplate <class Impl>
5972292SN/Auint64_t
5982292SN/AROB<Impl>::readHeadNextPC(unsigned tid)
5992292SN/A{
6002292SN/A    //assert(numInstsInROB == countInsts());
6012292SN/A    InstIt head_thread = instList[tid].begin();
6022292SN/A
6032292SN/A    return (*head_thread)->readNextPC();
6042292SN/A}
6052292SN/A
6062292SN/Atemplate <class Impl>
6071060SN/AInstSeqNum
6081060SN/AROB<Impl>::readHeadSeqNum()
6091060SN/A{
6102292SN/A    //assert(numInstsInROB == countInsts());
6112292SN/A    DynInstPtr head_inst = *head;
6121060SN/A
6131060SN/A    return head_inst->seqNum;
6141060SN/A}
6151060SN/A
6161061SN/Atemplate <class Impl>
6172292SN/AInstSeqNum
6182292SN/AROB<Impl>::readHeadSeqNum(unsigned tid)
6192292SN/A{
6202292SN/A    InstIt head_thread = instList[tid].begin();
6212292SN/A
6222292SN/A    return ((*head_thread)->seqNum);
6232292SN/A}
6242292SN/A
6252292SN/Atemplate <class Impl>
6262292SN/Atypename Impl::DynInstPtr
6272292SN/AROB<Impl>::readTailInst()
6282292SN/A{
6292292SN/A    //assert(numInstsInROB == countInsts());
6302292SN/A    //assert(tail != instList[0].end());
6312292SN/A
6322292SN/A    return (*tail);
6332292SN/A}
6342329SN/A*/
6352292SN/Atemplate <class Impl>
6362292SN/Atypename Impl::DynInstPtr
6372292SN/AROB<Impl>::readTailInst(unsigned tid)
6382292SN/A{
6392292SN/A    //assert(tail_thread[tid] != instList[tid].end());
6402292SN/A
6412292SN/A    InstIt tail_thread = instList[tid].end();
6422292SN/A    tail_thread--;
6432292SN/A
6442292SN/A    return *tail_thread;
6452292SN/A}
6462292SN/A
6472329SN/A/*
6482292SN/Atemplate <class Impl>
6491060SN/Auint64_t
6501060SN/AROB<Impl>::readTailPC()
6511060SN/A{
6522292SN/A    //assert(numInstsInROB == countInsts());
6531060SN/A
6542292SN/A    //assert(tail != instList[0].end());
6551060SN/A
6561060SN/A    return (*tail)->readPC();
6571060SN/A}
6581060SN/A
6591061SN/Atemplate <class Impl>
6602292SN/Auint64_t
6612292SN/AROB<Impl>::readTailPC(unsigned tid)
6622292SN/A{
6632292SN/A    //assert(tail_thread[tid] != instList[tid].end());
6642292SN/A
6652292SN/A    InstIt tail_thread = instList[tid].end();
6662292SN/A    tail_thread--;
6672292SN/A
6682292SN/A    return (*tail_thread)->readPC();
6692292SN/A}
6702292SN/A
6712292SN/Atemplate <class Impl>
6721060SN/AInstSeqNum
6731060SN/AROB<Impl>::readTailSeqNum()
6741060SN/A{
6751060SN/A    // Return the last sequence number that has not been squashed.  Other
6761060SN/A    // stages can use it to squash any instructions younger than the current
6771060SN/A    // tail.
6781060SN/A    return (*tail)->seqNum;
6791060SN/A}
6801060SN/A
6812292SN/Atemplate <class Impl>
6822292SN/AInstSeqNum
6832292SN/AROB<Impl>::readTailSeqNum(unsigned tid)
6842292SN/A{
6852292SN/A    // Return the last sequence number that has not been squashed.  Other
6862292SN/A    // stages can use it to squash any instructions younger than the current
6872292SN/A    // tail.
6882292SN/A    //    assert(tail_thread[tid] != instList[tid].end());
6892292SN/A
6902292SN/A    InstIt tail_thread = instList[tid].end();
6912292SN/A    tail_thread--;
6922292SN/A
6932292SN/A    return (*tail_thread)->seqNum;
6942292SN/A}
6952329SN/A*/
696