rob_impl.hh revision 3867
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321858SN/A#include "config/full_system.hh" 331717SN/A#include "cpu/o3/rob.hh" 341060SN/A 352980Sgblack@eecs.umich.edu#include <list> 362292SN/A 371061SN/Atemplate <class Impl> 382292SN/AROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth, 392980Sgblack@eecs.umich.edu std::string _smtROBPolicy, unsigned _smtROBThreshold, 402292SN/A unsigned _numThreads) 411060SN/A : numEntries(_numEntries), 421060SN/A squashWidth(_squashWidth), 431060SN/A numInstsInROB(0), 442292SN/A numThreads(_numThreads) 451060SN/A{ 462292SN/A for (int tid=0; tid < numThreads; tid++) { 472877Sksewell@umich.edu squashedSeqNum[tid] = 0; 482292SN/A doneSquashing[tid] = true; 492292SN/A threadEntries[tid] = 0; 502292SN/A } 512292SN/A 522980Sgblack@eecs.umich.edu std::string policy = _smtROBPolicy; 532292SN/A 542292SN/A //Convert string to lowercase 552292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 562292SN/A (int(*)(int)) tolower); 572292SN/A 582292SN/A //Figure out rob policy 592292SN/A if (policy == "dynamic") { 602292SN/A robPolicy = Dynamic; 612292SN/A 622292SN/A //Set Max Entries to Total ROB Capacity 632292SN/A for (int i = 0; i < numThreads; i++) { 642292SN/A maxEntries[i]=numEntries; 652292SN/A } 662292SN/A 672292SN/A } else if (policy == "partitioned") { 682292SN/A robPolicy = Partitioned; 692292SN/A DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n"); 702292SN/A 712292SN/A //@todo:make work if part_amt doesnt divide evenly. 722292SN/A int part_amt = numEntries / numThreads; 732292SN/A 742292SN/A //Divide ROB up evenly 752292SN/A for (int i = 0; i < numThreads; i++) { 762292SN/A maxEntries[i]=part_amt; 772292SN/A } 782292SN/A 792292SN/A } else if (policy == "threshold") { 802292SN/A robPolicy = Threshold; 812292SN/A DPRINTF(Fetch, "ROB sharing policy set to Threshold\n"); 822292SN/A 832292SN/A int threshold = _smtROBThreshold;; 842292SN/A 852292SN/A //Divide up by threshold amount 862292SN/A for (int i = 0; i < numThreads; i++) { 872292SN/A maxEntries[i]=threshold; 882292SN/A } 892292SN/A } else { 902292SN/A assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic," 912292SN/A "Partitioned, Threshold}"); 922292SN/A } 932292SN/A} 942292SN/A 952292SN/Atemplate <class Impl> 962292SN/Astd::string 972292SN/AROB<Impl>::name() const 982292SN/A{ 992292SN/A return cpu->name() + ".rob"; 1001060SN/A} 1011060SN/A 1021061SN/Atemplate <class Impl> 1031060SN/Avoid 1042733Sktlim@umich.eduROB<Impl>::setCPU(O3CPU *cpu_ptr) 1051060SN/A{ 1061060SN/A cpu = cpu_ptr; 1071060SN/A 1082292SN/A // Set the per-thread iterators to the end of the instruction list. 1092292SN/A for (int i=0; i < numThreads;i++) { 1102292SN/A squashIt[i] = instList[i].end(); 1112292SN/A } 1121060SN/A 1132292SN/A // Initialize the "universal" ROB head & tail point to invalid 1142292SN/A // pointers 1152292SN/A head = instList[0].end(); 1162292SN/A tail = instList[0].end(); 1172292SN/A} 1182292SN/A 1192292SN/Atemplate <class Impl> 1202292SN/Avoid 1212980Sgblack@eecs.umich.eduROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 1222292SN/A{ 1232292SN/A DPRINTF(ROB, "Setting active threads list pointer.\n"); 1242292SN/A activeThreads = at_ptr; 1252292SN/A} 1262292SN/A 1272307SN/Atemplate <class Impl> 1282307SN/Avoid 1292307SN/AROB<Impl>::switchOut() 1302307SN/A{ 1312307SN/A for (int tid = 0; tid < numThreads; tid++) { 1322307SN/A instList[tid].clear(); 1332307SN/A } 1342307SN/A} 1352307SN/A 1362307SN/Atemplate <class Impl> 1372307SN/Avoid 1382307SN/AROB<Impl>::takeOverFrom() 1392307SN/A{ 1402307SN/A for (int tid=0; tid < numThreads; tid++) { 1412307SN/A doneSquashing[tid] = true; 1422307SN/A threadEntries[tid] = 0; 1432307SN/A squashIt[tid] = instList[tid].end(); 1442307SN/A } 1452307SN/A numInstsInROB = 0; 1462307SN/A 1472307SN/A // Initialize the "universal" ROB head & tail point to invalid 1482307SN/A // pointers 1492307SN/A head = instList[0].end(); 1502307SN/A tail = instList[0].end(); 1512307SN/A} 1522292SN/A 1532292SN/Atemplate <class Impl> 1542292SN/Avoid 1552292SN/AROB<Impl>::resetEntries() 1562292SN/A{ 1572292SN/A if (robPolicy != Dynamic || numThreads > 1) { 1583867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 1592292SN/A 1603867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 1613867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 1622292SN/A 1633867Sbinkertn@umich.edu while (threads != end) { 1643867Sbinkertn@umich.edu unsigned tid = *threads++; 1653867Sbinkertn@umich.edu 1662292SN/A if (robPolicy == Partitioned) { 1673867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 1682292SN/A } else if (robPolicy == Threshold && active_threads == 1) { 1693867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 1702292SN/A } 1712292SN/A } 1722292SN/A } 1732292SN/A} 1742292SN/A 1752292SN/Atemplate <class Impl> 1762292SN/Aint 1772292SN/AROB<Impl>::entryAmount(int num_threads) 1782292SN/A{ 1792292SN/A if (robPolicy == Partitioned) { 1802292SN/A return numEntries / num_threads; 1812292SN/A } else { 1822292SN/A return 0; 1832292SN/A } 1841060SN/A} 1851060SN/A 1861061SN/Atemplate <class Impl> 1871060SN/Aint 1881060SN/AROB<Impl>::countInsts() 1891060SN/A{ 1902292SN/A int total=0; 1911061SN/A 1922292SN/A for (int i=0;i < numThreads;i++) 1932292SN/A total += countInsts(i); 1941060SN/A 1952292SN/A return total; 1962292SN/A} 1971060SN/A 1982292SN/Atemplate <class Impl> 1992292SN/Aint 2002292SN/AROB<Impl>::countInsts(unsigned tid) 2012292SN/A{ 2022292SN/A return instList[tid].size(); 2031060SN/A} 2041060SN/A 2051061SN/Atemplate <class Impl> 2061060SN/Avoid 2071061SN/AROB<Impl>::insertInst(DynInstPtr &inst) 2081060SN/A{ 2092292SN/A //assert(numInstsInROB == countInsts()); 2101060SN/A assert(inst); 2111060SN/A 2122292SN/A DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC()); 2131060SN/A 2141060SN/A assert(numInstsInROB != numEntries); 2151060SN/A 2162292SN/A int tid = inst->threadNumber; 2171060SN/A 2182292SN/A instList[tid].push_back(inst); 2192292SN/A 2202292SN/A //Set Up head iterator if this is the 1st instruction in the ROB 2212292SN/A if (numInstsInROB == 0) { 2222292SN/A head = instList[tid].begin(); 2232292SN/A assert((*head) == inst); 2241060SN/A } 2251060SN/A 2262292SN/A //Must Decrement for iterator to actually be valid since __.end() 2272292SN/A //actually points to 1 after the last inst 2282292SN/A tail = instList[tid].end(); 2292292SN/A tail--; 2302292SN/A 2312292SN/A inst->setInROB(); 2322292SN/A 2332292SN/A ++numInstsInROB; 2342292SN/A ++threadEntries[tid]; 2352292SN/A 2361060SN/A assert((*tail) == inst); 2371060SN/A 2382292SN/A DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]); 2391060SN/A} 2401060SN/A 2411060SN/A// Whatever calls this function needs to ensure that it properly frees up 2421060SN/A// registers prior to this function. 2432329SN/A/* 2441061SN/Atemplate <class Impl> 2451060SN/Avoid 2461060SN/AROB<Impl>::retireHead() 2471060SN/A{ 2482292SN/A //assert(numInstsInROB == countInsts()); 2492292SN/A assert(numInstsInROB > 0); 2502292SN/A 2512292SN/A int tid = (*head)->threadNumber; 2522292SN/A 2532292SN/A retireHead(tid); 2542292SN/A 2552292SN/A if (numInstsInROB == 0) { 2562292SN/A tail = instList[tid].end(); 2572292SN/A } 2582292SN/A} 2592329SN/A*/ 2602292SN/A 2612292SN/Atemplate <class Impl> 2622292SN/Avoid 2632292SN/AROB<Impl>::retireHead(unsigned tid) 2642292SN/A{ 2652292SN/A //assert(numInstsInROB == countInsts()); 2661061SN/A assert(numInstsInROB > 0); 2671060SN/A 2681060SN/A // Get the head ROB instruction. 2692292SN/A InstIt head_it = instList[tid].begin(); 2701060SN/A 2712292SN/A DynInstPtr head_inst = (*head_it); 2721858SN/A 2731060SN/A assert(head_inst->readyToCommit()); 2741060SN/A 2752292SN/A DPRINTF(ROB, "[tid:%u]: Retiring head instruction, " 2762292SN/A "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(), 2771060SN/A head_inst->seqNum); 2781060SN/A 2791060SN/A --numInstsInROB; 2802292SN/A --threadEntries[tid]; 2811060SN/A 2822731Sktlim@umich.edu head_inst->clearInROB(); 2832292SN/A head_inst->setCommitted(); 2842292SN/A 2852292SN/A instList[tid].erase(head_it); 2862292SN/A 2872292SN/A //Update "Global" Head of ROB 2882292SN/A updateHead(); 2892292SN/A 2902329SN/A // @todo: A special case is needed if the instruction being 2912329SN/A // retired is the only instruction in the ROB; otherwise the tail 2922329SN/A // iterator will become invalidated. 2931681SN/A cpu->removeFrontInst(head_inst); 2941060SN/A} 2952329SN/A/* 2961061SN/Atemplate <class Impl> 2971060SN/Abool 2981060SN/AROB<Impl>::isHeadReady() 2991060SN/A{ 3001060SN/A if (numInstsInROB != 0) { 3012292SN/A return (*head)->readyToCommit(); 3022292SN/A } 3032292SN/A 3042292SN/A return false; 3052292SN/A} 3062329SN/A*/ 3072292SN/Atemplate <class Impl> 3082292SN/Abool 3092292SN/AROB<Impl>::isHeadReady(unsigned tid) 3102292SN/A{ 3112292SN/A if (threadEntries[tid] != 0) { 3122292SN/A return instList[tid].front()->readyToCommit(); 3132292SN/A } 3142292SN/A 3152292SN/A return false; 3162292SN/A} 3172292SN/A 3182292SN/Atemplate <class Impl> 3192292SN/Abool 3202292SN/AROB<Impl>::canCommit() 3212292SN/A{ 3222292SN/A //@todo: set ActiveThreads through ROB or CPU 3233867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 3243867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 3252292SN/A 3263867Sbinkertn@umich.edu while (threads != end) { 3272292SN/A unsigned tid = *threads++; 3282292SN/A 3292292SN/A if (isHeadReady(tid)) { 3302292SN/A return true; 3312292SN/A } 3321060SN/A } 3331060SN/A 3341060SN/A return false; 3351060SN/A} 3361060SN/A 3371061SN/Atemplate <class Impl> 3381060SN/Aunsigned 3391060SN/AROB<Impl>::numFreeEntries() 3401060SN/A{ 3412292SN/A //assert(numInstsInROB == countInsts()); 3421060SN/A 3431060SN/A return numEntries - numInstsInROB; 3441060SN/A} 3451060SN/A 3461061SN/Atemplate <class Impl> 3472292SN/Aunsigned 3482292SN/AROB<Impl>::numFreeEntries(unsigned tid) 3491060SN/A{ 3502292SN/A return maxEntries[tid] - threadEntries[tid]; 3511060SN/A} 3521060SN/A 3531061SN/Atemplate <class Impl> 3541060SN/Avoid 3552292SN/AROB<Impl>::doSquash(unsigned tid) 3561060SN/A{ 3572292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", 3582877Sksewell@umich.edu tid, squashedSeqNum[tid]); 3591858SN/A 3602292SN/A assert(squashIt[tid] != instList[tid].end()); 3612292SN/A 3622877Sksewell@umich.edu if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { 3632292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 3642292SN/A tid); 3652292SN/A 3662292SN/A squashIt[tid] = instList[tid].end(); 3672292SN/A 3682292SN/A doneSquashing[tid] = true; 3692292SN/A return; 3702292SN/A } 3712292SN/A 3722292SN/A bool robTailUpdate = false; 3731858SN/A 3741858SN/A for (int numSquashed = 0; 3752292SN/A numSquashed < squashWidth && 3762292SN/A squashIt[tid] != instList[tid].end() && 3772877Sksewell@umich.edu (*squashIt[tid])->seqNum > squashedSeqNum[tid]; 3781858SN/A ++numSquashed) 3791858SN/A { 3802292SN/A DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n", 3812292SN/A (*squashIt[tid])->threadNumber, 3822292SN/A (*squashIt[tid])->readPC(), 3832292SN/A (*squashIt[tid])->seqNum); 3841858SN/A 3851858SN/A // Mark the instruction as squashed, and ready to commit so that 3861858SN/A // it can drain out of the pipeline. 3872292SN/A (*squashIt[tid])->setSquashed(); 3881858SN/A 3892292SN/A (*squashIt[tid])->setCanCommit(); 3901858SN/A 3912292SN/A 3922292SN/A if (squashIt[tid] == instList[tid].begin()) { 3932292SN/A DPRINTF(ROB, "Reached head of instruction list while " 3941858SN/A "squashing.\n"); 3951858SN/A 3962292SN/A squashIt[tid] = instList[tid].end(); 3971858SN/A 3982292SN/A doneSquashing[tid] = true; 3991858SN/A 4001858SN/A return; 4011858SN/A } 4021858SN/A 4032292SN/A InstIt tail_thread = instList[tid].end(); 4042292SN/A tail_thread--; 4052292SN/A 4062292SN/A if ((*squashIt[tid]) == (*tail_thread)) 4072292SN/A robTailUpdate = true; 4082292SN/A 4092292SN/A squashIt[tid]--; 4101858SN/A } 4111858SN/A 4121858SN/A 4131858SN/A // Check if ROB is done squashing. 4142877Sksewell@umich.edu if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { 4152292SN/A DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", 4162292SN/A tid); 4171858SN/A 4182292SN/A squashIt[tid] = instList[tid].end(); 4191858SN/A 4202292SN/A doneSquashing[tid] = true; 4212292SN/A } 4222292SN/A 4232292SN/A if (robTailUpdate) { 4242292SN/A updateTail(); 4252292SN/A } 4262292SN/A} 4272292SN/A 4282292SN/A 4292292SN/Atemplate <class Impl> 4302292SN/Avoid 4312292SN/AROB<Impl>::updateHead() 4322292SN/A{ 4332292SN/A DynInstPtr head_inst; 4342292SN/A InstSeqNum lowest_num = 0; 4352292SN/A bool first_valid = true; 4362292SN/A 4372292SN/A // @todo: set ActiveThreads through ROB or CPU 4383867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4393867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4402292SN/A 4413867Sbinkertn@umich.edu while (threads != end) { 4423867Sbinkertn@umich.edu unsigned tid = *threads++; 4432292SN/A 4443867Sbinkertn@umich.edu if (instList[tid].empty()) 4452292SN/A continue; 4462292SN/A 4472292SN/A if (first_valid) { 4483867Sbinkertn@umich.edu head = instList[tid].begin(); 4492292SN/A lowest_num = (*head)->seqNum; 4502292SN/A first_valid = false; 4512292SN/A continue; 4522292SN/A } 4532292SN/A 4543867Sbinkertn@umich.edu InstIt head_thread = instList[tid].begin(); 4552292SN/A 4562292SN/A DynInstPtr head_inst = (*head_thread); 4572292SN/A 4582292SN/A assert(head_inst != 0); 4592292SN/A 4602292SN/A if (head_inst->seqNum < lowest_num) { 4612292SN/A head = head_thread; 4622292SN/A lowest_num = head_inst->seqNum; 4632292SN/A } 4642292SN/A } 4652292SN/A 4662292SN/A if (first_valid) { 4672292SN/A head = instList[0].end(); 4682292SN/A } 4692292SN/A 4702292SN/A} 4712292SN/A 4722292SN/Atemplate <class Impl> 4732292SN/Avoid 4742292SN/AROB<Impl>::updateTail() 4752292SN/A{ 4762292SN/A tail = instList[0].end(); 4772292SN/A bool first_valid = true; 4782292SN/A 4793867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4803867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4812292SN/A 4823867Sbinkertn@umich.edu while (threads != end) { 4832292SN/A unsigned tid = *threads++; 4842292SN/A 4852292SN/A if (instList[tid].empty()) { 4862292SN/A continue; 4872292SN/A } 4882292SN/A 4892292SN/A // If this is the first valid then assign w/out 4902292SN/A // comparison 4912292SN/A if (first_valid) { 4922292SN/A tail = instList[tid].end(); 4932292SN/A tail--; 4942292SN/A first_valid = false; 4952292SN/A continue; 4962292SN/A } 4972292SN/A 4982292SN/A // Assign new tail if this thread's tail is younger 4992292SN/A // than our current "tail high" 5002292SN/A InstIt tail_thread = instList[tid].end(); 5012292SN/A tail_thread--; 5022292SN/A 5032292SN/A if ((*tail_thread)->seqNum > (*tail)->seqNum) { 5042292SN/A tail = tail_thread; 5052292SN/A } 5062292SN/A } 5072292SN/A} 5082292SN/A 5092292SN/A 5102292SN/Atemplate <class Impl> 5112292SN/Avoid 5122292SN/AROB<Impl>::squash(InstSeqNum squash_num,unsigned tid) 5132292SN/A{ 5142292SN/A if (isEmpty()) { 5152292SN/A DPRINTF(ROB, "Does not need to squash due to being empty " 5162292SN/A "[sn:%i]\n", 5172292SN/A squash_num); 5182292SN/A 5192292SN/A return; 5202292SN/A } 5212292SN/A 5222292SN/A DPRINTF(ROB, "Starting to squash within the ROB.\n"); 5232292SN/A 5242292SN/A robStatus[tid] = ROBSquashing; 5252292SN/A 5262292SN/A doneSquashing[tid] = false; 5271060SN/A 5282877Sksewell@umich.edu squashedSeqNum[tid] = squash_num; 5291060SN/A 5302292SN/A if (!instList[tid].empty()) { 5312292SN/A InstIt tail_thread = instList[tid].end(); 5322292SN/A tail_thread--; 5331060SN/A 5342292SN/A squashIt[tid] = tail_thread; 5351060SN/A 5362292SN/A doSquash(tid); 5371858SN/A } 5381060SN/A} 5392329SN/A/* 5401858SN/Atemplate <class Impl> 5412292SN/Atypename Impl::DynInstPtr 5422292SN/AROB<Impl>::readHeadInst() 5431858SN/A{ 5442292SN/A if (numInstsInROB != 0) { 5452292SN/A assert((*head)->isInROB()==true); 5462292SN/A return *head; 5472292SN/A } else { 5482292SN/A return dummyInst; 5492292SN/A } 5502292SN/A} 5512329SN/A*/ 5522877Sksewell@umich.edu 5532292SN/Atemplate <class Impl> 5542292SN/Atypename Impl::DynInstPtr 5552292SN/AROB<Impl>::readHeadInst(unsigned tid) 5562292SN/A{ 5572292SN/A if (threadEntries[tid] != 0) { 5582292SN/A InstIt head_thread = instList[tid].begin(); 5591060SN/A 5602292SN/A assert((*head_thread)->isInROB()==true); 5611858SN/A 5622292SN/A return *head_thread; 5632292SN/A } else { 5642292SN/A return dummyInst; 5652292SN/A } 5661858SN/A} 5672877Sksewell@umich.edu 5682329SN/A/* 5691061SN/Atemplate <class Impl> 5701060SN/Auint64_t 5711060SN/AROB<Impl>::readHeadPC() 5721060SN/A{ 5732292SN/A //assert(numInstsInROB == countInsts()); 5741060SN/A 5752292SN/A DynInstPtr head_inst = *head; 5761060SN/A 5771060SN/A return head_inst->readPC(); 5781060SN/A} 5791060SN/A 5801061SN/Atemplate <class Impl> 5811060SN/Auint64_t 5822292SN/AROB<Impl>::readHeadPC(unsigned tid) 5832292SN/A{ 5842292SN/A //assert(numInstsInROB == countInsts()); 5852292SN/A InstIt head_thread = instList[tid].begin(); 5862292SN/A 5872292SN/A return (*head_thread)->readPC(); 5882292SN/A} 5892292SN/A 5902292SN/A 5912292SN/Atemplate <class Impl> 5922292SN/Auint64_t 5931060SN/AROB<Impl>::readHeadNextPC() 5941060SN/A{ 5952292SN/A //assert(numInstsInROB == countInsts()); 5961060SN/A 5972292SN/A DynInstPtr head_inst = *head; 5981060SN/A 5991060SN/A return head_inst->readNextPC(); 6001060SN/A} 6011060SN/A 6021061SN/Atemplate <class Impl> 6032292SN/Auint64_t 6042292SN/AROB<Impl>::readHeadNextPC(unsigned tid) 6052292SN/A{ 6062292SN/A //assert(numInstsInROB == countInsts()); 6072292SN/A InstIt head_thread = instList[tid].begin(); 6082292SN/A 6092292SN/A return (*head_thread)->readNextPC(); 6102292SN/A} 6112292SN/A 6122292SN/Atemplate <class Impl> 6131060SN/AInstSeqNum 6141060SN/AROB<Impl>::readHeadSeqNum() 6151060SN/A{ 6162292SN/A //assert(numInstsInROB == countInsts()); 6172292SN/A DynInstPtr head_inst = *head; 6181060SN/A 6191060SN/A return head_inst->seqNum; 6201060SN/A} 6211060SN/A 6221061SN/Atemplate <class Impl> 6232292SN/AInstSeqNum 6242292SN/AROB<Impl>::readHeadSeqNum(unsigned tid) 6252292SN/A{ 6262292SN/A InstIt head_thread = instList[tid].begin(); 6272292SN/A 6282292SN/A return ((*head_thread)->seqNum); 6292292SN/A} 6302292SN/A 6312292SN/Atemplate <class Impl> 6322292SN/Atypename Impl::DynInstPtr 6332292SN/AROB<Impl>::readTailInst() 6342292SN/A{ 6352292SN/A //assert(numInstsInROB == countInsts()); 6362292SN/A //assert(tail != instList[0].end()); 6372292SN/A 6382292SN/A return (*tail); 6392292SN/A} 6402329SN/A*/ 6412292SN/Atemplate <class Impl> 6422292SN/Atypename Impl::DynInstPtr 6432292SN/AROB<Impl>::readTailInst(unsigned tid) 6442292SN/A{ 6452292SN/A //assert(tail_thread[tid] != instList[tid].end()); 6462292SN/A 6472292SN/A InstIt tail_thread = instList[tid].end(); 6482292SN/A tail_thread--; 6492292SN/A 6502292SN/A return *tail_thread; 6512292SN/A} 6522292SN/A 6532329SN/A/* 6542292SN/Atemplate <class Impl> 6551060SN/Auint64_t 6561060SN/AROB<Impl>::readTailPC() 6571060SN/A{ 6582292SN/A //assert(numInstsInROB == countInsts()); 6591060SN/A 6602292SN/A //assert(tail != instList[0].end()); 6611060SN/A 6621060SN/A return (*tail)->readPC(); 6631060SN/A} 6641060SN/A 6651061SN/Atemplate <class Impl> 6662292SN/Auint64_t 6672292SN/AROB<Impl>::readTailPC(unsigned tid) 6682292SN/A{ 6692292SN/A //assert(tail_thread[tid] != instList[tid].end()); 6702292SN/A 6712292SN/A InstIt tail_thread = instList[tid].end(); 6722292SN/A tail_thread--; 6732292SN/A 6742292SN/A return (*tail_thread)->readPC(); 6752292SN/A} 6762292SN/A 6772292SN/Atemplate <class Impl> 6781060SN/AInstSeqNum 6791060SN/AROB<Impl>::readTailSeqNum() 6801060SN/A{ 6811060SN/A // Return the last sequence number that has not been squashed. Other 6821060SN/A // stages can use it to squash any instructions younger than the current 6831060SN/A // tail. 6841060SN/A return (*tail)->seqNum; 6851060SN/A} 6861060SN/A 6872292SN/Atemplate <class Impl> 6882292SN/AInstSeqNum 6892292SN/AROB<Impl>::readTailSeqNum(unsigned tid) 6902292SN/A{ 6912292SN/A // Return the last sequence number that has not been squashed. Other 6922292SN/A // stages can use it to squash any instructions younger than the current 6932292SN/A // tail. 6942292SN/A // assert(tail_thread[tid] != instList[tid].end()); 6952292SN/A 6962292SN/A InstIt tail_thread = instList[tid].end(); 6972292SN/A tail_thread--; 6982292SN/A 6992292SN/A return (*tail_thread)->seqNum; 7002292SN/A} 7012329SN/A*/ 702