rob_impl.hh revision 2733
11689SN/A/*
22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
311858SN/A#include "config/full_system.hh"
321717SN/A#include "cpu/o3/rob.hh"
331060SN/A
342292SN/Ausing namespace std;
352292SN/A
361061SN/Atemplate <class Impl>
372292SN/AROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
382292SN/A               string _smtROBPolicy, unsigned _smtROBThreshold,
392292SN/A               unsigned _numThreads)
401060SN/A    : numEntries(_numEntries),
411060SN/A      squashWidth(_squashWidth),
421060SN/A      numInstsInROB(0),
432292SN/A      squashedSeqNum(0),
442292SN/A      numThreads(_numThreads)
451060SN/A{
462292SN/A    for (int tid=0; tid  < numThreads; tid++) {
472292SN/A        doneSquashing[tid] = true;
482292SN/A        threadEntries[tid] = 0;
492292SN/A    }
502292SN/A
512292SN/A    string policy = _smtROBPolicy;
522292SN/A
532292SN/A    //Convert string to lowercase
542292SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
552292SN/A                   (int(*)(int)) tolower);
562292SN/A
572292SN/A    //Figure out rob policy
582292SN/A    if (policy == "dynamic") {
592292SN/A        robPolicy = Dynamic;
602292SN/A
612292SN/A        //Set Max Entries to Total ROB Capacity
622292SN/A        for (int i = 0; i < numThreads; i++) {
632292SN/A            maxEntries[i]=numEntries;
642292SN/A        }
652292SN/A
662292SN/A    } else if (policy == "partitioned") {
672292SN/A        robPolicy = Partitioned;
682292SN/A        DPRINTF(Fetch, "ROB sharing policy set to Partitioned\n");
692292SN/A
702292SN/A        //@todo:make work if part_amt doesnt divide evenly.
712292SN/A        int part_amt = numEntries / numThreads;
722292SN/A
732292SN/A        //Divide ROB up evenly
742292SN/A        for (int i = 0; i < numThreads; i++) {
752292SN/A            maxEntries[i]=part_amt;
762292SN/A        }
772292SN/A
782292SN/A    } else if (policy == "threshold") {
792292SN/A        robPolicy = Threshold;
802292SN/A        DPRINTF(Fetch, "ROB sharing policy set to Threshold\n");
812292SN/A
822292SN/A        int threshold =  _smtROBThreshold;;
832292SN/A
842292SN/A        //Divide up by threshold amount
852292SN/A        for (int i = 0; i < numThreads; i++) {
862292SN/A            maxEntries[i]=threshold;
872292SN/A        }
882292SN/A    } else {
892292SN/A        assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
902292SN/A                    "Partitioned, Threshold}");
912292SN/A    }
922292SN/A}
932292SN/A
942292SN/Atemplate <class Impl>
952292SN/Astd::string
962292SN/AROB<Impl>::name() const
972292SN/A{
982292SN/A    return cpu->name() + ".rob";
991060SN/A}
1001060SN/A
1011061SN/Atemplate <class Impl>
1021060SN/Avoid
1032733Sktlim@umich.eduROB<Impl>::setCPU(O3CPU *cpu_ptr)
1041060SN/A{
1051060SN/A    cpu = cpu_ptr;
1061060SN/A
1072292SN/A    // Set the per-thread iterators to the end of the instruction list.
1082292SN/A    for (int i=0; i < numThreads;i++) {
1092292SN/A        squashIt[i] = instList[i].end();
1102292SN/A    }
1111060SN/A
1122292SN/A    // Initialize the "universal" ROB head & tail point to invalid
1132292SN/A    // pointers
1142292SN/A    head = instList[0].end();
1152292SN/A    tail = instList[0].end();
1162292SN/A}
1172292SN/A
1182292SN/Atemplate <class Impl>
1192292SN/Avoid
1202292SN/AROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
1212292SN/A{
1222292SN/A    DPRINTF(ROB, "Setting active threads list pointer.\n");
1232292SN/A    activeThreads = at_ptr;
1242292SN/A}
1252292SN/A
1262307SN/Atemplate <class Impl>
1272307SN/Avoid
1282307SN/AROB<Impl>::switchOut()
1292307SN/A{
1302307SN/A    for (int tid = 0; tid < numThreads; tid++) {
1312307SN/A        instList[tid].clear();
1322307SN/A    }
1332307SN/A}
1342307SN/A
1352307SN/Atemplate <class Impl>
1362307SN/Avoid
1372307SN/AROB<Impl>::takeOverFrom()
1382307SN/A{
1392307SN/A    for (int tid=0; tid  < numThreads; tid++) {
1402307SN/A        doneSquashing[tid] = true;
1412307SN/A        threadEntries[tid] = 0;
1422307SN/A        squashIt[tid] = instList[tid].end();
1432307SN/A    }
1442307SN/A    numInstsInROB = 0;
1452307SN/A
1462307SN/A    // Initialize the "universal" ROB head & tail point to invalid
1472307SN/A    // pointers
1482307SN/A    head = instList[0].end();
1492307SN/A    tail = instList[0].end();
1502307SN/A}
1512292SN/A
1522292SN/Atemplate <class Impl>
1532292SN/Avoid
1542292SN/AROB<Impl>::resetEntries()
1552292SN/A{
1562292SN/A    if (robPolicy != Dynamic || numThreads > 1) {
1572292SN/A        int active_threads = (*activeThreads).size();
1582292SN/A
1592292SN/A        list<unsigned>::iterator threads  = (*activeThreads).begin();
1602292SN/A        list<unsigned>::iterator list_end = (*activeThreads).end();
1612292SN/A
1622292SN/A        while (threads != list_end) {
1632292SN/A            if (robPolicy == Partitioned) {
1642292SN/A                maxEntries[*threads++] = numEntries / active_threads;
1652292SN/A            } else if (robPolicy == Threshold && active_threads == 1) {
1662292SN/A                maxEntries[*threads++] = numEntries;
1672292SN/A            }
1682292SN/A        }
1692292SN/A    }
1702292SN/A}
1712292SN/A
1722292SN/Atemplate <class Impl>
1732292SN/Aint
1742292SN/AROB<Impl>::entryAmount(int num_threads)
1752292SN/A{
1762292SN/A    if (robPolicy == Partitioned) {
1772292SN/A        return numEntries / num_threads;
1782292SN/A    } else {
1792292SN/A        return 0;
1802292SN/A    }
1811060SN/A}
1821060SN/A
1831061SN/Atemplate <class Impl>
1841060SN/Aint
1851060SN/AROB<Impl>::countInsts()
1861060SN/A{
1872292SN/A    int total=0;
1881061SN/A
1892292SN/A    for (int i=0;i < numThreads;i++)
1902292SN/A        total += countInsts(i);
1911060SN/A
1922292SN/A    return total;
1932292SN/A}
1941060SN/A
1952292SN/Atemplate <class Impl>
1962292SN/Aint
1972292SN/AROB<Impl>::countInsts(unsigned tid)
1982292SN/A{
1992292SN/A    return instList[tid].size();
2001060SN/A}
2011060SN/A
2021061SN/Atemplate <class Impl>
2031060SN/Avoid
2041061SN/AROB<Impl>::insertInst(DynInstPtr &inst)
2051060SN/A{
2062292SN/A    //assert(numInstsInROB == countInsts());
2071060SN/A    assert(inst);
2081060SN/A
2092292SN/A    DPRINTF(ROB, "Adding inst PC %#x to the ROB.\n", inst->readPC());
2101060SN/A
2111060SN/A    assert(numInstsInROB != numEntries);
2121060SN/A
2132292SN/A    int tid = inst->threadNumber;
2141060SN/A
2152292SN/A    instList[tid].push_back(inst);
2162292SN/A
2172292SN/A    //Set Up head iterator if this is the 1st instruction in the ROB
2182292SN/A    if (numInstsInROB == 0) {
2192292SN/A        head = instList[tid].begin();
2202292SN/A        assert((*head) == inst);
2211060SN/A    }
2221060SN/A
2232292SN/A    //Must Decrement for iterator to actually be valid  since __.end()
2242292SN/A    //actually points to 1 after the last inst
2252292SN/A    tail = instList[tid].end();
2262292SN/A    tail--;
2272292SN/A
2282292SN/A    inst->setInROB();
2292292SN/A
2302292SN/A    ++numInstsInROB;
2312292SN/A    ++threadEntries[tid];
2322292SN/A
2331060SN/A    assert((*tail) == inst);
2341060SN/A
2352292SN/A    DPRINTF(ROB, "[tid:%i] Now has %d instructions.\n", tid, threadEntries[tid]);
2361060SN/A}
2371060SN/A
2381060SN/A// Whatever calls this function needs to ensure that it properly frees up
2391060SN/A// registers prior to this function.
2402329SN/A/*
2411061SN/Atemplate <class Impl>
2421060SN/Avoid
2431060SN/AROB<Impl>::retireHead()
2441060SN/A{
2452292SN/A    //assert(numInstsInROB == countInsts());
2462292SN/A    assert(numInstsInROB > 0);
2472292SN/A
2482292SN/A    int tid = (*head)->threadNumber;
2492292SN/A
2502292SN/A    retireHead(tid);
2512292SN/A
2522292SN/A    if (numInstsInROB == 0) {
2532292SN/A        tail = instList[tid].end();
2542292SN/A    }
2552292SN/A}
2562329SN/A*/
2572292SN/A
2582292SN/Atemplate <class Impl>
2592292SN/Avoid
2602292SN/AROB<Impl>::retireHead(unsigned tid)
2612292SN/A{
2622292SN/A    //assert(numInstsInROB == countInsts());
2631061SN/A    assert(numInstsInROB > 0);
2641060SN/A
2651060SN/A    // Get the head ROB instruction.
2662292SN/A    InstIt head_it = instList[tid].begin();
2671060SN/A
2682292SN/A    DynInstPtr head_inst = (*head_it);
2691858SN/A
2701060SN/A    assert(head_inst->readyToCommit());
2711060SN/A
2722292SN/A    DPRINTF(ROB, "[tid:%u]: Retiring head instruction, "
2732292SN/A            "instruction PC %#x,[sn:%lli]\n", tid, head_inst->readPC(),
2741060SN/A            head_inst->seqNum);
2751060SN/A
2761060SN/A    --numInstsInROB;
2772292SN/A    --threadEntries[tid];
2781060SN/A
2792731Sktlim@umich.edu    head_inst->clearInROB();
2802292SN/A    head_inst->setCommitted();
2812292SN/A
2822292SN/A    instList[tid].erase(head_it);
2832292SN/A
2842292SN/A    //Update "Global" Head of ROB
2852292SN/A    updateHead();
2862292SN/A
2872329SN/A    // @todo: A special case is needed if the instruction being
2882329SN/A    // retired is the only instruction in the ROB; otherwise the tail
2892329SN/A    // iterator will become invalidated.
2901681SN/A    cpu->removeFrontInst(head_inst);
2911060SN/A}
2922329SN/A/*
2931061SN/Atemplate <class Impl>
2941060SN/Abool
2951060SN/AROB<Impl>::isHeadReady()
2961060SN/A{
2971060SN/A    if (numInstsInROB != 0) {
2982292SN/A        return (*head)->readyToCommit();
2992292SN/A    }
3002292SN/A
3012292SN/A    return false;
3022292SN/A}
3032329SN/A*/
3042292SN/Atemplate <class Impl>
3052292SN/Abool
3062292SN/AROB<Impl>::isHeadReady(unsigned tid)
3072292SN/A{
3082292SN/A    if (threadEntries[tid] != 0) {
3092292SN/A        return instList[tid].front()->readyToCommit();
3102292SN/A    }
3112292SN/A
3122292SN/A    return false;
3132292SN/A}
3142292SN/A
3152292SN/Atemplate <class Impl>
3162292SN/Abool
3172292SN/AROB<Impl>::canCommit()
3182292SN/A{
3192292SN/A    //@todo: set ActiveThreads through ROB or CPU
3202292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
3212292SN/A
3222292SN/A    while (threads != (*activeThreads).end()) {
3232292SN/A        unsigned tid = *threads++;
3242292SN/A
3252292SN/A        if (isHeadReady(tid)) {
3262292SN/A            return true;
3272292SN/A        }
3281060SN/A    }
3291060SN/A
3301060SN/A    return false;
3311060SN/A}
3321060SN/A
3331061SN/Atemplate <class Impl>
3341060SN/Aunsigned
3351060SN/AROB<Impl>::numFreeEntries()
3361060SN/A{
3372292SN/A    //assert(numInstsInROB == countInsts());
3381060SN/A
3391060SN/A    return numEntries - numInstsInROB;
3401060SN/A}
3411060SN/A
3421061SN/Atemplate <class Impl>
3432292SN/Aunsigned
3442292SN/AROB<Impl>::numFreeEntries(unsigned tid)
3451060SN/A{
3462292SN/A    return maxEntries[tid] - threadEntries[tid];
3471060SN/A}
3481060SN/A
3491061SN/Atemplate <class Impl>
3501060SN/Avoid
3512292SN/AROB<Impl>::doSquash(unsigned tid)
3521060SN/A{
3532292SN/A    DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
3542292SN/A            tid, squashedSeqNum);
3551858SN/A
3562292SN/A    assert(squashIt[tid] != instList[tid].end());
3572292SN/A
3582292SN/A    if ((*squashIt[tid])->seqNum < squashedSeqNum) {
3592292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
3602292SN/A                tid);
3612292SN/A
3622292SN/A        squashIt[tid] = instList[tid].end();
3632292SN/A
3642292SN/A        doneSquashing[tid] = true;
3652292SN/A        return;
3662292SN/A    }
3672292SN/A
3682292SN/A    bool robTailUpdate = false;
3691858SN/A
3701858SN/A    for (int numSquashed = 0;
3712292SN/A         numSquashed < squashWidth &&
3722292SN/A         squashIt[tid] != instList[tid].end() &&
3732292SN/A         (*squashIt[tid])->seqNum > squashedSeqNum;
3741858SN/A         ++numSquashed)
3751858SN/A    {
3762292SN/A        DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n",
3772292SN/A                (*squashIt[tid])->threadNumber,
3782292SN/A                (*squashIt[tid])->readPC(),
3792292SN/A                (*squashIt[tid])->seqNum);
3801858SN/A
3811858SN/A        // Mark the instruction as squashed, and ready to commit so that
3821858SN/A        // it can drain out of the pipeline.
3832292SN/A        (*squashIt[tid])->setSquashed();
3841858SN/A
3852292SN/A        (*squashIt[tid])->setCanCommit();
3861858SN/A
3872292SN/A
3882292SN/A        if (squashIt[tid] == instList[tid].begin()) {
3892292SN/A            DPRINTF(ROB, "Reached head of instruction list while "
3901858SN/A                    "squashing.\n");
3911858SN/A
3922292SN/A            squashIt[tid] = instList[tid].end();
3931858SN/A
3942292SN/A            doneSquashing[tid] = true;
3951858SN/A
3961858SN/A            return;
3971858SN/A        }
3981858SN/A
3992292SN/A        InstIt tail_thread = instList[tid].end();
4002292SN/A        tail_thread--;
4012292SN/A
4022292SN/A        if ((*squashIt[tid]) == (*tail_thread))
4032292SN/A            robTailUpdate = true;
4042292SN/A
4052292SN/A        squashIt[tid]--;
4061858SN/A    }
4071858SN/A
4081858SN/A
4091858SN/A    // Check if ROB is done squashing.
4102292SN/A    if ((*squashIt[tid])->seqNum <= squashedSeqNum) {
4112292SN/A        DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n",
4122292SN/A                tid);
4131858SN/A
4142292SN/A        squashIt[tid] = instList[tid].end();
4151858SN/A
4162292SN/A        doneSquashing[tid] = true;
4172292SN/A    }
4182292SN/A
4192292SN/A    if (robTailUpdate) {
4202292SN/A        updateTail();
4212292SN/A    }
4222292SN/A}
4232292SN/A
4242292SN/A
4252292SN/Atemplate <class Impl>
4262292SN/Avoid
4272292SN/AROB<Impl>::updateHead()
4282292SN/A{
4292292SN/A    DynInstPtr head_inst;
4302292SN/A    InstSeqNum lowest_num = 0;
4312292SN/A    bool first_valid = true;
4322292SN/A
4332292SN/A    // @todo: set ActiveThreads through ROB or CPU
4342292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
4352292SN/A
4362292SN/A    while (threads != (*activeThreads).end()) {
4372292SN/A        unsigned thread_num = *threads++;
4382292SN/A
4392292SN/A        if (instList[thread_num].empty())
4402292SN/A            continue;
4412292SN/A
4422292SN/A        if (first_valid) {
4432292SN/A            head = instList[thread_num].begin();
4442292SN/A            lowest_num = (*head)->seqNum;
4452292SN/A            first_valid = false;
4462292SN/A            continue;
4472292SN/A        }
4482292SN/A
4492292SN/A        InstIt head_thread = instList[thread_num].begin();
4502292SN/A
4512292SN/A        DynInstPtr head_inst = (*head_thread);
4522292SN/A
4532292SN/A        assert(head_inst != 0);
4542292SN/A
4552292SN/A        if (head_inst->seqNum < lowest_num) {
4562292SN/A            head = head_thread;
4572292SN/A            lowest_num = head_inst->seqNum;
4582292SN/A        }
4592292SN/A    }
4602292SN/A
4612292SN/A    if (first_valid) {
4622292SN/A        head = instList[0].end();
4632292SN/A    }
4642292SN/A
4652292SN/A}
4662292SN/A
4672292SN/Atemplate <class Impl>
4682292SN/Avoid
4692292SN/AROB<Impl>::updateTail()
4702292SN/A{
4712292SN/A    tail = instList[0].end();
4722292SN/A    bool first_valid = true;
4732292SN/A
4742292SN/A    list<unsigned>::iterator threads = (*activeThreads).begin();
4752292SN/A
4762292SN/A    while (threads != (*activeThreads).end()) {
4772292SN/A        unsigned tid = *threads++;
4782292SN/A
4792292SN/A        if (instList[tid].empty()) {
4802292SN/A            continue;
4812292SN/A        }
4822292SN/A
4832292SN/A        // If this is the first valid then assign w/out
4842292SN/A        // comparison
4852292SN/A        if (first_valid) {
4862292SN/A            tail = instList[tid].end();
4872292SN/A            tail--;
4882292SN/A            first_valid = false;
4892292SN/A            continue;
4902292SN/A        }
4912292SN/A
4922292SN/A        // Assign new tail if this thread's tail is younger
4932292SN/A        // than our current "tail high"
4942292SN/A        InstIt tail_thread = instList[tid].end();
4952292SN/A        tail_thread--;
4962292SN/A
4972292SN/A        if ((*tail_thread)->seqNum > (*tail)->seqNum) {
4982292SN/A            tail = tail_thread;
4992292SN/A        }
5002292SN/A    }
5012292SN/A}
5022292SN/A
5032292SN/A
5042292SN/Atemplate <class Impl>
5052292SN/Avoid
5062292SN/AROB<Impl>::squash(InstSeqNum squash_num,unsigned tid)
5072292SN/A{
5082292SN/A    if (isEmpty()) {
5092292SN/A        DPRINTF(ROB, "Does not need to squash due to being empty "
5102292SN/A                "[sn:%i]\n",
5112292SN/A                squash_num);
5122292SN/A
5132292SN/A        return;
5142292SN/A    }
5152292SN/A
5162292SN/A    DPRINTF(ROB, "Starting to squash within the ROB.\n");
5172292SN/A
5182292SN/A    robStatus[tid] = ROBSquashing;
5192292SN/A
5202292SN/A    doneSquashing[tid] = false;
5211060SN/A
5221060SN/A    squashedSeqNum = squash_num;
5231060SN/A
5242292SN/A    if (!instList[tid].empty()) {
5252292SN/A        InstIt tail_thread = instList[tid].end();
5262292SN/A        tail_thread--;
5271060SN/A
5282292SN/A        squashIt[tid] = tail_thread;
5291060SN/A
5302292SN/A        doSquash(tid);
5311858SN/A    }
5321060SN/A}
5332329SN/A/*
5341858SN/Atemplate <class Impl>
5352292SN/Atypename Impl::DynInstPtr
5362292SN/AROB<Impl>::readHeadInst()
5371858SN/A{
5382292SN/A    if (numInstsInROB != 0) {
5392292SN/A        assert((*head)->isInROB()==true);
5402292SN/A        return *head;
5412292SN/A    } else {
5422292SN/A        return dummyInst;
5432292SN/A    }
5442292SN/A}
5452329SN/A*/
5462292SN/Atemplate <class Impl>
5472292SN/Atypename Impl::DynInstPtr
5482292SN/AROB<Impl>::readHeadInst(unsigned tid)
5492292SN/A{
5502292SN/A    if (threadEntries[tid] != 0) {
5512292SN/A        InstIt head_thread = instList[tid].begin();
5521060SN/A
5532292SN/A        assert((*head_thread)->isInROB()==true);
5541858SN/A
5552292SN/A        return *head_thread;
5562292SN/A    } else {
5572292SN/A        return dummyInst;
5582292SN/A    }
5591858SN/A}
5602329SN/A/*
5611061SN/Atemplate <class Impl>
5621060SN/Auint64_t
5631060SN/AROB<Impl>::readHeadPC()
5641060SN/A{
5652292SN/A    //assert(numInstsInROB == countInsts());
5661060SN/A
5672292SN/A    DynInstPtr head_inst = *head;
5681060SN/A
5691060SN/A    return head_inst->readPC();
5701060SN/A}
5711060SN/A
5721061SN/Atemplate <class Impl>
5731060SN/Auint64_t
5742292SN/AROB<Impl>::readHeadPC(unsigned tid)
5752292SN/A{
5762292SN/A    //assert(numInstsInROB == countInsts());
5772292SN/A    InstIt head_thread = instList[tid].begin();
5782292SN/A
5792292SN/A    return (*head_thread)->readPC();
5802292SN/A}
5812292SN/A
5822292SN/A
5832292SN/Atemplate <class Impl>
5842292SN/Auint64_t
5851060SN/AROB<Impl>::readHeadNextPC()
5861060SN/A{
5872292SN/A    //assert(numInstsInROB == countInsts());
5881060SN/A
5892292SN/A    DynInstPtr head_inst = *head;
5901060SN/A
5911060SN/A    return head_inst->readNextPC();
5921060SN/A}
5931060SN/A
5941061SN/Atemplate <class Impl>
5952292SN/Auint64_t
5962292SN/AROB<Impl>::readHeadNextPC(unsigned tid)
5972292SN/A{
5982292SN/A    //assert(numInstsInROB == countInsts());
5992292SN/A    InstIt head_thread = instList[tid].begin();
6002292SN/A
6012292SN/A    return (*head_thread)->readNextPC();
6022292SN/A}
6032292SN/A
6042292SN/Atemplate <class Impl>
6051060SN/AInstSeqNum
6061060SN/AROB<Impl>::readHeadSeqNum()
6071060SN/A{
6082292SN/A    //assert(numInstsInROB == countInsts());
6092292SN/A    DynInstPtr head_inst = *head;
6101060SN/A
6111060SN/A    return head_inst->seqNum;
6121060SN/A}
6131060SN/A
6141061SN/Atemplate <class Impl>
6152292SN/AInstSeqNum
6162292SN/AROB<Impl>::readHeadSeqNum(unsigned tid)
6172292SN/A{
6182292SN/A    InstIt head_thread = instList[tid].begin();
6192292SN/A
6202292SN/A    return ((*head_thread)->seqNum);
6212292SN/A}
6222292SN/A
6232292SN/Atemplate <class Impl>
6242292SN/Atypename Impl::DynInstPtr
6252292SN/AROB<Impl>::readTailInst()
6262292SN/A{
6272292SN/A    //assert(numInstsInROB == countInsts());
6282292SN/A    //assert(tail != instList[0].end());
6292292SN/A
6302292SN/A    return (*tail);
6312292SN/A}
6322329SN/A*/
6332292SN/Atemplate <class Impl>
6342292SN/Atypename Impl::DynInstPtr
6352292SN/AROB<Impl>::readTailInst(unsigned tid)
6362292SN/A{
6372292SN/A    //assert(tail_thread[tid] != instList[tid].end());
6382292SN/A
6392292SN/A    InstIt tail_thread = instList[tid].end();
6402292SN/A    tail_thread--;
6412292SN/A
6422292SN/A    return *tail_thread;
6432292SN/A}
6442292SN/A
6452329SN/A/*
6462292SN/Atemplate <class Impl>
6471060SN/Auint64_t
6481060SN/AROB<Impl>::readTailPC()
6491060SN/A{
6502292SN/A    //assert(numInstsInROB == countInsts());
6511060SN/A
6522292SN/A    //assert(tail != instList[0].end());
6531060SN/A
6541060SN/A    return (*tail)->readPC();
6551060SN/A}
6561060SN/A
6571061SN/Atemplate <class Impl>
6582292SN/Auint64_t
6592292SN/AROB<Impl>::readTailPC(unsigned tid)
6602292SN/A{
6612292SN/A    //assert(tail_thread[tid] != instList[tid].end());
6622292SN/A
6632292SN/A    InstIt tail_thread = instList[tid].end();
6642292SN/A    tail_thread--;
6652292SN/A
6662292SN/A    return (*tail_thread)->readPC();
6672292SN/A}
6682292SN/A
6692292SN/Atemplate <class Impl>
6701060SN/AInstSeqNum
6711060SN/AROB<Impl>::readTailSeqNum()
6721060SN/A{
6731060SN/A    // Return the last sequence number that has not been squashed.  Other
6741060SN/A    // stages can use it to squash any instructions younger than the current
6751060SN/A    // tail.
6761060SN/A    return (*tail)->seqNum;
6771060SN/A}
6781060SN/A
6792292SN/Atemplate <class Impl>
6802292SN/AInstSeqNum
6812292SN/AROB<Impl>::readTailSeqNum(unsigned tid)
6822292SN/A{
6832292SN/A    // Return the last sequence number that has not been squashed.  Other
6842292SN/A    // stages can use it to squash any instructions younger than the current
6852292SN/A    // tail.
6862292SN/A    //    assert(tail_thread[tid] != instList[tid].end());
6872292SN/A
6882292SN/A    InstIt tail_thread = instList[tid].end();
6892292SN/A    tail_thread--;
6902292SN/A
6912292SN/A    return (*tail_thread)->seqNum;
6922292SN/A}
6932329SN/A*/
694