rob.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo: Probably add in support for scheduling events (more than one as
30// well) on the case of the ROB being empty or full.  Considering tracking
31// free entries instead of insts in ROB.  Differentiate between squashing
32// all instructions after the instruction, and all instructions after *and*
33// including that instruction.
34
35#ifndef __CPU_O3_CPU_ROB_HH__
36#define __CPU_O3_CPU_ROB_HH__
37
38#include <utility>
39#include <vector>
40
41/**
42 * ROB class.  Uses the instruction list that exists within the CPU to
43 * represent the ROB.  This class doesn't contain that list, but instead
44 * a pointer to the CPU to get access to the list.  The ROB, in this first
45 * implementation, is largely what drives squashing.
46 */
47template <class Impl>
48class ROB
49{
50  protected:
51    typedef TheISA::RegIndex RegIndex;
52  public:
53    //Typedefs from the Impl.
54    typedef typename Impl::FullCPU FullCPU;
55    typedef typename Impl::DynInstPtr DynInstPtr;
56
57    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo_t;
58    typedef typename list<DynInstPtr>::iterator InstIt_t;
59
60  public:
61    /** ROB constructor.
62     *  @param _numEntries Number of entries in ROB.
63     *  @param _squashWidth Number of instructions that can be squashed in a
64     *                       single cycle.
65     */
66    ROB(unsigned _numEntries, unsigned _squashWidth);
67
68    /** Function to set the CPU pointer, necessary due to which object the ROB
69     *  is created within.
70     *  @param cpu_ptr Pointer to the implementation specific full CPU object.
71     */
72    void setCPU(FullCPU *cpu_ptr);
73
74    /** Function to insert an instruction into the ROB.  The parameter inst is
75     *  not truly required, but is useful for checking correctness.  Note
76     *  that whatever calls this function must ensure that there is enough
77     *  space within the ROB for the new instruction.
78     *  @param inst The instruction being inserted into the ROB.
79     *  @todo Remove the parameter once correctness is ensured.
80     */
81    void insertInst(DynInstPtr &inst);
82
83    /** Returns pointer to the head instruction within the ROB.  There is
84     *  no guarantee as to the return value if the ROB is empty.
85     *  @retval Pointer to the DynInst that is at the head of the ROB.
86     */
87    DynInstPtr readHeadInst() { return cpu->instList.front(); }
88
89    DynInstPtr readTailInst() { return (*tail); }
90
91    void retireHead();
92
93    bool isHeadReady();
94
95    unsigned numFreeEntries();
96
97    bool isFull()
98    { return numInstsInROB == numEntries; }
99
100    bool isEmpty()
101    { return numInstsInROB == 0; }
102
103    void doSquash();
104
105    void squash(InstSeqNum squash_num);
106
107    uint64_t readHeadPC();
108
109    uint64_t readHeadNextPC();
110
111    InstSeqNum readHeadSeqNum();
112
113    uint64_t readTailPC();
114
115    InstSeqNum readTailSeqNum();
116
117    /** Checks if the ROB is still in the process of squashing instructions.
118     *  @retval Whether or not the ROB is done squashing.
119     */
120    bool isDoneSquashing() const { return doneSquashing; }
121
122    /** This is more of a debugging function than anything.  Use
123     *  numInstsInROB to get the instructions in the ROB unless you are
124     *  double checking that variable.
125     */
126    int countInsts();
127
128  private:
129
130    /** Pointer to the CPU. */
131    FullCPU *cpu;
132
133    /** Number of instructions in the ROB. */
134    unsigned numEntries;
135
136    /** Number of instructions that can be squashed in a single cycle. */
137    unsigned squashWidth;
138
139    /** Iterator pointing to the instruction which is the last instruction
140     *  in the ROB.  This may at times be invalid (ie when the ROB is empty),
141     *  however it should never be incorrect.
142     */
143    InstIt_t tail;
144
145    /** Iterator used for walking through the list of instructions when
146     *  squashing.  Used so that there is persistent state between cycles;
147     *  when squashing, the instructions are marked as squashed but not
148     *  immediately removed, meaning the tail iterator remains the same before
149     *  and after a squash.
150     *  This will always be set to cpu->instList.end() if it is invalid.
151     */
152    InstIt_t squashIt;
153
154    /** Number of instructions in the ROB. */
155    int numInstsInROB;
156
157    /** The sequence number of the squashed instruction. */
158    InstSeqNum squashedSeqNum;
159
160    /** Is the ROB done squashing. */
161    bool doneSquashing;
162};
163
164#endif //__CPU_O3_CPU_ROB_HH__
165