rob.hh revision 6221
11689SN/A/*
22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
292831Sksewell@umich.edu *          Korey Sewell
301689SN/A */
311689SN/A
322292SN/A#ifndef __CPU_O3_ROB_HH__
332292SN/A#define __CPU_O3_ROB_HH__
341060SN/A
352292SN/A#include <string>
361461SN/A#include <utility>
371461SN/A#include <vector>
381060SN/A
391060SN/A/**
402292SN/A * ROB class.  The ROB is largely what drives squashing.
411060SN/A */
421061SN/Atemplate <class Impl>
431060SN/Aclass ROB
441060SN/A{
452107SN/A  protected:
462107SN/A    typedef TheISA::RegIndex RegIndex;
471060SN/A  public:
481060SN/A    //Typedefs from the Impl.
492733Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
501061SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
511060SN/A
522292SN/A    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
532292SN/A    typedef typename std::list<DynInstPtr>::iterator InstIt;
542292SN/A
552292SN/A    /** Possible ROB statuses. */
562292SN/A    enum Status {
572292SN/A        Running,
582292SN/A        Idle,
592329SN/A        ROBSquashing
602292SN/A    };
612292SN/A
622292SN/A    /** SMT ROB Sharing Policy */
632292SN/A    enum ROBPolicy{
642292SN/A        Dynamic,
652292SN/A        Partitioned,
662292SN/A        Threshold
672292SN/A    };
682292SN/A
692292SN/A  private:
702292SN/A    /** Per-thread ROB status. */
712292SN/A    Status robStatus[Impl::MaxThreads];
722292SN/A
732292SN/A    /** ROB resource sharing policy for SMT mode. */
742292SN/A    ROBPolicy robPolicy;
751060SN/A
761060SN/A  public:
771060SN/A    /** ROB constructor.
782292SN/A     *  @param _numEntries      Number of entries in ROB.
792292SN/A     *  @param _squashWidth     Number of instructions that can be squashed in a
802292SN/A     *                          single cycle.
812292SN/A     *  @param _smtROBPolicy    ROB Partitioning Scheme for SMT.
822292SN/A     *  @param _smtROBThreshold Max Resources(by %) a thread can have in the ROB.
832292SN/A     *  @param _numThreads      The number of active threads.
841060SN/A     */
854329Sktlim@umich.edu    ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
864329Sktlim@umich.edu        std::string smtROBPolicy, unsigned _smtROBThreshold,
876221Snate@binkert.org        ThreadID _numThreads);
882292SN/A
892292SN/A    std::string name() const;
901060SN/A
912292SN/A    /** Sets pointer to the list of active threads.
922292SN/A     *  @param at_ptr Pointer to the list of active threads.
932292SN/A     */
946221Snate@binkert.org    void setActiveThreads(std::list<ThreadID> *at_ptr);
952292SN/A
962348SN/A    /** Switches out the ROB. */
972307SN/A    void switchOut();
982307SN/A
992348SN/A    /** Takes over another CPU's thread. */
1002307SN/A    void takeOverFrom();
1012307SN/A
1022292SN/A    /** Function to insert an instruction into the ROB. Note that whatever
1032292SN/A     *  calls this function must ensure that there is enough space within the
1042292SN/A     *  ROB for the new instruction.
1051763SN/A     *  @param inst The instruction being inserted into the ROB.
1061060SN/A     */
1071061SN/A    void insertInst(DynInstPtr &inst);
1081060SN/A
1091060SN/A    /** Returns pointer to the head instruction within the ROB.  There is
1101060SN/A     *  no guarantee as to the return value if the ROB is empty.
1111060SN/A     *  @retval Pointer to the DynInst that is at the head of the ROB.
1121060SN/A     */
1132329SN/A//    DynInstPtr readHeadInst();
1141060SN/A
1152292SN/A    /** Returns a pointer to the head instruction of a specific thread within
1162292SN/A     *  the ROB.
1172292SN/A     *  @return Pointer to the DynInst that is at the head of the ROB.
1182292SN/A     */
1196221Snate@binkert.org    DynInstPtr readHeadInst(ThreadID tid);
1201060SN/A
1212292SN/A    /** Returns pointer to the tail instruction within the ROB.  There is
1222292SN/A     *  no guarantee as to the return value if the ROB is empty.
1232292SN/A     *  @retval Pointer to the DynInst that is at the tail of the ROB.
1242292SN/A     */
1252329SN/A//    DynInstPtr readTailInst();
1261060SN/A
1272292SN/A    /** Returns a pointer to the tail instruction of a specific thread within
1282292SN/A     *  the ROB.
1292292SN/A     *  @return Pointer to the DynInst that is at the tail of the ROB.
1302292SN/A     */
1316221Snate@binkert.org    DynInstPtr readTailInst(ThreadID tid);
1321060SN/A
1332292SN/A    /** Retires the head instruction, removing it from the ROB. */
1342329SN/A//    void retireHead();
1352107SN/A
1362292SN/A    /** Retires the head instruction of a specific thread, removing it from the
1372292SN/A     *  ROB.
1382292SN/A     */
1396221Snate@binkert.org    void retireHead(ThreadID tid);
1402292SN/A
1412292SN/A    /** Is the oldest instruction across all threads ready. */
1422329SN/A//    bool isHeadReady();
1432107SN/A
1442292SN/A    /** Is the oldest instruction across a particular thread ready. */
1456221Snate@binkert.org    bool isHeadReady(ThreadID tid);
1462292SN/A
1472292SN/A    /** Is there any commitable head instruction across all threads ready. */
1482292SN/A    bool canCommit();
1492292SN/A
1502292SN/A    /** Re-adjust ROB partitioning. */
1512292SN/A    void resetEntries();
1522292SN/A
1532292SN/A    /** Number of entries needed For 'num_threads' amount of threads. */
1546221Snate@binkert.org    int entryAmount(ThreadID num_threads);
1552292SN/A
1562292SN/A    /** Returns the number of total free entries in the ROB. */
1571060SN/A    unsigned numFreeEntries();
1581060SN/A
1592292SN/A    /** Returns the number of free entries in a specific ROB paritition. */
1606221Snate@binkert.org    unsigned numFreeEntries(ThreadID tid);
1612292SN/A
1622292SN/A    /** Returns the maximum number of entries for a specific thread. */
1636221Snate@binkert.org    unsigned getMaxEntries(ThreadID tid)
1642292SN/A    { return maxEntries[tid]; }
1652292SN/A
1662292SN/A    /** Returns the number of entries being used by a specific thread. */
1676221Snate@binkert.org    unsigned getThreadEntries(ThreadID tid)
1682292SN/A    { return threadEntries[tid]; }
1692292SN/A
1702292SN/A    /** Returns if the ROB is full. */
1711060SN/A    bool isFull()
1721060SN/A    { return numInstsInROB == numEntries; }
1731060SN/A
1742292SN/A    /** Returns if a specific thread's partition is full. */
1756221Snate@binkert.org    bool isFull(ThreadID tid)
1762292SN/A    { return threadEntries[tid] == numEntries; }
1772292SN/A
1782292SN/A    /** Returns if the ROB is empty. */
1791060SN/A    bool isEmpty()
1801060SN/A    { return numInstsInROB == 0; }
1811060SN/A
1822292SN/A    /** Returns if a specific thread's partition is empty. */
1836221Snate@binkert.org    bool isEmpty(ThreadID tid)
1842292SN/A    { return threadEntries[tid] == 0; }
1851060SN/A
1862292SN/A    /** Executes the squash, marking squashed instructions. */
1876221Snate@binkert.org    void doSquash(ThreadID tid);
1881060SN/A
1892292SN/A    /** Squashes all instructions younger than the given sequence number for
1902292SN/A     *  the specific thread.
1912292SN/A     */
1926221Snate@binkert.org    void squash(InstSeqNum squash_num, ThreadID tid);
1931060SN/A
1942292SN/A    /** Updates the head instruction with the new oldest instruction. */
1952292SN/A    void updateHead();
1961060SN/A
1972292SN/A    /** Updates the tail instruction with the new youngest instruction. */
1982292SN/A    void updateTail();
1991060SN/A
2002292SN/A    /** Reads the PC of the oldest head instruction. */
2012329SN/A//    uint64_t readHeadPC();
2021060SN/A
2032292SN/A    /** Reads the PC of the head instruction of a specific thread. */
2046221Snate@binkert.org//    uint64_t readHeadPC(ThreadID tid);
2052292SN/A
2062292SN/A    /** Reads the next PC of the oldest head instruction. */
2072329SN/A//    uint64_t readHeadNextPC();
2082107SN/A
2092292SN/A    /** Reads the next PC of the head instruction of a specific thread. */
2106221Snate@binkert.org//    uint64_t readHeadNextPC(ThreadID tid);
2112292SN/A
2122292SN/A    /** Reads the sequence number of the oldest head instruction. */
2132329SN/A//    InstSeqNum readHeadSeqNum();
2142107SN/A
2152292SN/A    /** Reads the sequence number of the head instruction of a specific thread.
2162292SN/A     */
2176221Snate@binkert.org//    InstSeqNum readHeadSeqNum(ThreadID tid);
2182292SN/A
2192292SN/A    /** Reads the PC of the youngest tail instruction. */
2202329SN/A//    uint64_t readTailPC();
2212107SN/A
2222292SN/A    /** Reads the PC of the tail instruction of a specific thread. */
2236221Snate@binkert.org//    uint64_t readTailPC(ThreadID tid);
2242292SN/A
2252292SN/A    /** Reads the sequence number of the youngest tail instruction. */
2262329SN/A//    InstSeqNum readTailSeqNum();
2272107SN/A
2282292SN/A    /** Reads the sequence number of tail instruction of a specific thread. */
2296221Snate@binkert.org//    InstSeqNum readTailSeqNum(ThreadID tid);
2301060SN/A
2311060SN/A    /** Checks if the ROB is still in the process of squashing instructions.
2321060SN/A     *  @retval Whether or not the ROB is done squashing.
2331060SN/A     */
2346221Snate@binkert.org    bool isDoneSquashing(ThreadID tid) const
2352292SN/A    { return doneSquashing[tid]; }
2362292SN/A
2372292SN/A    /** Checks if the ROB is still in the process of squashing instructions for
2382292SN/A     *  any thread.
2392292SN/A     */
2402292SN/A    bool isDoneSquashing();
2411060SN/A
2421060SN/A    /** This is more of a debugging function than anything.  Use
2431060SN/A     *  numInstsInROB to get the instructions in the ROB unless you are
2441060SN/A     *  double checking that variable.
2451060SN/A     */
2461060SN/A    int countInsts();
2471060SN/A
2482292SN/A    /** This is more of a debugging function than anything.  Use
2492292SN/A     *  threadEntries to get the instructions in the ROB unless you are
2502292SN/A     *  double checking that variable.
2512292SN/A     */
2526221Snate@binkert.org    int countInsts(ThreadID tid);
2532292SN/A
2541060SN/A  private:
2551060SN/A    /** Pointer to the CPU. */
2562733Sktlim@umich.edu    O3CPU *cpu;
2571060SN/A
2582292SN/A    /** Active Threads in CPU */
2596221Snate@binkert.org    std::list<ThreadID> *activeThreads;
2602292SN/A
2611061SN/A    /** Number of instructions in the ROB. */
2621060SN/A    unsigned numEntries;
2631060SN/A
2642292SN/A    /** Entries Per Thread */
2652292SN/A    unsigned threadEntries[Impl::MaxThreads];
2662292SN/A
2672292SN/A    /** Max Insts a Thread Can Have in the ROB */
2682292SN/A    unsigned maxEntries[Impl::MaxThreads];
2692292SN/A
2702292SN/A    /** ROB List of Instructions */
2712292SN/A    std::list<DynInstPtr> instList[Impl::MaxThreads];
2722292SN/A
2731060SN/A    /** Number of instructions that can be squashed in a single cycle. */
2741060SN/A    unsigned squashWidth;
2751060SN/A
2762292SN/A  public:
2771061SN/A    /** Iterator pointing to the instruction which is the last instruction
2781061SN/A     *  in the ROB.  This may at times be invalid (ie when the ROB is empty),
2791061SN/A     *  however it should never be incorrect.
2801061SN/A     */
2812292SN/A    InstIt tail;
2821060SN/A
2832292SN/A    /** Iterator pointing to the instruction which is the first instruction in
2842292SN/A     *  in the ROB*/
2852292SN/A    InstIt head;
2862292SN/A
2872292SN/A  private:
2881061SN/A    /** Iterator used for walking through the list of instructions when
2891061SN/A     *  squashing.  Used so that there is persistent state between cycles;
2901061SN/A     *  when squashing, the instructions are marked as squashed but not
2911061SN/A     *  immediately removed, meaning the tail iterator remains the same before
2921061SN/A     *  and after a squash.
2931061SN/A     *  This will always be set to cpu->instList.end() if it is invalid.
2941061SN/A     */
2952292SN/A    InstIt squashIt[Impl::MaxThreads];
2961060SN/A
2972292SN/A  public:
2981061SN/A    /** Number of instructions in the ROB. */
2991060SN/A    int numInstsInROB;
3001060SN/A
3012348SN/A    /** Dummy instruction returned if there are no insts left. */
3022292SN/A    DynInstPtr dummyInst;
3032292SN/A
3042292SN/A  private:
3051060SN/A    /** The sequence number of the squashed instruction. */
3062877Sksewell@umich.edu    InstSeqNum squashedSeqNum[Impl::MaxThreads];
3071060SN/A
3081060SN/A    /** Is the ROB done squashing. */
3092292SN/A    bool doneSquashing[Impl::MaxThreads];
3102292SN/A
3112292SN/A    /** Number of active threads. */
3126221Snate@binkert.org    ThreadID numThreads;
3131060SN/A};
3141060SN/A
3152292SN/A#endif //__CPU_O3_ROB_HH__
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