rename_map.hh revision 13601:f5c84915eb7f
14120Sgblack@eecs.umich.edu/* 24120Sgblack@eecs.umich.edu * Copyright (c) 2015-2016 ARM Limited 34120Sgblack@eecs.umich.edu * All rights reserved. 44120Sgblack@eecs.umich.edu * 54120Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 64120Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 74120Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 84120Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 94120Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 104120Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 114120Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 124120Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 134120Sgblack@eecs.umich.edu * 144120Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 154120Sgblack@eecs.umich.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 164120Sgblack@eecs.umich.edu * All rights reserved. 174120Sgblack@eecs.umich.edu * 184120Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194120Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204120Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224120Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234120Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244120Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254120Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264120Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274120Sgblack@eecs.umich.edu * this software without specific prior written permission. 284120Sgblack@eecs.umich.edu * 294120Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304120Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314120Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324120Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334120Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344120Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354120Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364120Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374120Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384120Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394120Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404120Sgblack@eecs.umich.edu * 414120Sgblack@eecs.umich.edu * Authors: Kevin Lim 424120Sgblack@eecs.umich.edu * Steve Reinhardt 434120Sgblack@eecs.umich.edu */ 444120Sgblack@eecs.umich.edu 454120Sgblack@eecs.umich.edu#ifndef __CPU_O3_RENAME_MAP_HH__ 464120Sgblack@eecs.umich.edu#define __CPU_O3_RENAME_MAP_HH__ 474120Sgblack@eecs.umich.edu 484120Sgblack@eecs.umich.edu#include <iostream> 494120Sgblack@eecs.umich.edu#include <utility> 504120Sgblack@eecs.umich.edu#include <vector> 514120Sgblack@eecs.umich.edu 524120Sgblack@eecs.umich.edu#include "arch/types.hh" 534120Sgblack@eecs.umich.edu#include "config/the_isa.hh" 544120Sgblack@eecs.umich.edu#include "cpu/o3/free_list.hh" 554120Sgblack@eecs.umich.edu#include "cpu/o3/regfile.hh" 564120Sgblack@eecs.umich.edu#include "cpu/reg_class.hh" 574120Sgblack@eecs.umich.edu#include "enums/VecRegRenameMode.hh" 584120Sgblack@eecs.umich.edu 594120Sgblack@eecs.umich.edu/** 604120Sgblack@eecs.umich.edu * Register rename map for a single class of registers (e.g., integer 615647Sgblack@eecs.umich.edu * or floating point). Because the register class is implicitly 625086Sgblack@eecs.umich.edu * determined by the rename map instance being accessed, all 635655Sgblack@eecs.umich.edu * architectural register index parameters and values in this class 645654Sgblack@eecs.umich.edu * are relative (e.g., %fp2 is just index 2). 655086Sgblack@eecs.umich.edu */ 665648Sgblack@eecs.umich.educlass SimpleRenameMap 675651Sgblack@eecs.umich.edu{ 685647Sgblack@eecs.umich.edu private: 695647Sgblack@eecs.umich.edu using Arch2PhysMap = std::vector<PhysRegIdPtr>; 705647Sgblack@eecs.umich.edu /** The acutal arch-to-phys register map */ 715647Sgblack@eecs.umich.edu Arch2PhysMap map; 725810Sgblack@eecs.umich.edu public: 734120Sgblack@eecs.umich.edu using iterator = Arch2PhysMap::iterator; 745704Snate@binkert.org using const_iterator = Arch2PhysMap::const_iterator; 755086Sgblack@eecs.umich.edu private: 765651Sgblack@eecs.umich.edu 775086Sgblack@eecs.umich.edu /** 785647Sgblack@eecs.umich.edu * Pointer to the free list from which new physical registers 795654Sgblack@eecs.umich.edu * should be allocated in rename() 805647Sgblack@eecs.umich.edu */ 815654Sgblack@eecs.umich.edu SimpleFreeList *freeList; 825691Sgblack@eecs.umich.edu 835691Sgblack@eecs.umich.edu /** 845691Sgblack@eecs.umich.edu * The architectural index of the zero register. This register is 855691Sgblack@eecs.umich.edu * mapped but read-only, so we ignore attempts to rename it via 865691Sgblack@eecs.umich.edu * the rename() method. If there is no such register for this map 875691Sgblack@eecs.umich.edu * table, it should be set to an invalid index so that it never 885691Sgblack@eecs.umich.edu * matches. 895691Sgblack@eecs.umich.edu */ 905691Sgblack@eecs.umich.edu RegId zeroReg; 915691Sgblack@eecs.umich.edu 925691Sgblack@eecs.umich.edu public: 935654Sgblack@eecs.umich.edu 945654Sgblack@eecs.umich.edu SimpleRenameMap(); 955654Sgblack@eecs.umich.edu 965648Sgblack@eecs.umich.edu ~SimpleRenameMap() {}; 975648Sgblack@eecs.umich.edu 985647Sgblack@eecs.umich.edu /** 995647Sgblack@eecs.umich.edu * Because we have an array of rename maps (one per thread) in the CPU, 1005647Sgblack@eecs.umich.edu * it's awkward to initialize this object via the constructor. 1015691Sgblack@eecs.umich.edu * Instead, this method is used for initialization. 1025691Sgblack@eecs.umich.edu */ 1035647Sgblack@eecs.umich.edu void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg); 1045691Sgblack@eecs.umich.edu 1055691Sgblack@eecs.umich.edu /** 1065647Sgblack@eecs.umich.edu * Pair of a physical register and a physical register. Used to 1075647Sgblack@eecs.umich.edu * return the physical register that a logical register has been 1085647Sgblack@eecs.umich.edu * renamed to, and the previous physical register that the same 1095647Sgblack@eecs.umich.edu * logical register was previously mapped to. 1105691Sgblack@eecs.umich.edu */ 1115691Sgblack@eecs.umich.edu typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo; 1125691Sgblack@eecs.umich.edu 1135691Sgblack@eecs.umich.edu /** 1145691Sgblack@eecs.umich.edu * Tell rename map to get a new free physical register to remap 1155647Sgblack@eecs.umich.edu * the specified architectural register. 1165647Sgblack@eecs.umich.edu * @param arch_reg The architectural register to remap. 1175647Sgblack@eecs.umich.edu * @return A RenameInfo pair indicating both the new and previous 1185647Sgblack@eecs.umich.edu * physical registers. 1195647Sgblack@eecs.umich.edu */ 1205654Sgblack@eecs.umich.edu RenameInfo rename(const RegId& arch_reg); 1215655Sgblack@eecs.umich.edu 1225655Sgblack@eecs.umich.edu /** 1235655Sgblack@eecs.umich.edu * Look up the physical register mapped to an architectural register. 1245655Sgblack@eecs.umich.edu * @param arch_reg The architectural register to look up. 1255691Sgblack@eecs.umich.edu * @return The physical register it is currently mapped to. 1265655Sgblack@eecs.umich.edu */ 1275691Sgblack@eecs.umich.edu PhysRegIdPtr lookup(const RegId& arch_reg) const 1285655Sgblack@eecs.umich.edu { 1295691Sgblack@eecs.umich.edu assert(arch_reg.flatIndex() <= map.size()); 1305655Sgblack@eecs.umich.edu return map[arch_reg.flatIndex()]; 1315691Sgblack@eecs.umich.edu } 1326050Sgblack@eecs.umich.edu 1336050Sgblack@eecs.umich.edu /** 1346066Sgblack@eecs.umich.edu * Update rename map with a specific mapping. Generally used to 1355655Sgblack@eecs.umich.edu * roll back to old mappings on a squash. 1365655Sgblack@eecs.umich.edu * @param arch_reg The architectural register to remap. 1375655Sgblack@eecs.umich.edu * @param phys_reg The physical register to remap it to. 1385655Sgblack@eecs.umich.edu */ 1396069Sgblack@eecs.umich.edu void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) 1406069Sgblack@eecs.umich.edu { 1416069Sgblack@eecs.umich.edu assert(arch_reg.flatIndex() <= map.size()); 1425655Sgblack@eecs.umich.edu map[arch_reg.flatIndex()] = phys_reg; 1435654Sgblack@eecs.umich.edu } 1445654Sgblack@eecs.umich.edu 1455654Sgblack@eecs.umich.edu /** Return the number of free entries on the associated free list. */ 1465654Sgblack@eecs.umich.edu unsigned numFreeEntries() const { return freeList->numFreeRegs(); } 1475654Sgblack@eecs.umich.edu 1485654Sgblack@eecs.umich.edu /** Forward begin/cbegin to the map. */ 1495654Sgblack@eecs.umich.edu /** @{ */ 1505654Sgblack@eecs.umich.edu iterator begin() { return map.begin(); } 1515654Sgblack@eecs.umich.edu const_iterator begin() const { return map.begin(); } 1525654Sgblack@eecs.umich.edu const_iterator cbegin() const { return map.cbegin(); } 1535654Sgblack@eecs.umich.edu /** @} */ 1545654Sgblack@eecs.umich.edu 1555654Sgblack@eecs.umich.edu /** Forward end/cend to the map. */ 1565654Sgblack@eecs.umich.edu /** @{ */ 1575654Sgblack@eecs.umich.edu iterator end() { return map.end(); } 1585654Sgblack@eecs.umich.edu const_iterator end() const { return map.end(); } 1595654Sgblack@eecs.umich.edu const_iterator cend() const { return map.cend(); } 1605654Sgblack@eecs.umich.edu /** @} */ 1615654Sgblack@eecs.umich.edu}; 1625654Sgblack@eecs.umich.edu 1635654Sgblack@eecs.umich.edu/** 1645654Sgblack@eecs.umich.edu * Unified register rename map for all classes of registers. Wraps a 1655654Sgblack@eecs.umich.edu * set of class-specific rename maps. Methods that do not specify a 1665654Sgblack@eecs.umich.edu * register class (e.g., rename()) take register ids, 1675654Sgblack@eecs.umich.edu * while methods that do specify a register class (e.g., renameInt()) 1685654Sgblack@eecs.umich.edu * take register indices. 1695654Sgblack@eecs.umich.edu */ 1705654Sgblack@eecs.umich.educlass UnifiedRenameMap 1715654Sgblack@eecs.umich.edu{ 1725654Sgblack@eecs.umich.edu private: 1735654Sgblack@eecs.umich.edu static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg; 1745654Sgblack@eecs.umich.edu using VecReg = TheISA::VecReg; 1756101Sgblack@eecs.umich.edu 1765654Sgblack@eecs.umich.edu /** The integer register rename map */ 1775654Sgblack@eecs.umich.edu SimpleRenameMap intMap; 1785654Sgblack@eecs.umich.edu 1795654Sgblack@eecs.umich.edu /** The floating-point register rename map */ 1805654Sgblack@eecs.umich.edu SimpleRenameMap floatMap; 1816101Sgblack@eecs.umich.edu 1825654Sgblack@eecs.umich.edu /** The condition-code register rename map */ 1835654Sgblack@eecs.umich.edu SimpleRenameMap ccMap; 1845654Sgblack@eecs.umich.edu 1855654Sgblack@eecs.umich.edu /** The vector register rename map */ 1865654Sgblack@eecs.umich.edu SimpleRenameMap vecMap; 1876101Sgblack@eecs.umich.edu 1885654Sgblack@eecs.umich.edu /** The vector element register rename map */ 1895654Sgblack@eecs.umich.edu SimpleRenameMap vecElemMap; 1905691Sgblack@eecs.umich.edu 1915691Sgblack@eecs.umich.edu using VecMode = Enums::VecRegRenameMode; 1925810Sgblack@eecs.umich.edu VecMode vecMode; 1935810Sgblack@eecs.umich.edu 1946136Sgblack@eecs.umich.edu /** 1956136Sgblack@eecs.umich.edu * The register file object is used only to get PhysRegIdPtr 1965086Sgblack@eecs.umich.edu * on MiscRegs, as they are stored in it. 1975654Sgblack@eecs.umich.edu */ 1985654Sgblack@eecs.umich.edu PhysRegFile *regFile; 1995654Sgblack@eecs.umich.edu 2005647Sgblack@eecs.umich.edu public: 2015647Sgblack@eecs.umich.edu 2026041Sgblack@eecs.umich.edu typedef SimpleRenameMap::RenameInfo RenameInfo; 2035810Sgblack@eecs.umich.edu 2045810Sgblack@eecs.umich.edu /** Default constructor. init() must be called prior to use. */ 2055704Snate@binkert.org UnifiedRenameMap() : regFile(nullptr) {}; 2065648Sgblack@eecs.umich.edu 2075648Sgblack@eecs.umich.edu /** Destructor. */ 2085648Sgblack@eecs.umich.edu ~UnifiedRenameMap() {}; 2095648Sgblack@eecs.umich.edu 2105647Sgblack@eecs.umich.edu /** Initializes rename map with given parameters. */ 2115647Sgblack@eecs.umich.edu void init(PhysRegFile *_regFile, 2125086Sgblack@eecs.umich.edu RegIndex _intZeroReg, 2135647Sgblack@eecs.umich.edu RegIndex _floatZeroReg, 2145647Sgblack@eecs.umich.edu UnifiedFreeList *freeList, 2155647Sgblack@eecs.umich.edu VecMode _mode); 2165654Sgblack@eecs.umich.edu 2175654Sgblack@eecs.umich.edu /** 2185654Sgblack@eecs.umich.edu * Tell rename map to get a new free physical register to remap 2195648Sgblack@eecs.umich.edu * the specified architectural register. This version takes a 2205648Sgblack@eecs.umich.edu * RegId and reads the appropriate class-specific rename table. 2215651Sgblack@eecs.umich.edu * @param arch_reg The architectural register id to remap. 2226064Sgblack@eecs.umich.edu * @return A RenameInfo pair indicating both the new and previous 2235647Sgblack@eecs.umich.edu * physical registers. 2245691Sgblack@eecs.umich.edu */ 2255691Sgblack@eecs.umich.edu RenameInfo rename(const RegId& arch_reg) 2265691Sgblack@eecs.umich.edu { 2275691Sgblack@eecs.umich.edu switch (arch_reg.classValue()) { 2285691Sgblack@eecs.umich.edu case IntRegClass: 2295691Sgblack@eecs.umich.edu return intMap.rename(arch_reg); 2305691Sgblack@eecs.umich.edu case FloatRegClass: 2315691Sgblack@eecs.umich.edu return floatMap.rename(arch_reg); 2325691Sgblack@eecs.umich.edu case VecRegClass: 2336041Sgblack@eecs.umich.edu assert(vecMode == Enums::Full); 2346041Sgblack@eecs.umich.edu return vecMap.rename(arch_reg); 2355651Sgblack@eecs.umich.edu case VecElemClass: 2365654Sgblack@eecs.umich.edu assert(vecMode == Enums::Elem); 2375654Sgblack@eecs.umich.edu return vecElemMap.rename(arch_reg); 2385654Sgblack@eecs.umich.edu case CCRegClass: 2395654Sgblack@eecs.umich.edu return ccMap.rename(arch_reg); 2405654Sgblack@eecs.umich.edu case MiscRegClass: 2415654Sgblack@eecs.umich.edu { 2425654Sgblack@eecs.umich.edu // misc regs aren't really renamed, just remapped 2435654Sgblack@eecs.umich.edu PhysRegIdPtr phys_reg = lookup(arch_reg); 2445654Sgblack@eecs.umich.edu // Set the new register to the previous one to keep the same 2455654Sgblack@eecs.umich.edu // mapping throughout the execution. 2465654Sgblack@eecs.umich.edu return RenameInfo(phys_reg, phys_reg); 2475648Sgblack@eecs.umich.edu } 2485648Sgblack@eecs.umich.edu 2495704Snate@binkert.org default: 2505704Snate@binkert.org panic("rename rename(): unknown reg class %s\n", 2515647Sgblack@eecs.umich.edu arch_reg.className()); 2525648Sgblack@eecs.umich.edu } 2535648Sgblack@eecs.umich.edu } 2545648Sgblack@eecs.umich.edu 2555654Sgblack@eecs.umich.edu /** 2565654Sgblack@eecs.umich.edu * Look up the physical register mapped to an architectural register. 2575654Sgblack@eecs.umich.edu * This version takes a flattened architectural register id 2585654Sgblack@eecs.umich.edu * and calls the appropriate class-specific rename table. 2596041Sgblack@eecs.umich.edu * @param arch_reg The architectural register to look up. 2605086Sgblack@eecs.umich.edu * @return The physical register it is currently mapped to. 2615654Sgblack@eecs.umich.edu */ 2625654Sgblack@eecs.umich.edu PhysRegIdPtr lookup(const RegId& arch_reg) const 2635654Sgblack@eecs.umich.edu { 2645651Sgblack@eecs.umich.edu switch (arch_reg.classValue()) { 2655704Snate@binkert.org case IntRegClass: 2665704Snate@binkert.org return intMap.lookup(arch_reg); 2675704Snate@binkert.org 2685086Sgblack@eecs.umich.edu case FloatRegClass: 2695654Sgblack@eecs.umich.edu return floatMap.lookup(arch_reg); 2705654Sgblack@eecs.umich.edu 2715654Sgblack@eecs.umich.edu case VecRegClass: 2725086Sgblack@eecs.umich.edu assert(vecMode == Enums::Full); 2735704Snate@binkert.org return vecMap.lookup(arch_reg); 2745704Snate@binkert.org 2755086Sgblack@eecs.umich.edu case VecElemClass: 2765133Sgblack@eecs.umich.edu assert(vecMode == Enums::Elem); 2775086Sgblack@eecs.umich.edu return vecElemMap.lookup(arch_reg); 2785086Sgblack@eecs.umich.edu 2795704Snate@binkert.org case CCRegClass: 2805704Snate@binkert.org return ccMap.lookup(arch_reg); 2815086Sgblack@eecs.umich.edu 2825133Sgblack@eecs.umich.edu case MiscRegClass: 2835086Sgblack@eecs.umich.edu // misc regs aren't really renamed, they keep the same 2845654Sgblack@eecs.umich.edu // mapping throughout the execution. 2855654Sgblack@eecs.umich.edu return regFile->getMiscRegId(arch_reg.flatIndex()); 2865654Sgblack@eecs.umich.edu 2875654Sgblack@eecs.umich.edu default: 2885654Sgblack@eecs.umich.edu panic("rename lookup(): unknown reg class %s\n", 2895704Snate@binkert.org arch_reg.className()); 2905704Snate@binkert.org } 2915654Sgblack@eecs.umich.edu } 2925654Sgblack@eecs.umich.edu 2935654Sgblack@eecs.umich.edu /** 2945654Sgblack@eecs.umich.edu * Update rename map with a specific mapping. Generally used to 2955704Snate@binkert.org * roll back to old mappings on a squash. This version takes a 2965704Snate@binkert.org * flattened architectural register id and calls the 2975654Sgblack@eecs.umich.edu * appropriate class-specific rename table. 2985654Sgblack@eecs.umich.edu * @param arch_reg The architectural register to remap. 2995654Sgblack@eecs.umich.edu * @param phys_reg The physical register to remap it to. 3005654Sgblack@eecs.umich.edu */ 3015704Snate@binkert.org void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) 3025704Snate@binkert.org { 3035654Sgblack@eecs.umich.edu switch (arch_reg.classValue()) { 3045704Snate@binkert.org case IntRegClass: 3055654Sgblack@eecs.umich.edu assert(phys_reg->isIntPhysReg()); 3065086Sgblack@eecs.umich.edu return intMap.setEntry(arch_reg, phys_reg); 3075086Sgblack@eecs.umich.edu 3085704Snate@binkert.org case FloatRegClass: 3094120Sgblack@eecs.umich.edu assert(phys_reg->isFloatPhysReg()); 3104120Sgblack@eecs.umich.edu return floatMap.setEntry(arch_reg, phys_reg); 311 312 case VecRegClass: 313 assert(phys_reg->isVectorPhysReg()); 314 assert(vecMode == Enums::Full); 315 return vecMap.setEntry(arch_reg, phys_reg); 316 317 case VecElemClass: 318 assert(phys_reg->isVectorPhysElem()); 319 assert(vecMode == Enums::Elem); 320 return vecElemMap.setEntry(arch_reg, phys_reg); 321 322 case CCRegClass: 323 assert(phys_reg->isCCPhysReg()); 324 return ccMap.setEntry(arch_reg, phys_reg); 325 326 case MiscRegClass: 327 // Misc registers do not actually rename, so don't change 328 // their mappings. We end up here when a commit or squash 329 // tries to update or undo a hardwired misc reg nmapping, 330 // which should always be setting it to what it already is. 331 assert(phys_reg == lookup(arch_reg)); 332 return; 333 334 default: 335 panic("rename setEntry(): unknown reg class %s\n", 336 arch_reg.className()); 337 } 338 } 339 340 /** 341 * Return the minimum number of free entries across all of the 342 * register classes. The minimum is used so we guarantee that 343 * this number of entries is available regardless of which class 344 * of registers is requested. 345 */ 346 unsigned numFreeEntries() const 347 { 348 return std::min( 349 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()), 350 vecMode == Enums::Full ? vecMap.numFreeEntries() 351 : vecElemMap.numFreeEntries()); 352 } 353 354 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); } 355 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); } 356 unsigned numFreeVecEntries() const 357 { 358 return vecMode == Enums::Full 359 ? vecMap.numFreeEntries() 360 : vecElemMap.numFreeEntries(); 361 } 362 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); } 363 364 /** 365 * Return whether there are enough registers to serve the request. 366 */ 367 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs, 368 uint32_t vecElemRegs, uint32_t ccRegs) const 369 { 370 return intRegs <= intMap.numFreeEntries() && 371 floatRegs <= floatMap.numFreeEntries() && 372 vectorRegs <= vecMap.numFreeEntries() && 373 vecElemRegs <= vecElemMap.numFreeEntries() && 374 ccRegs <= ccMap.numFreeEntries(); 375 } 376 /** 377 * Set vector mode to Full or Elem. 378 * Ignore 'silent' modifications. 379 * 380 * @param newVecMode new vector renaming mode 381 */ 382 void switchMode(VecMode newVecMode); 383 384 /** 385 * Switch freeList of registers from Full to Elem or vicevers 386 * depending on vecMode (vector renaming mode). 387 */ 388 void switchFreeList(UnifiedFreeList* freeList); 389 390}; 391 392#endif //__CPU_O3_RENAME_MAP_HH__ 393