rename_map.hh revision 12109:f29e9c5418aa
1/* 2 * Copyright (c) 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2004-2005 The Regents of The University of Michigan 15 * Copyright (c) 2013 Advanced Micro Devices, Inc. 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Steve Reinhardt 43 */ 44 45#ifndef __CPU_O3_RENAME_MAP_HH__ 46#define __CPU_O3_RENAME_MAP_HH__ 47 48#include <iostream> 49#include <utility> 50#include <vector> 51 52#include "arch/types.hh" 53#include "config/the_isa.hh" 54#include "cpu/o3/free_list.hh" 55#include "cpu/o3/regfile.hh" 56#include "cpu/reg_class.hh" 57#include "enums/VecRegRenameMode.hh" 58 59/** 60 * Register rename map for a single class of registers (e.g., integer 61 * or floating point). Because the register class is implicitly 62 * determined by the rename map instance being accessed, all 63 * architectural register index parameters and values in this class 64 * are relative (e.g., %fp2 is just index 2). 65 */ 66class SimpleRenameMap 67{ 68 private: 69 using Arch2PhysMap = std::vector<PhysRegIdPtr>; 70 /** The acutal arch-to-phys register map */ 71 Arch2PhysMap map; 72 public: 73 using iterator = Arch2PhysMap::iterator; 74 using const_iterator = Arch2PhysMap::const_iterator; 75 private: 76 77 /** 78 * Pointer to the free list from which new physical registers 79 * should be allocated in rename() 80 */ 81 SimpleFreeList *freeList; 82 83 /** 84 * The architectural index of the zero register. This register is 85 * mapped but read-only, so we ignore attempts to rename it via 86 * the rename() method. If there is no such register for this map 87 * table, it should be set to an invalid index so that it never 88 * matches. 89 */ 90 RegId zeroReg; 91 92 public: 93 94 SimpleRenameMap(); 95 96 ~SimpleRenameMap() {}; 97 98 /** 99 * Because we have an array of rename maps (one per thread) in the CPU, 100 * it's awkward to initialize this object via the constructor. 101 * Instead, this method is used for initialization. 102 */ 103 void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg); 104 105 /** 106 * Pair of a physical register and a physical register. Used to 107 * return the physical register that a logical register has been 108 * renamed to, and the previous physical register that the same 109 * logical register was previously mapped to. 110 */ 111 typedef std::pair<PhysRegIdPtr, PhysRegIdPtr> RenameInfo; 112 113 /** 114 * Tell rename map to get a new free physical register to remap 115 * the specified architectural register. 116 * @param arch_reg The architectural register to remap. 117 * @return A RenameInfo pair indicating both the new and previous 118 * physical registers. 119 */ 120 RenameInfo rename(const RegId& arch_reg); 121 122 /** 123 * Look up the physical register mapped to an architectural register. 124 * @param arch_reg The architectural register to look up. 125 * @return The physical register it is currently mapped to. 126 */ 127 PhysRegIdPtr lookup(const RegId& arch_reg) const 128 { 129 assert(arch_reg.flatIndex() <= map.size()); 130 return map[arch_reg.flatIndex()]; 131 } 132 133 /** 134 * Update rename map with a specific mapping. Generally used to 135 * roll back to old mappings on a squash. 136 * @param arch_reg The architectural register to remap. 137 * @param phys_reg The physical register to remap it to. 138 */ 139 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) 140 { 141 assert(arch_reg.flatIndex() <= map.size()); 142 map[arch_reg.flatIndex()] = phys_reg; 143 } 144 145 /** Return the number of free entries on the associated free list. */ 146 unsigned numFreeEntries() const { return freeList->numFreeRegs(); } 147 148 /** Forward begin/cbegin to the map. */ 149 /** @{ */ 150 iterator begin() { return map.begin(); } 151 const_iterator begin() const { return map.begin(); } 152 const_iterator cbegin() const { return map.cbegin(); } 153 /** @} */ 154 155 /** Forward end/cend to the map. */ 156 /** @{ */ 157 iterator end() { return map.end(); } 158 const_iterator end() const { return map.end(); } 159 const_iterator cend() const { return map.cend(); } 160 /** @} */ 161}; 162 163 164/** 165 * Unified register rename map for all classes of registers. Wraps a 166 * set of class-specific rename maps. Methods that do not specify a 167 * register class (e.g., rename()) take register ids, 168 * while methods that do specify a register class (e.g., renameInt()) 169 * take register indices. 170 */ 171class UnifiedRenameMap 172{ 173 private: 174 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg; 175 using VecReg = TheISA::VecReg; 176 177 /** The integer register rename map */ 178 SimpleRenameMap intMap; 179 180 /** The floating-point register rename map */ 181 SimpleRenameMap floatMap; 182 183 /** The condition-code register rename map */ 184 SimpleRenameMap ccMap; 185 186 /** The vector register rename map */ 187 SimpleRenameMap vecMap; 188 189 /** The vector element register rename map */ 190 SimpleRenameMap vecElemMap; 191 192 using VecMode = Enums::VecRegRenameMode; 193 VecMode vecMode; 194 195 /** 196 * The register file object is used only to get PhysRegIdPtr 197 * on MiscRegs, as they are stored in it. 198 */ 199 PhysRegFile *regFile; 200 201 public: 202 203 typedef SimpleRenameMap::RenameInfo RenameInfo; 204 205 /** Default constructor. init() must be called prior to use. */ 206 UnifiedRenameMap() : regFile(nullptr) {}; 207 208 /** Destructor. */ 209 ~UnifiedRenameMap() {}; 210 211 /** Initializes rename map with given parameters. */ 212 void init(PhysRegFile *_regFile, 213 RegIndex _intZeroReg, 214 RegIndex _floatZeroReg, 215 UnifiedFreeList *freeList, 216 VecMode _mode); 217 218 /** 219 * Tell rename map to get a new free physical register to remap 220 * the specified architectural register. This version takes a 221 * RegId and reads the appropriate class-specific rename table. 222 * @param arch_reg The architectural register id to remap. 223 * @return A RenameInfo pair indicating both the new and previous 224 * physical registers. 225 */ 226 RenameInfo rename(const RegId& arch_reg) 227 { 228 switch (arch_reg.classValue()) { 229 case IntRegClass: 230 return intMap.rename(arch_reg); 231 case FloatRegClass: 232 return floatMap.rename(arch_reg); 233 case VecRegClass: 234 assert(vecMode == Enums::Full); 235 return vecMap.rename(arch_reg); 236 case VecElemClass: 237 assert(vecMode == Enums::Elem); 238 return vecElemMap.rename(arch_reg); 239 case CCRegClass: 240 return ccMap.rename(arch_reg); 241 case MiscRegClass: 242 { 243 // misc regs aren't really renamed, just remapped 244 PhysRegIdPtr phys_reg = lookup(arch_reg); 245 // Set the new register to the previous one to keep the same 246 // mapping throughout the execution. 247 return RenameInfo(phys_reg, phys_reg); 248 } 249 250 default: 251 panic("rename rename(): unknown reg class %s\n", 252 arch_reg.className()); 253 } 254 } 255 256 /** 257 * Look up the physical register mapped to an architectural register. 258 * This version takes a flattened architectural register id 259 * and calls the appropriate class-specific rename table. 260 * @param arch_reg The architectural register to look up. 261 * @return The physical register it is currently mapped to. 262 */ 263 PhysRegIdPtr lookup(const RegId& arch_reg) const 264 { 265 switch (arch_reg.classValue()) { 266 case IntRegClass: 267 return intMap.lookup(arch_reg); 268 269 case FloatRegClass: 270 return floatMap.lookup(arch_reg); 271 272 case VecRegClass: 273 assert(vecMode == Enums::Full); 274 return vecMap.lookup(arch_reg); 275 276 case VecElemClass: 277 assert(vecMode == Enums::Elem); 278 return vecElemMap.lookup(arch_reg); 279 280 case CCRegClass: 281 return ccMap.lookup(arch_reg); 282 283 case MiscRegClass: 284 // misc regs aren't really renamed, they keep the same 285 // mapping throughout the execution. 286 return regFile->getMiscRegId(arch_reg.flatIndex()); 287 288 default: 289 panic("rename lookup(): unknown reg class %s\n", 290 arch_reg.className()); 291 } 292 } 293 294 /** 295 * Update rename map with a specific mapping. Generally used to 296 * roll back to old mappings on a squash. This version takes a 297 * flattened architectural register id and calls the 298 * appropriate class-specific rename table. 299 * @param arch_reg The architectural register to remap. 300 * @param phys_reg The physical register to remap it to. 301 */ 302 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg) 303 { 304 switch (arch_reg.classValue()) { 305 case IntRegClass: 306 assert(phys_reg->isIntPhysReg()); 307 return intMap.setEntry(arch_reg, phys_reg); 308 309 case FloatRegClass: 310 assert(phys_reg->isFloatPhysReg()); 311 return floatMap.setEntry(arch_reg, phys_reg); 312 313 case VecRegClass: 314 assert(phys_reg->isVectorPhysReg()); 315 assert(vecMode == Enums::Full); 316 return vecMap.setEntry(arch_reg, phys_reg); 317 318 case VecElemClass: 319 assert(phys_reg->isVectorPhysElem()); 320 assert(vecMode == Enums::Elem); 321 return vecElemMap.setEntry(arch_reg, phys_reg); 322 323 case CCRegClass: 324 assert(phys_reg->isCCPhysReg()); 325 return ccMap.setEntry(arch_reg, phys_reg); 326 327 case MiscRegClass: 328 // Misc registers do not actually rename, so don't change 329 // their mappings. We end up here when a commit or squash 330 // tries to update or undo a hardwired misc reg nmapping, 331 // which should always be setting it to what it already is. 332 assert(phys_reg == lookup(arch_reg)); 333 return; 334 335 default: 336 panic("rename setEntry(): unknown reg class %s\n", 337 arch_reg.className()); 338 } 339 } 340 341 /** 342 * Return the minimum number of free entries across all of the 343 * register classes. The minimum is used so we guarantee that 344 * this number of entries is available regardless of which class 345 * of registers is requested. 346 */ 347 unsigned numFreeEntries() const 348 { 349 return std::min( 350 std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()), 351 vecMode == Enums::Full ? vecMap.numFreeEntries() 352 : vecElemMap.numFreeEntries()); 353 } 354 355 unsigned numFreeIntEntries() const { return intMap.numFreeEntries(); } 356 unsigned numFreeFloatEntries() const { return floatMap.numFreeEntries(); } 357 unsigned numFreeVecEntries() const 358 { 359 return vecMode == Enums::Full 360 ? vecMap.numFreeEntries() 361 : vecElemMap.numFreeEntries(); 362 } 363 unsigned numFreeCCEntries() const { return ccMap.numFreeEntries(); } 364 365 /** 366 * Return whether there are enough registers to serve the request. 367 */ 368 bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t vectorRegs, 369 uint32_t vecElemRegs, uint32_t ccRegs) const 370 { 371 return intRegs <= intMap.numFreeEntries() && 372 floatRegs <= floatMap.numFreeEntries() && 373 vectorRegs <= vecMap.numFreeEntries() && 374 vecElemRegs <= vecElemMap.numFreeEntries() && 375 ccRegs <= ccMap.numFreeEntries(); 376 } 377 /** 378 * Set vector mode to Full or Elem. 379 * Ignore 'silent' modifications. 380 */ 381 void switchMode(VecMode newVecMode, UnifiedFreeList* freeList); 382 383}; 384 385#endif //__CPU_O3_RENAME_MAP_HH__ 386