rename_map.hh revision 6658
11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
311060SN/A// Todo:  Create destructor.
321061SN/A// Have it so that there's a more meaningful name given to the variable
331060SN/A// that marks the beginning of the FP registers.
341060SN/A
352292SN/A#ifndef __CPU_O3_RENAME_MAP_HH__
362292SN/A#define __CPU_O3_RENAME_MAP_HH__
371060SN/A
381060SN/A#include <iostream>
391461SN/A#include <utility>
401060SN/A#include <vector>
411060SN/A
426658Snate@binkert.org#include "arch/types.hh"
436658Snate@binkert.org#include "config/the_isa.hh"
441717SN/A#include "cpu/o3/free_list.hh"
451060SN/A
461060SN/Aclass SimpleRenameMap
471060SN/A{
482107SN/A  protected:
492107SN/A    typedef TheISA::RegIndex RegIndex;
501060SN/A  public:
511060SN/A    /**
521060SN/A     * Pair of a logical register and a physical register.  Tells the
531060SN/A     * previous mapping of a logical register to a physical register.
541060SN/A     * Used to roll back the rename map to a previous state.
551060SN/A     */
561461SN/A    typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo;
571060SN/A
581060SN/A    /**
591060SN/A     * Pair of a physical register and a physical register.  Used to
601060SN/A     * return the physical register that a logical register has been
611060SN/A     * renamed to, and the previous physical register that the same
621060SN/A     * logical register was previously mapped to.
631060SN/A     */
641461SN/A    typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo;
651060SN/A
661060SN/A  public:
672348SN/A    /** Default constructor.  init() must be called prior to use. */
682348SN/A    SimpleRenameMap() {};
691060SN/A
701061SN/A    /** Destructor. */
711061SN/A    ~SimpleRenameMap();
721061SN/A
732348SN/A    /** Initializes rename map with given parameters. */
742292SN/A    void init(unsigned _numLogicalIntRegs,
752292SN/A              unsigned _numPhysicalIntRegs,
762292SN/A              PhysRegIndex &_int_reg_start,
772292SN/A
782292SN/A              unsigned _numLogicalFloatRegs,
792292SN/A              unsigned _numPhysicalFloatRegs,
802292SN/A              PhysRegIndex &_float_reg_start,
812292SN/A
822292SN/A              unsigned _numMiscRegs,
832292SN/A
842292SN/A              RegIndex _intZeroReg,
852292SN/A              RegIndex _floatZeroReg,
862292SN/A
872292SN/A              int id,
882292SN/A              bool bindRegs);
892292SN/A
902348SN/A    /** Sets the free list used with this rename map. */
911060SN/A    void setFreeList(SimpleFreeList *fl_ptr);
921060SN/A
931060SN/A    //Tell rename map to get a free physical register for a given
941060SN/A    //architected register.  Not sure it should have a return value,
951060SN/A    //but perhaps it should have some sort of fault in case there are
961060SN/A    //no free registers.
971060SN/A    RenameInfo rename(RegIndex arch_reg);
981060SN/A
991060SN/A    PhysRegIndex lookup(RegIndex phys_reg);
1001060SN/A
1011060SN/A    /**
1021060SN/A     * Marks the given register as ready, meaning that its value has been
1031060SN/A     * calculated and written to the register file.
1041763SN/A     * @param ready_reg The index of the physical register that is now ready.
1051060SN/A     */
1061060SN/A    void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg);
1071060SN/A
1081060SN/A    int numFreeEntries();
1091060SN/A
1101060SN/A  private:
1112292SN/A    /** Rename Map ID  */
1122292SN/A    int id;
1132292SN/A
1141060SN/A    /** Number of logical integer registers. */
1151060SN/A    int numLogicalIntRegs;
1161060SN/A
1171060SN/A    /** Number of physical integer registers. */
1181060SN/A    int numPhysicalIntRegs;
1191060SN/A
1201060SN/A    /** Number of logical floating point registers. */
1211060SN/A    int numLogicalFloatRegs;
1221060SN/A
1231060SN/A    /** Number of physical floating point registers. */
1241060SN/A    int numPhysicalFloatRegs;
1251060SN/A
1261060SN/A    /** Number of miscellaneous registers. */
1271060SN/A    int numMiscRegs;
1281060SN/A
1291060SN/A    /** Number of logical integer + float registers. */
1301060SN/A    int numLogicalRegs;
1311060SN/A
1321060SN/A    /** Number of physical integer + float registers. */
1331060SN/A    int numPhysicalRegs;
1341060SN/A
1351060SN/A    /** The integer zero register.  This implementation assumes it is always
1361060SN/A     *  zero and never can be anything else.
1371060SN/A     */
1381060SN/A    RegIndex intZeroReg;
1391060SN/A
1401060SN/A    /** The floating point zero register.  This implementation assumes it is
1411060SN/A     *  always zero and never can be anything else.
1421060SN/A     */
1431060SN/A    RegIndex floatZeroReg;
1441060SN/A
1451060SN/A    class RenameEntry
1461060SN/A    {
1471060SN/A      public:
1481060SN/A        PhysRegIndex physical_reg;
1491060SN/A        bool valid;
1501060SN/A
1511061SN/A        RenameEntry()
1521061SN/A            : physical_reg(0), valid(false)
1531061SN/A        { }
1541060SN/A    };
1551060SN/A
1562329SN/A  private:
1571060SN/A    /** Integer rename map. */
1582292SN/A    std::vector<RenameEntry> intRenameMap;
1591060SN/A
1601060SN/A    /** Floating point rename map. */
1612292SN/A    std::vector<RenameEntry> floatRenameMap;
1621060SN/A
1632292SN/A  private:
1641060SN/A    /** Free list interface. */
1651060SN/A    SimpleFreeList *freeList;
1661060SN/A};
1671060SN/A
1682292SN/A#endif //__CPU_O3_RENAME_MAP_HH__
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