rename_map.hh revision 2107
11761SN/A/* 22SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262665Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282686Sksewell@umich.edu 292SN/A// Todo: Create destructor. 302SN/A// Have it so that there's a more meaningful name given to the variable 312SN/A// that marks the beginning of the FP registers. 322SN/A 332SN/A#ifndef __CPU_O3_CPU_RENAME_MAP_HH__ 34705SN/A#define __CPU_O3_CPU_RENAME_MAP_HH__ 352SN/A 362SN/A#include <iostream> 372SN/A#include <utility> 382SN/A#include <vector> 392SN/A 402SN/A#include "cpu/o3/free_list.hh" 412632Sstever@eecs.umich.edu//For RegIndex 422SN/A#include "arch/isa_traits.hh" 432SN/A 442SN/Aclass SimpleRenameMap 452SN/A{ 462SN/A protected: 472SN/A typedef TheISA::RegIndex RegIndex; 482SN/A public: 492SN/A /** 502SN/A * Pair of a logical register and a physical register. Tells the 512SN/A * previous mapping of a logical register to a physical register. 522SN/A * Used to roll back the rename map to a previous state. 532SN/A */ 542SN/A typedef std::pair<RegIndex, PhysRegIndex> UnmapInfo; 552SN/A 562SN/A /** 572SN/A * Pair of a physical register and a physical register. Used to 582SN/A * return the physical register that a logical register has been 592SN/A * renamed to, and the previous physical register that the same 602SN/A * logical register was previously mapped to. 612SN/A */ 622SN/A typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo; 632SN/A 642SN/A public: 65715SN/A //Constructor 66715SN/A SimpleRenameMap(unsigned _numLogicalIntRegs, 67715SN/A unsigned _numPhysicalIntRegs, 682SN/A unsigned _numLogicalFloatRegs, 692SN/A unsigned _numPhysicalFloatRegs, 702SN/A unsigned _numMiscRegs, 712SN/A RegIndex _intZeroReg, 722SN/A RegIndex _floatZeroReg); 732SN/A 742SN/A /** Destructor. */ 752SN/A ~SimpleRenameMap(); 762SN/A 772SN/A void setFreeList(SimpleFreeList *fl_ptr); 782SN/A 792SN/A //Tell rename map to get a free physical register for a given 802SN/A //architected register. Not sure it should have a return value, 812SN/A //but perhaps it should have some sort of fault in case there are 822SN/A //no free registers. 832SN/A RenameInfo rename(RegIndex arch_reg); 842SN/A 852SN/A PhysRegIndex lookup(RegIndex phys_reg); 862075SN/A 872SN/A bool isReady(PhysRegIndex arch_reg); 882075SN/A 892SN/A /** 902SN/A * Marks the given register as ready, meaning that its value has been 912SN/A * calculated and written to the register file. 922SN/A * @param ready_reg The index of the physical register that is now ready. 932SN/A */ 942023SN/A void markAsReady(PhysRegIndex ready_reg); 952023SN/A 962023SN/A void setEntry(RegIndex arch_reg, PhysRegIndex renamed_reg); 972023SN/A 982023SN/A void squash(std::vector<RegIndex> freed_regs, 992023SN/A std::vector<UnmapInfo> unmaps); 1002023SN/A 1012023SN/A int numFreeEntries(); 1022SN/A 1032SN/A private: 1042SN/A /** Number of logical integer registers. */ 1052SN/A int numLogicalIntRegs; 1062SN/A 1072075SN/A /** Number of physical integer registers. */ 1082075SN/A int numPhysicalIntRegs; 1092SN/A 1102SN/A /** Number of logical floating point registers. */ 1112SN/A int numLogicalFloatRegs; 1122SN/A 1132075SN/A /** Number of physical floating point registers. */ 1142SN/A int numPhysicalFloatRegs; 1152SN/A 1162SN/A /** Number of miscellaneous registers. */ 1172SN/A int numMiscRegs; 1182SN/A 1192SN/A /** Number of logical integer + float registers. */ 1202SN/A int numLogicalRegs; 1212SN/A 1222SN/A /** Number of physical integer + float registers. */ 1232SN/A int numPhysicalRegs; 1242SN/A 1252SN/A /** The integer zero register. This implementation assumes it is always 1262SN/A * zero and never can be anything else. 1272SN/A */ 1282SN/A RegIndex intZeroReg; 1292SN/A 1302SN/A /** The floating point zero register. This implementation assumes it is 1312SN/A * always zero and never can be anything else. 1322SN/A */ 1332SN/A RegIndex floatZeroReg; 1342SN/A 1352SN/A class RenameEntry 1362SN/A { 1372SN/A public: 1382SN/A PhysRegIndex physical_reg; 1392SN/A bool valid; 1402SN/A 1412SN/A RenameEntry() 1422SN/A : physical_reg(0), valid(false) 1432SN/A { } 1442SN/A }; 1452SN/A 1462SN/A /** Integer rename map. */ 1472SN/A RenameEntry *intRenameMap; 1482SN/A 1492SN/A /** Floating point rename map. */ 1502SN/A RenameEntry *floatRenameMap; 1512SN/A 1522SN/A /** Free list interface. */ 1532SN/A SimpleFreeList *freeList; 1542SN/A 1552SN/A // Might want to make all these scoreboards into one large scoreboard. 1562SN/A 1572SN/A /** Scoreboard of physical integer registers, saying whether or not they 1582SN/A * are ready. 1592SN/A */ 1602023SN/A std::vector<bool> intScoreboard; 1612SN/A 1622SN/A /** Scoreboard of physical floating registers, saying whether or not they 1632SN/A * are ready. 1642023SN/A */ 1652065SN/A std::vector<bool> floatScoreboard; 1662504SN/A 1672023SN/A /** Scoreboard of miscellaneous registers, saying whether or not they 1682023SN/A * are ready. 1692023SN/A */ 1702023SN/A std::vector<bool> miscScoreboard; 1712504SN/A}; 1722023SN/A 1732SN/A#endif //__CPU_O3_CPU_RENAME_MAP_HH__ 1742SN/A