rename_map.hh revision 10935
11689SN/A/* 210715SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2015 ARM Limited 310715SRekai.GonzalezAlberquilla@arm.com * All rights reserved. 410715SRekai.GonzalezAlberquilla@arm.com * 510715SRekai.GonzalezAlberquilla@arm.com * The license below extends only to copyright in the software and shall 610715SRekai.GonzalezAlberquilla@arm.com * not be construed as granting a license to any other intellectual 710715SRekai.GonzalezAlberquilla@arm.com * property including but not limited to intellectual property relating 810715SRekai.GonzalezAlberquilla@arm.com * to a hardware implementation of the functionality of the software 910715SRekai.GonzalezAlberquilla@arm.com * licensed hereunder. You may use the software subject to the license 1010715SRekai.GonzalezAlberquilla@arm.com * terms below provided that you ensure that this notice is replicated 1110715SRekai.GonzalezAlberquilla@arm.com * unmodified and in its entirety in all distributions of the software, 1210715SRekai.GonzalezAlberquilla@arm.com * modified or unmodified, in source code or in binary form. 1310715SRekai.GonzalezAlberquilla@arm.com * 141689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 159919Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 429919Ssteve.reinhardt@amd.com * Steve Reinhardt 431689SN/A */ 441689SN/A 451060SN/A// Todo: Create destructor. 461061SN/A// Have it so that there's a more meaningful name given to the variable 471060SN/A// that marks the beginning of the FP registers. 481060SN/A 492292SN/A#ifndef __CPU_O3_RENAME_MAP_HH__ 502292SN/A#define __CPU_O3_RENAME_MAP_HH__ 511060SN/A 521060SN/A#include <iostream> 531461SN/A#include <utility> 541060SN/A#include <vector> 551060SN/A 566658Snate@binkert.org#include "arch/types.hh" 576658Snate@binkert.org#include "config/the_isa.hh" 581717SN/A#include "cpu/o3/free_list.hh" 599919Ssteve.reinhardt@amd.com#include "cpu/o3/regfile.hh" 609919Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 611060SN/A 629919Ssteve.reinhardt@amd.com/** 639919Ssteve.reinhardt@amd.com * Register rename map for a single class of registers (e.g., integer 649919Ssteve.reinhardt@amd.com * or floating point). Because the register class is implicitly 659919Ssteve.reinhardt@amd.com * determined by the rename map instance being accessed, all 669919Ssteve.reinhardt@amd.com * architectural register index parameters and values in this class 679919Ssteve.reinhardt@amd.com * are relative (e.g., %fp2 is just index 2). 689919Ssteve.reinhardt@amd.com */ 691060SN/Aclass SimpleRenameMap 701060SN/A{ 719919Ssteve.reinhardt@amd.com public: 729919Ssteve.reinhardt@amd.com 732107SN/A typedef TheISA::RegIndex RegIndex; 749919Ssteve.reinhardt@amd.com 759919Ssteve.reinhardt@amd.com private: 769919Ssteve.reinhardt@amd.com 779919Ssteve.reinhardt@amd.com /** The acutal arch-to-phys register map */ 789919Ssteve.reinhardt@amd.com std::vector<PhysRegIndex> map; 799919Ssteve.reinhardt@amd.com 809919Ssteve.reinhardt@amd.com /** 819919Ssteve.reinhardt@amd.com * Pointer to the free list from which new physical registers 829919Ssteve.reinhardt@amd.com * should be allocated in rename() 839919Ssteve.reinhardt@amd.com */ 849919Ssteve.reinhardt@amd.com SimpleFreeList *freeList; 859919Ssteve.reinhardt@amd.com 869919Ssteve.reinhardt@amd.com /** 879919Ssteve.reinhardt@amd.com * The architectural index of the zero register. This register is 889919Ssteve.reinhardt@amd.com * mapped but read-only, so we ignore attempts to rename it via 899919Ssteve.reinhardt@amd.com * the rename() method. If there is no such register for this map 909919Ssteve.reinhardt@amd.com * table, it should be set to an invalid index so that it never 919919Ssteve.reinhardt@amd.com * matches. 929919Ssteve.reinhardt@amd.com */ 939919Ssteve.reinhardt@amd.com RegIndex zeroReg; 949919Ssteve.reinhardt@amd.com 951060SN/A public: 969919Ssteve.reinhardt@amd.com 979919Ssteve.reinhardt@amd.com SimpleRenameMap(); 989919Ssteve.reinhardt@amd.com 999919Ssteve.reinhardt@amd.com ~SimpleRenameMap() {}; 1009919Ssteve.reinhardt@amd.com 1011060SN/A /** 1029919Ssteve.reinhardt@amd.com * Because we have an array of rename maps (one per thread) in the CPU, 1039919Ssteve.reinhardt@amd.com * it's awkward to initialize this object via the constructor. 1049919Ssteve.reinhardt@amd.com * Instead, this method is used for initialization. 1051060SN/A */ 1069919Ssteve.reinhardt@amd.com void init(unsigned size, SimpleFreeList *_freeList, RegIndex _zeroReg); 1071060SN/A 1081060SN/A /** 1091060SN/A * Pair of a physical register and a physical register. Used to 1101060SN/A * return the physical register that a logical register has been 1111060SN/A * renamed to, and the previous physical register that the same 1121060SN/A * logical register was previously mapped to. 1131060SN/A */ 1141461SN/A typedef std::pair<PhysRegIndex, PhysRegIndex> RenameInfo; 1151060SN/A 1169919Ssteve.reinhardt@amd.com /** 1179919Ssteve.reinhardt@amd.com * Tell rename map to get a new free physical register to remap 1189919Ssteve.reinhardt@amd.com * the specified architectural register. 1199919Ssteve.reinhardt@amd.com * @param arch_reg The architectural register to remap. 1209919Ssteve.reinhardt@amd.com * @return A RenameInfo pair indicating both the new and previous 1219919Ssteve.reinhardt@amd.com * physical registers. 1229919Ssteve.reinhardt@amd.com */ 1239919Ssteve.reinhardt@amd.com RenameInfo rename(RegIndex arch_reg); 1249919Ssteve.reinhardt@amd.com 1259919Ssteve.reinhardt@amd.com /** 1269919Ssteve.reinhardt@amd.com * Look up the physical register mapped to an architectural register. 1279919Ssteve.reinhardt@amd.com * @param arch_reg The architectural register to look up. 1289919Ssteve.reinhardt@amd.com * @return The physical register it is currently mapped to. 1299919Ssteve.reinhardt@amd.com */ 1309919Ssteve.reinhardt@amd.com PhysRegIndex lookup(RegIndex arch_reg) const 1319919Ssteve.reinhardt@amd.com { 1329919Ssteve.reinhardt@amd.com assert(arch_reg < map.size()); 1339919Ssteve.reinhardt@amd.com return map[arch_reg]; 1349919Ssteve.reinhardt@amd.com } 1359919Ssteve.reinhardt@amd.com 1369919Ssteve.reinhardt@amd.com /** 1379919Ssteve.reinhardt@amd.com * Update rename map with a specific mapping. Generally used to 1389919Ssteve.reinhardt@amd.com * roll back to old mappings on a squash. 1399919Ssteve.reinhardt@amd.com * @param arch_reg The architectural register to remap. 1409919Ssteve.reinhardt@amd.com * @param phys_reg The physical register to remap it to. 1419919Ssteve.reinhardt@amd.com */ 1429919Ssteve.reinhardt@amd.com void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 1439919Ssteve.reinhardt@amd.com { 1449919Ssteve.reinhardt@amd.com map[arch_reg] = phys_reg; 1459919Ssteve.reinhardt@amd.com } 1469919Ssteve.reinhardt@amd.com 1479919Ssteve.reinhardt@amd.com /** Return the number of free entries on the associated free list. */ 1489919Ssteve.reinhardt@amd.com unsigned numFreeEntries() const { return freeList->numFreeRegs(); } 1499919Ssteve.reinhardt@amd.com}; 1509919Ssteve.reinhardt@amd.com 1519919Ssteve.reinhardt@amd.com 1529919Ssteve.reinhardt@amd.com/** 1539919Ssteve.reinhardt@amd.com * Unified register rename map for all classes of registers. Wraps a 1549919Ssteve.reinhardt@amd.com * set of class-specific rename maps. Methods that do not specify a 1559919Ssteve.reinhardt@amd.com * register class (e.g., rename()) take unified register indices, 1569919Ssteve.reinhardt@amd.com * while methods that do specify a register class (e.g., renameInt()) 1579919Ssteve.reinhardt@amd.com * take relative register indices. See http://gem5.org/Register_Indexing. 1589919Ssteve.reinhardt@amd.com */ 1599919Ssteve.reinhardt@amd.comclass UnifiedRenameMap 1609919Ssteve.reinhardt@amd.com{ 1619919Ssteve.reinhardt@amd.com private: 1629919Ssteve.reinhardt@amd.com 1639919Ssteve.reinhardt@amd.com /** The integer register rename map */ 1649919Ssteve.reinhardt@amd.com SimpleRenameMap intMap; 1659919Ssteve.reinhardt@amd.com 1669919Ssteve.reinhardt@amd.com /** The floating-point register rename map */ 1679919Ssteve.reinhardt@amd.com SimpleRenameMap floatMap; 1689919Ssteve.reinhardt@amd.com 1699919Ssteve.reinhardt@amd.com /** 1709919Ssteve.reinhardt@amd.com * The register file object is used only to distinguish integer 1719919Ssteve.reinhardt@amd.com * from floating-point physical register indices, which in turn is 1729919Ssteve.reinhardt@amd.com * used only for assert statements that make sure the physical 1739919Ssteve.reinhardt@amd.com * register indices that get passed in and handed out are of the 1749919Ssteve.reinhardt@amd.com * proper class. 1759919Ssteve.reinhardt@amd.com */ 1769919Ssteve.reinhardt@amd.com PhysRegFile *regFile; 1779919Ssteve.reinhardt@amd.com 1789920Syasuko.eckert@amd.com /** The condition-code register rename map */ 1799920Syasuko.eckert@amd.com SimpleRenameMap ccMap; 1809920Syasuko.eckert@amd.com 1811060SN/A public: 1829919Ssteve.reinhardt@amd.com typedef TheISA::RegIndex RegIndex; 1839919Ssteve.reinhardt@amd.com 1849919Ssteve.reinhardt@amd.com typedef SimpleRenameMap::RenameInfo RenameInfo; 1859919Ssteve.reinhardt@amd.com 1862348SN/A /** Default constructor. init() must be called prior to use. */ 18710537Sandreas.hansson@arm.com UnifiedRenameMap() : regFile(nullptr) {}; 1881060SN/A 1891061SN/A /** Destructor. */ 1909919Ssteve.reinhardt@amd.com ~UnifiedRenameMap() {}; 1911061SN/A 1922348SN/A /** Initializes rename map with given parameters. */ 1939919Ssteve.reinhardt@amd.com void init(PhysRegFile *_regFile, 1942292SN/A RegIndex _intZeroReg, 1952292SN/A RegIndex _floatZeroReg, 1969919Ssteve.reinhardt@amd.com UnifiedFreeList *freeList); 1972292SN/A 1989919Ssteve.reinhardt@amd.com /** 1999919Ssteve.reinhardt@amd.com * Tell rename map to get a new free physical register to remap 2009919Ssteve.reinhardt@amd.com * the specified architectural register. This version takes a 2019919Ssteve.reinhardt@amd.com * unified flattened architectural register index and calls the 2029919Ssteve.reinhardt@amd.com * appropriate class-specific rename table. 2039919Ssteve.reinhardt@amd.com * @param arch_reg The unified architectural register index to remap. 2049919Ssteve.reinhardt@amd.com * @return A RenameInfo pair indicating both the new and previous 2059919Ssteve.reinhardt@amd.com * physical registers. 2069919Ssteve.reinhardt@amd.com */ 2071060SN/A RenameInfo rename(RegIndex arch_reg); 2081060SN/A 2099919Ssteve.reinhardt@amd.com /** 2109919Ssteve.reinhardt@amd.com * Perform rename() on an integer register, given a relative 2119919Ssteve.reinhardt@amd.com * integer register index. 2129919Ssteve.reinhardt@amd.com */ 2139919Ssteve.reinhardt@amd.com RenameInfo renameInt(RegIndex rel_arch_reg) 2149919Ssteve.reinhardt@amd.com { 2159919Ssteve.reinhardt@amd.com RenameInfo info = intMap.rename(rel_arch_reg); 2169919Ssteve.reinhardt@amd.com assert(regFile->isIntPhysReg(info.first)); 2179919Ssteve.reinhardt@amd.com return info; 2189919Ssteve.reinhardt@amd.com } 2191060SN/A 2201060SN/A /** 2219919Ssteve.reinhardt@amd.com * Perform rename() on a floating-point register, given a relative 2229919Ssteve.reinhardt@amd.com * floating-point register index. 2231060SN/A */ 2249919Ssteve.reinhardt@amd.com RenameInfo renameFloat(RegIndex rel_arch_reg) 2259919Ssteve.reinhardt@amd.com { 2269919Ssteve.reinhardt@amd.com RenameInfo info = floatMap.rename(rel_arch_reg); 2279919Ssteve.reinhardt@amd.com assert(regFile->isFloatPhysReg(info.first)); 2289919Ssteve.reinhardt@amd.com return info; 2299919Ssteve.reinhardt@amd.com } 2301060SN/A 2319919Ssteve.reinhardt@amd.com /** 2329920Syasuko.eckert@amd.com * Perform rename() on a condition-code register, given a relative 2339920Syasuko.eckert@amd.com * condition-code register index. 2349920Syasuko.eckert@amd.com */ 2359920Syasuko.eckert@amd.com RenameInfo renameCC(RegIndex rel_arch_reg) 2369920Syasuko.eckert@amd.com { 2379920Syasuko.eckert@amd.com RenameInfo info = ccMap.rename(rel_arch_reg); 2389920Syasuko.eckert@amd.com assert(regFile->isCCPhysReg(info.first)); 2399920Syasuko.eckert@amd.com return info; 2409920Syasuko.eckert@amd.com } 2419920Syasuko.eckert@amd.com 2429920Syasuko.eckert@amd.com /** 2439919Ssteve.reinhardt@amd.com * Perform rename() on a misc register, given a relative 2449919Ssteve.reinhardt@amd.com * misc register index. 2459919Ssteve.reinhardt@amd.com */ 2469919Ssteve.reinhardt@amd.com RenameInfo renameMisc(RegIndex rel_arch_reg) 2479919Ssteve.reinhardt@amd.com { 2489919Ssteve.reinhardt@amd.com // misc regs aren't really renamed, just remapped 2499919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = lookupMisc(rel_arch_reg); 2509919Ssteve.reinhardt@amd.com // Set the previous register to the same register; mainly it must be 2519919Ssteve.reinhardt@amd.com // known that the prev reg was outside the range of normal registers 2529919Ssteve.reinhardt@amd.com // so the free list can avoid adding it. 2539919Ssteve.reinhardt@amd.com return RenameInfo(phys_reg, phys_reg); 2549919Ssteve.reinhardt@amd.com } 2551060SN/A 2562292SN/A 2579919Ssteve.reinhardt@amd.com /** 2589919Ssteve.reinhardt@amd.com * Look up the physical register mapped to an architectural register. 2599919Ssteve.reinhardt@amd.com * This version takes a unified flattened architectural register index 2609919Ssteve.reinhardt@amd.com * and calls the appropriate class-specific rename table. 2619919Ssteve.reinhardt@amd.com * @param arch_reg The unified architectural register to look up. 2629919Ssteve.reinhardt@amd.com * @return The physical register it is currently mapped to. 2639919Ssteve.reinhardt@amd.com */ 2649919Ssteve.reinhardt@amd.com PhysRegIndex lookup(RegIndex arch_reg) const; 2651060SN/A 2669919Ssteve.reinhardt@amd.com /** 2679919Ssteve.reinhardt@amd.com * Perform lookup() on an integer register, given a relative 2689919Ssteve.reinhardt@amd.com * integer register index. 2699919Ssteve.reinhardt@amd.com */ 2709919Ssteve.reinhardt@amd.com PhysRegIndex lookupInt(RegIndex rel_arch_reg) const 2719919Ssteve.reinhardt@amd.com { 2729919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = intMap.lookup(rel_arch_reg); 2739919Ssteve.reinhardt@amd.com assert(regFile->isIntPhysReg(phys_reg)); 2749919Ssteve.reinhardt@amd.com return phys_reg; 2759919Ssteve.reinhardt@amd.com } 2761060SN/A 2779919Ssteve.reinhardt@amd.com /** 2789919Ssteve.reinhardt@amd.com * Perform lookup() on a floating-point register, given a relative 2799919Ssteve.reinhardt@amd.com * floating-point register index. 2809919Ssteve.reinhardt@amd.com */ 2819919Ssteve.reinhardt@amd.com PhysRegIndex lookupFloat(RegIndex rel_arch_reg) const 2829919Ssteve.reinhardt@amd.com { 2839919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = floatMap.lookup(rel_arch_reg); 2849919Ssteve.reinhardt@amd.com assert(regFile->isFloatPhysReg(phys_reg)); 2859919Ssteve.reinhardt@amd.com return phys_reg; 2869919Ssteve.reinhardt@amd.com } 2871060SN/A 2889919Ssteve.reinhardt@amd.com /** 2899920Syasuko.eckert@amd.com * Perform lookup() on a condition-code register, given a relative 2909920Syasuko.eckert@amd.com * condition-code register index. 2919920Syasuko.eckert@amd.com */ 2929920Syasuko.eckert@amd.com PhysRegIndex lookupCC(RegIndex rel_arch_reg) const 2939920Syasuko.eckert@amd.com { 2949920Syasuko.eckert@amd.com PhysRegIndex phys_reg = ccMap.lookup(rel_arch_reg); 2959920Syasuko.eckert@amd.com assert(regFile->isCCPhysReg(phys_reg)); 2969920Syasuko.eckert@amd.com return phys_reg; 2979920Syasuko.eckert@amd.com } 2989920Syasuko.eckert@amd.com 2999920Syasuko.eckert@amd.com /** 3009919Ssteve.reinhardt@amd.com * Perform lookup() on a misc register, given a relative 3019919Ssteve.reinhardt@amd.com * misc register index. 3029919Ssteve.reinhardt@amd.com */ 3039919Ssteve.reinhardt@amd.com PhysRegIndex lookupMisc(RegIndex rel_arch_reg) const 3049919Ssteve.reinhardt@amd.com { 3059919Ssteve.reinhardt@amd.com // misc regs aren't really renamed, just given an index 3069919Ssteve.reinhardt@amd.com // beyond the range of actual physical registers 3079919Ssteve.reinhardt@amd.com PhysRegIndex phys_reg = rel_arch_reg + regFile->totalNumPhysRegs(); 3089919Ssteve.reinhardt@amd.com return phys_reg; 3099919Ssteve.reinhardt@amd.com } 3101060SN/A 3119919Ssteve.reinhardt@amd.com /** 3129919Ssteve.reinhardt@amd.com * Update rename map with a specific mapping. Generally used to 3139919Ssteve.reinhardt@amd.com * roll back to old mappings on a squash. This version takes a 3149919Ssteve.reinhardt@amd.com * unified flattened architectural register index and calls the 3159919Ssteve.reinhardt@amd.com * appropriate class-specific rename table. 3169919Ssteve.reinhardt@amd.com * @param arch_reg The unified architectural register to remap. 3179919Ssteve.reinhardt@amd.com * @param phys_reg The physical register to remap it to. 3189919Ssteve.reinhardt@amd.com */ 3199919Ssteve.reinhardt@amd.com void setEntry(RegIndex arch_reg, PhysRegIndex phys_reg); 3201060SN/A 3219919Ssteve.reinhardt@amd.com /** 3229919Ssteve.reinhardt@amd.com * Perform setEntry() on an integer register, given a relative 3239919Ssteve.reinhardt@amd.com * integer register index. 3249919Ssteve.reinhardt@amd.com */ 3259919Ssteve.reinhardt@amd.com void setIntEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 3269919Ssteve.reinhardt@amd.com { 3279919Ssteve.reinhardt@amd.com assert(regFile->isIntPhysReg(phys_reg)); 3289919Ssteve.reinhardt@amd.com intMap.setEntry(arch_reg, phys_reg); 3299919Ssteve.reinhardt@amd.com } 3301060SN/A 3319919Ssteve.reinhardt@amd.com /** 3329919Ssteve.reinhardt@amd.com * Perform setEntry() on a floating-point register, given a relative 3339919Ssteve.reinhardt@amd.com * floating-point register index. 3349919Ssteve.reinhardt@amd.com */ 3359919Ssteve.reinhardt@amd.com void setFloatEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 3369919Ssteve.reinhardt@amd.com { 3379919Ssteve.reinhardt@amd.com assert(regFile->isFloatPhysReg(phys_reg)); 3389919Ssteve.reinhardt@amd.com floatMap.setEntry(arch_reg, phys_reg); 3399919Ssteve.reinhardt@amd.com } 3401060SN/A 3419919Ssteve.reinhardt@amd.com /** 3429920Syasuko.eckert@amd.com * Perform setEntry() on a condition-code register, given a relative 3439920Syasuko.eckert@amd.com * condition-code register index. 3449920Syasuko.eckert@amd.com */ 3459920Syasuko.eckert@amd.com void setCCEntry(RegIndex arch_reg, PhysRegIndex phys_reg) 3469920Syasuko.eckert@amd.com { 3479920Syasuko.eckert@amd.com assert(regFile->isCCPhysReg(phys_reg)); 3489920Syasuko.eckert@amd.com ccMap.setEntry(arch_reg, phys_reg); 3499920Syasuko.eckert@amd.com } 3509920Syasuko.eckert@amd.com 3519920Syasuko.eckert@amd.com /** 3529919Ssteve.reinhardt@amd.com * Return the minimum number of free entries across all of the 3539919Ssteve.reinhardt@amd.com * register classes. The minimum is used so we guarantee that 3549919Ssteve.reinhardt@amd.com * this number of entries is available regardless of which class 3559919Ssteve.reinhardt@amd.com * of registers is requested. 3561060SN/A */ 3579919Ssteve.reinhardt@amd.com unsigned numFreeEntries() const 3581060SN/A { 3599919Ssteve.reinhardt@amd.com return std::min(intMap.numFreeEntries(), floatMap.numFreeEntries()); 3609919Ssteve.reinhardt@amd.com } 36110715SRekai.GonzalezAlberquilla@arm.com 36210715SRekai.GonzalezAlberquilla@arm.com /** 36310715SRekai.GonzalezAlberquilla@arm.com * Return whether there are enough registers to serve the request. 36410715SRekai.GonzalezAlberquilla@arm.com */ 36510935Snilay@cs.wisc.edu bool canRename(uint32_t intRegs, uint32_t floatRegs, uint32_t ccRegs) const 36610715SRekai.GonzalezAlberquilla@arm.com { 36710715SRekai.GonzalezAlberquilla@arm.com return intRegs <= intMap.numFreeEntries() && 36810715SRekai.GonzalezAlberquilla@arm.com floatRegs <= floatMap.numFreeEntries() && 36910935Snilay@cs.wisc.edu ccRegs <= ccMap.numFreeEntries(); 37010715SRekai.GonzalezAlberquilla@arm.com } 37110715SRekai.GonzalezAlberquilla@arm.com 3721060SN/A}; 3731060SN/A 3742292SN/A#endif //__CPU_O3_RENAME_MAP_HH__ 375