rename_impl.hh revision 7720:65d338a8dba4 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include <list>
33
34#include "arch/isa_traits.hh"
35#include "arch/registers.hh"
36#include "config/full_system.hh"
37#include "config/the_isa.hh"
38#include "cpu/o3/rename.hh"
39#include "params/DerivO3CPU.hh"
40
41using namespace std;
42
43template <class Impl>
44DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
45    : cpu(_cpu),
46      iewToRenameDelay(params->iewToRenameDelay),
47      decodeToRenameDelay(params->decodeToRenameDelay),
48      commitToRenameDelay(params->commitToRenameDelay),
49      renameWidth(params->renameWidth),
50      commitWidth(params->commitWidth),
51      resumeSerialize(false),
52      resumeUnblocking(false),
53      numThreads(params->numThreads),
54      maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
55{
56    _status = Inactive;
57
58    for (ThreadID tid = 0; tid < numThreads; tid++) {
59        renameStatus[tid] = Idle;
60
61        freeEntries[tid].iqEntries = 0;
62        freeEntries[tid].lsqEntries = 0;
63        freeEntries[tid].robEntries = 0;
64
65        stalls[tid].iew = false;
66        stalls[tid].commit = false;
67        serializeInst[tid] = NULL;
68
69        instsInProgress[tid] = 0;
70
71        emptyROB[tid] = true;
72
73        serializeOnNextInst[tid] = false;
74    }
75
76    // @todo: Make into a parameter.
77    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
78}
79
80template <class Impl>
81std::string
82DefaultRename<Impl>::name() const
83{
84    return cpu->name() + ".rename";
85}
86
87template <class Impl>
88void
89DefaultRename<Impl>::regStats()
90{
91    renameSquashCycles
92        .name(name() + ".RENAME:SquashCycles")
93        .desc("Number of cycles rename is squashing")
94        .prereq(renameSquashCycles);
95    renameIdleCycles
96        .name(name() + ".RENAME:IdleCycles")
97        .desc("Number of cycles rename is idle")
98        .prereq(renameIdleCycles);
99    renameBlockCycles
100        .name(name() + ".RENAME:BlockCycles")
101        .desc("Number of cycles rename is blocking")
102        .prereq(renameBlockCycles);
103    renameSerializeStallCycles
104        .name(name() + ".RENAME:serializeStallCycles")
105        .desc("count of cycles rename stalled for serializing inst")
106        .flags(Stats::total);
107    renameRunCycles
108        .name(name() + ".RENAME:RunCycles")
109        .desc("Number of cycles rename is running")
110        .prereq(renameIdleCycles);
111    renameUnblockCycles
112        .name(name() + ".RENAME:UnblockCycles")
113        .desc("Number of cycles rename is unblocking")
114        .prereq(renameUnblockCycles);
115    renameRenamedInsts
116        .name(name() + ".RENAME:RenamedInsts")
117        .desc("Number of instructions processed by rename")
118        .prereq(renameRenamedInsts);
119    renameSquashedInsts
120        .name(name() + ".RENAME:SquashedInsts")
121        .desc("Number of squashed instructions processed by rename")
122        .prereq(renameSquashedInsts);
123    renameROBFullEvents
124        .name(name() + ".RENAME:ROBFullEvents")
125        .desc("Number of times rename has blocked due to ROB full")
126        .prereq(renameROBFullEvents);
127    renameIQFullEvents
128        .name(name() + ".RENAME:IQFullEvents")
129        .desc("Number of times rename has blocked due to IQ full")
130        .prereq(renameIQFullEvents);
131    renameLSQFullEvents
132        .name(name() + ".RENAME:LSQFullEvents")
133        .desc("Number of times rename has blocked due to LSQ full")
134        .prereq(renameLSQFullEvents);
135    renameFullRegistersEvents
136        .name(name() + ".RENAME:FullRegisterEvents")
137        .desc("Number of times there has been no free registers")
138        .prereq(renameFullRegistersEvents);
139    renameRenamedOperands
140        .name(name() + ".RENAME:RenamedOperands")
141        .desc("Number of destination operands rename has renamed")
142        .prereq(renameRenamedOperands);
143    renameRenameLookups
144        .name(name() + ".RENAME:RenameLookups")
145        .desc("Number of register rename lookups that rename has made")
146        .prereq(renameRenameLookups);
147    renameCommittedMaps
148        .name(name() + ".RENAME:CommittedMaps")
149        .desc("Number of HB maps that are committed")
150        .prereq(renameCommittedMaps);
151    renameUndoneMaps
152        .name(name() + ".RENAME:UndoneMaps")
153        .desc("Number of HB maps that are undone due to squashing")
154        .prereq(renameUndoneMaps);
155    renamedSerializing
156        .name(name() + ".RENAME:serializingInsts")
157        .desc("count of serializing insts renamed")
158        .flags(Stats::total)
159        ;
160    renamedTempSerializing
161        .name(name() + ".RENAME:tempSerializingInsts")
162        .desc("count of temporary serializing insts renamed")
163        .flags(Stats::total)
164        ;
165    renameSkidInsts
166        .name(name() + ".RENAME:skidInsts")
167        .desc("count of insts added to the skid buffer")
168        .flags(Stats::total)
169        ;
170}
171
172template <class Impl>
173void
174DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
175{
176    timeBuffer = tb_ptr;
177
178    // Setup wire to read information from time buffer, from IEW stage.
179    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181    // Setup wire to read infromation from time buffer, from commit stage.
182    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184    // Setup wire to write information to previous stages.
185    toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192    renameQueue = rq_ptr;
193
194    // Setup wire to write information to future stages.
195    toIEW = renameQueue->getWire(0);
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
201{
202    decodeQueue = dq_ptr;
203
204    // Setup wire to get information from decode.
205    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
210DefaultRename<Impl>::initStage()
211{
212    // Grab the number of free entries directly from the stages.
213    for (ThreadID tid = 0; tid < numThreads; tid++) {
214        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
215        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
216        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
217        emptyROB[tid] = true;
218    }
219}
220
221template<class Impl>
222void
223DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
224{
225    activeThreads = at_ptr;
226}
227
228
229template <class Impl>
230void
231DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
232{
233    for (ThreadID tid = 0; tid < numThreads; tid++)
234        renameMap[tid] = &rm_ptr[tid];
235}
236
237template <class Impl>
238void
239DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
240{
241    freeList = fl_ptr;
242}
243
244template<class Impl>
245void
246DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
247{
248    scoreboard = _scoreboard;
249}
250
251template <class Impl>
252bool
253DefaultRename<Impl>::drain()
254{
255    // Rename is ready to switch out at any time.
256    cpu->signalDrained();
257    return true;
258}
259
260template <class Impl>
261void
262DefaultRename<Impl>::switchOut()
263{
264    // Clear any state, fix up the rename map.
265    for (ThreadID tid = 0; tid < numThreads; tid++) {
266        typename std::list<RenameHistory>::iterator hb_it =
267            historyBuffer[tid].begin();
268
269        while (!historyBuffer[tid].empty()) {
270            assert(hb_it != historyBuffer[tid].end());
271
272            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
273                    "number %i.\n", tid, (*hb_it).instSeqNum);
274
275            // Tell the rename map to set the architected register to the
276            // previous physical register that it was renamed to.
277            renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
278
279            // Put the renamed physical register back on the free list.
280            freeList->addReg(hb_it->newPhysReg);
281
282            // Be sure to mark its register as ready if it's a misc register.
283            if (hb_it->newPhysReg >= maxPhysicalRegs) {
284                scoreboard->setReg(hb_it->newPhysReg);
285            }
286
287            historyBuffer[tid].erase(hb_it++);
288        }
289        insts[tid].clear();
290        skidBuffer[tid].clear();
291    }
292}
293
294template <class Impl>
295void
296DefaultRename<Impl>::takeOverFrom()
297{
298    _status = Inactive;
299    initStage();
300
301    // Reset all state prior to taking over from the other CPU.
302    for (ThreadID tid = 0; tid < numThreads; tid++) {
303        renameStatus[tid] = Idle;
304
305        stalls[tid].iew = false;
306        stalls[tid].commit = false;
307        serializeInst[tid] = NULL;
308
309        instsInProgress[tid] = 0;
310
311        emptyROB[tid] = true;
312
313        serializeOnNextInst[tid] = false;
314    }
315}
316
317template <class Impl>
318void
319DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
320{
321    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
322
323    // Clear the stall signal if rename was blocked or unblocking before.
324    // If it still needs to block, the blocking should happen the next
325    // cycle and there should be space to hold everything due to the squash.
326    if (renameStatus[tid] == Blocked ||
327        renameStatus[tid] == Unblocking) {
328        toDecode->renameUnblock[tid] = 1;
329
330        resumeSerialize = false;
331        serializeInst[tid] = NULL;
332    } else if (renameStatus[tid] == SerializeStall) {
333        if (serializeInst[tid]->seqNum <= squash_seq_num) {
334            DPRINTF(Rename, "Rename will resume serializing after squash\n");
335            resumeSerialize = true;
336            assert(serializeInst[tid]);
337        } else {
338            resumeSerialize = false;
339            toDecode->renameUnblock[tid] = 1;
340
341            serializeInst[tid] = NULL;
342        }
343    }
344
345    // Set the status to Squashing.
346    renameStatus[tid] = Squashing;
347
348    // Squash any instructions from decode.
349    unsigned squashCount = 0;
350
351    for (int i=0; i<fromDecode->size; i++) {
352        if (fromDecode->insts[i]->threadNumber == tid &&
353            fromDecode->insts[i]->seqNum > squash_seq_num) {
354            fromDecode->insts[i]->setSquashed();
355            wroteToTimeBuffer = true;
356            squashCount++;
357        }
358
359    }
360
361    // Clear the instruction list and skid buffer in case they have any
362    // insts in them.
363    insts[tid].clear();
364
365    // Clear the skid buffer in case it has any data in it.
366    skidBuffer[tid].clear();
367
368    doSquash(squash_seq_num, tid);
369}
370
371template <class Impl>
372void
373DefaultRename<Impl>::tick()
374{
375    wroteToTimeBuffer = false;
376
377    blockThisCycle = false;
378
379    bool status_change = false;
380
381    toIEWIndex = 0;
382
383    sortInsts();
384
385    list<ThreadID>::iterator threads = activeThreads->begin();
386    list<ThreadID>::iterator end = activeThreads->end();
387
388    // Check stall and squash signals.
389    while (threads != end) {
390        ThreadID tid = *threads++;
391
392        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
393
394        status_change = checkSignalsAndUpdate(tid) || status_change;
395
396        rename(status_change, tid);
397    }
398
399    if (status_change) {
400        updateStatus();
401    }
402
403    if (wroteToTimeBuffer) {
404        DPRINTF(Activity, "Activity this cycle.\n");
405        cpu->activityThisCycle();
406    }
407
408    threads = activeThreads->begin();
409
410    while (threads != end) {
411        ThreadID tid = *threads++;
412
413        // If we committed this cycle then doneSeqNum will be > 0
414        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
415            !fromCommit->commitInfo[tid].squash &&
416            renameStatus[tid] != Squashing) {
417
418            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
419                                  tid);
420        }
421    }
422
423    // @todo: make into updateProgress function
424    for (ThreadID tid = 0; tid < numThreads; tid++) {
425        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
426
427        assert(instsInProgress[tid] >=0);
428    }
429
430}
431
432template<class Impl>
433void
434DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
435{
436    // If status is Running or idle,
437    //     call renameInsts()
438    // If status is Unblocking,
439    //     buffer any instructions coming from decode
440    //     continue trying to empty skid buffer
441    //     check if stall conditions have passed
442
443    if (renameStatus[tid] == Blocked) {
444        ++renameBlockCycles;
445    } else if (renameStatus[tid] == Squashing) {
446        ++renameSquashCycles;
447    } else if (renameStatus[tid] == SerializeStall) {
448        ++renameSerializeStallCycles;
449        // If we are currently in SerializeStall and resumeSerialize
450        // was set, then that means that we are resuming serializing
451        // this cycle.  Tell the previous stages to block.
452        if (resumeSerialize) {
453            resumeSerialize = false;
454            block(tid);
455            toDecode->renameUnblock[tid] = false;
456        }
457    } else if (renameStatus[tid] == Unblocking) {
458        if (resumeUnblocking) {
459            block(tid);
460            resumeUnblocking = false;
461            toDecode->renameUnblock[tid] = false;
462        }
463    }
464
465    if (renameStatus[tid] == Running ||
466        renameStatus[tid] == Idle) {
467        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
468                "stage.\n", tid);
469
470        renameInsts(tid);
471    } else if (renameStatus[tid] == Unblocking) {
472        renameInsts(tid);
473
474        if (validInsts()) {
475            // Add the current inputs to the skid buffer so they can be
476            // reprocessed when this stage unblocks.
477            skidInsert(tid);
478        }
479
480        // If we switched over to blocking, then there's a potential for
481        // an overall status change.
482        status_change = unblock(tid) || status_change || blockThisCycle;
483    }
484}
485
486template <class Impl>
487void
488DefaultRename<Impl>::renameInsts(ThreadID tid)
489{
490    // Instructions can be either in the skid buffer or the queue of
491    // instructions coming from decode, depending on the status.
492    int insts_available = renameStatus[tid] == Unblocking ?
493        skidBuffer[tid].size() : insts[tid].size();
494
495    // Check the decode queue to see if instructions are available.
496    // If there are no available instructions to rename, then do nothing.
497    if (insts_available == 0) {
498        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
499                tid);
500        // Should I change status to idle?
501        ++renameIdleCycles;
502        return;
503    } else if (renameStatus[tid] == Unblocking) {
504        ++renameUnblockCycles;
505    } else if (renameStatus[tid] == Running) {
506        ++renameRunCycles;
507    }
508
509    DynInstPtr inst;
510
511    // Will have to do a different calculation for the number of free
512    // entries.
513    int free_rob_entries = calcFreeROBEntries(tid);
514    int free_iq_entries  = calcFreeIQEntries(tid);
515    int free_lsq_entries = calcFreeLSQEntries(tid);
516    int min_free_entries = free_rob_entries;
517
518    FullSource source = ROB;
519
520    if (free_iq_entries < min_free_entries) {
521        min_free_entries = free_iq_entries;
522        source = IQ;
523    }
524
525    if (free_lsq_entries < min_free_entries) {
526        min_free_entries = free_lsq_entries;
527        source = LSQ;
528    }
529
530    // Check if there's any space left.
531    if (min_free_entries <= 0) {
532        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
533                "entries.\n"
534                "ROB has %i free entries.\n"
535                "IQ has %i free entries.\n"
536                "LSQ has %i free entries.\n",
537                tid,
538                free_rob_entries,
539                free_iq_entries,
540                free_lsq_entries);
541
542        blockThisCycle = true;
543
544        block(tid);
545
546        incrFullStat(source);
547
548        return;
549    } else if (min_free_entries < insts_available) {
550        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
551                "%i insts available, but only %i insts can be "
552                "renamed due to ROB/IQ/LSQ limits.\n",
553                tid, insts_available, min_free_entries);
554
555        insts_available = min_free_entries;
556
557        blockThisCycle = true;
558
559        incrFullStat(source);
560    }
561
562    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
563        skidBuffer[tid] : insts[tid];
564
565    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
566            "send iew.\n", tid, insts_available);
567
568    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
569            "dispatched to IQ last cycle.\n",
570            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
571
572    // Handle serializing the next instruction if necessary.
573    if (serializeOnNextInst[tid]) {
574        if (emptyROB[tid] && instsInProgress[tid] == 0) {
575            // ROB already empty; no need to serialize.
576            serializeOnNextInst[tid] = false;
577        } else if (!insts_to_rename.empty()) {
578            insts_to_rename.front()->setSerializeBefore();
579        }
580    }
581
582    int renamed_insts = 0;
583
584    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
585        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
586
587        assert(!insts_to_rename.empty());
588
589        inst = insts_to_rename.front();
590
591        insts_to_rename.pop_front();
592
593        if (renameStatus[tid] == Unblocking) {
594            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
595                    "skidBuffer\n", tid, inst->seqNum, inst->pcState());
596        }
597
598        if (inst->isSquashed()) {
599            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
600                    "squashed, skipping.\n", tid, inst->seqNum,
601                    inst->pcState());
602
603            ++renameSquashedInsts;
604
605            // Decrement how many instructions are available.
606            --insts_available;
607
608            continue;
609        }
610
611        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
612                "PC %s.\n", tid, inst->seqNum, inst->pcState());
613
614        // Handle serializeAfter/serializeBefore instructions.
615        // serializeAfter marks the next instruction as serializeBefore.
616        // serializeBefore makes the instruction wait in rename until the ROB
617        // is empty.
618
619        // In this model, IPR accesses are serialize before
620        // instructions, and store conditionals are serialize after
621        // instructions.  This is mainly due to lack of support for
622        // out-of-order operations of either of those classes of
623        // instructions.
624        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
625            !inst->isSerializeHandled()) {
626            DPRINTF(Rename, "Serialize before instruction encountered.\n");
627
628            if (!inst->isTempSerializeBefore()) {
629                renamedSerializing++;
630                inst->setSerializeHandled();
631            } else {
632                renamedTempSerializing++;
633            }
634
635            // Change status over to SerializeStall so that other stages know
636            // what this is blocked on.
637            renameStatus[tid] = SerializeStall;
638
639            serializeInst[tid] = inst;
640
641            blockThisCycle = true;
642
643            break;
644        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
645                   !inst->isSerializeHandled()) {
646            DPRINTF(Rename, "Serialize after instruction encountered.\n");
647
648            renamedSerializing++;
649
650            inst->setSerializeHandled();
651
652            serializeAfter(insts_to_rename, tid);
653        }
654
655        // Check here to make sure there are enough destination registers
656        // to rename to.  Otherwise block.
657        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
658            DPRINTF(Rename, "Blocking due to lack of free "
659                    "physical registers to rename to.\n");
660            blockThisCycle = true;
661            insts_to_rename.push_front(inst);
662            ++renameFullRegistersEvents;
663
664            break;
665        }
666
667        renameSrcRegs(inst, inst->threadNumber);
668
669        renameDestRegs(inst, inst->threadNumber);
670
671        ++renamed_insts;
672
673        // Put instruction in rename queue.
674        toIEW->insts[toIEWIndex] = inst;
675        ++(toIEW->size);
676
677        // Increment which instruction we're on.
678        ++toIEWIndex;
679
680        // Decrement how many instructions are available.
681        --insts_available;
682    }
683
684    instsInProgress[tid] += renamed_insts;
685    renameRenamedInsts += renamed_insts;
686
687    // If we wrote to the time buffer, record this.
688    if (toIEWIndex) {
689        wroteToTimeBuffer = true;
690    }
691
692    // Check if there's any instructions left that haven't yet been renamed.
693    // If so then block.
694    if (insts_available) {
695        blockThisCycle = true;
696    }
697
698    if (blockThisCycle) {
699        block(tid);
700        toDecode->renameUnblock[tid] = false;
701    }
702}
703
704template<class Impl>
705void
706DefaultRename<Impl>::skidInsert(ThreadID tid)
707{
708    DynInstPtr inst = NULL;
709
710    while (!insts[tid].empty()) {
711        inst = insts[tid].front();
712
713        insts[tid].pop_front();
714
715        assert(tid == inst->threadNumber);
716
717        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
718                "skidBuffer\n", tid, inst->seqNum, inst->pcState());
719
720        ++renameSkidInsts;
721
722        skidBuffer[tid].push_back(inst);
723    }
724
725    if (skidBuffer[tid].size() > skidBufferMax)
726    {
727        typename InstQueue::iterator it;
728        warn("Skidbuffer contents:\n");
729        for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
730        {
731            warn("[tid:%u]: %s [sn:%i].\n", tid,
732                    (*it)->staticInst->disassemble(inst->instAddr()),
733                    (*it)->seqNum);
734        }
735        panic("Skidbuffer Exceeded Max Size");
736    }
737}
738
739template <class Impl>
740void
741DefaultRename<Impl>::sortInsts()
742{
743    int insts_from_decode = fromDecode->size;
744#ifdef DEBUG
745    for (ThreadID tid = 0; tid < numThreads; tid++)
746        assert(insts[tid].empty());
747#endif
748    for (int i = 0; i < insts_from_decode; ++i) {
749        DynInstPtr inst = fromDecode->insts[i];
750        insts[inst->threadNumber].push_back(inst);
751    }
752}
753
754template<class Impl>
755bool
756DefaultRename<Impl>::skidsEmpty()
757{
758    list<ThreadID>::iterator threads = activeThreads->begin();
759    list<ThreadID>::iterator end = activeThreads->end();
760
761    while (threads != end) {
762        ThreadID tid = *threads++;
763
764        if (!skidBuffer[tid].empty())
765            return false;
766    }
767
768    return true;
769}
770
771template<class Impl>
772void
773DefaultRename<Impl>::updateStatus()
774{
775    bool any_unblocking = false;
776
777    list<ThreadID>::iterator threads = activeThreads->begin();
778    list<ThreadID>::iterator end = activeThreads->end();
779
780    while (threads != end) {
781        ThreadID tid = *threads++;
782
783        if (renameStatus[tid] == Unblocking) {
784            any_unblocking = true;
785            break;
786        }
787    }
788
789    // Rename will have activity if it's unblocking.
790    if (any_unblocking) {
791        if (_status == Inactive) {
792            _status = Active;
793
794            DPRINTF(Activity, "Activating stage.\n");
795
796            cpu->activateStage(O3CPU::RenameIdx);
797        }
798    } else {
799        // If it's not unblocking, then rename will not have any internal
800        // activity.  Switch it to inactive.
801        if (_status == Active) {
802            _status = Inactive;
803            DPRINTF(Activity, "Deactivating stage.\n");
804
805            cpu->deactivateStage(O3CPU::RenameIdx);
806        }
807    }
808}
809
810template <class Impl>
811bool
812DefaultRename<Impl>::block(ThreadID tid)
813{
814    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
815
816    // Add the current inputs onto the skid buffer, so they can be
817    // reprocessed when this stage unblocks.
818    skidInsert(tid);
819
820    // Only signal backwards to block if the previous stages do not think
821    // rename is already blocked.
822    if (renameStatus[tid] != Blocked) {
823        // If resumeUnblocking is set, we unblocked during the squash,
824        // but now we're have unblocking status. We need to tell earlier
825        // stages to block.
826        if (resumeUnblocking || renameStatus[tid] != Unblocking) {
827            toDecode->renameBlock[tid] = true;
828            toDecode->renameUnblock[tid] = false;
829            wroteToTimeBuffer = true;
830        }
831
832        // Rename can not go from SerializeStall to Blocked, otherwise
833        // it would not know to complete the serialize stall.
834        if (renameStatus[tid] != SerializeStall) {
835            // Set status to Blocked.
836            renameStatus[tid] = Blocked;
837            return true;
838        }
839    }
840
841    return false;
842}
843
844template <class Impl>
845bool
846DefaultRename<Impl>::unblock(ThreadID tid)
847{
848    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
849
850    // Rename is done unblocking if the skid buffer is empty.
851    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
852
853        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
854
855        toDecode->renameUnblock[tid] = true;
856        wroteToTimeBuffer = true;
857
858        renameStatus[tid] = Running;
859        return true;
860    }
861
862    return false;
863}
864
865template <class Impl>
866void
867DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
868{
869    typename std::list<RenameHistory>::iterator hb_it =
870        historyBuffer[tid].begin();
871
872    // After a syscall squashes everything, the history buffer may be empty
873    // but the ROB may still be squashing instructions.
874    if (historyBuffer[tid].empty()) {
875        return;
876    }
877
878    // Go through the most recent instructions, undoing the mappings
879    // they did and freeing up the registers.
880    while (!historyBuffer[tid].empty() &&
881           (*hb_it).instSeqNum > squashed_seq_num) {
882        assert(hb_it != historyBuffer[tid].end());
883
884        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
885                "number %i.\n", tid, (*hb_it).instSeqNum);
886
887        // Tell the rename map to set the architected register to the
888        // previous physical register that it was renamed to.
889        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
890
891        // Put the renamed physical register back on the free list.
892        freeList->addReg(hb_it->newPhysReg);
893
894        // Be sure to mark its register as ready if it's a misc register.
895        if (hb_it->newPhysReg >= maxPhysicalRegs) {
896            scoreboard->setReg(hb_it->newPhysReg);
897        }
898
899        historyBuffer[tid].erase(hb_it++);
900
901        ++renameUndoneMaps;
902    }
903}
904
905template<class Impl>
906void
907DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
908{
909    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
910            "history buffer %u (size=%i), until [sn:%lli].\n",
911            tid, tid, historyBuffer[tid].size(), inst_seq_num);
912
913    typename std::list<RenameHistory>::iterator hb_it =
914        historyBuffer[tid].end();
915
916    --hb_it;
917
918    if (historyBuffer[tid].empty()) {
919        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
920        return;
921    } else if (hb_it->instSeqNum > inst_seq_num) {
922        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
923                "that a syscall happened recently.\n", tid);
924        return;
925    }
926
927    // Commit all the renames up until (and including) the committed sequence
928    // number. Some or even all of the committed instructions may not have
929    // rename histories if they did not have destination registers that were
930    // renamed.
931    while (!historyBuffer[tid].empty() &&
932           hb_it != historyBuffer[tid].end() &&
933           (*hb_it).instSeqNum <= inst_seq_num) {
934
935        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
936                "[sn:%lli].\n",
937                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
938
939        freeList->addReg((*hb_it).prevPhysReg);
940        ++renameCommittedMaps;
941
942        historyBuffer[tid].erase(hb_it--);
943    }
944}
945
946template <class Impl>
947inline void
948DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
949{
950    assert(renameMap[tid] != 0);
951
952    unsigned num_src_regs = inst->numSrcRegs();
953
954    // Get the architectual register numbers from the source and
955    // destination operands, and redirect them to the right register.
956    // Will need to mark dependencies though.
957    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
958        RegIndex src_reg = inst->srcRegIdx(src_idx);
959        RegIndex flat_src_reg = src_reg;
960        if (src_reg < TheISA::FP_Base_DepTag) {
961            flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
962            DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
963        } else if (src_reg < TheISA::Ctrl_Base_DepTag) {
964            src_reg = src_reg - TheISA::FP_Base_DepTag;
965            flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
966            flat_src_reg += TheISA::NumIntRegs;
967        } else if (src_reg < TheISA::Max_DepTag) {
968            flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
969            DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg);
970        } else {
971            panic("Reg index is out of bound: %d.", src_reg);
972        }
973
974        inst->flattenSrcReg(src_idx, flat_src_reg);
975
976        // Look up the source registers to get the phys. register they've
977        // been renamed to, and set the sources to those registers.
978        PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg);
979
980        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
981                "physical reg %i.\n", tid, (int)flat_src_reg,
982                (int)renamed_reg);
983
984        inst->renameSrcReg(src_idx, renamed_reg);
985
986        // See if the register is ready or not.
987        if (scoreboard->getReg(renamed_reg) == true) {
988            DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", tid, renamed_reg);
989
990            inst->markSrcRegReady(src_idx);
991        } else {
992            DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", tid, renamed_reg);
993        }
994
995        ++renameRenameLookups;
996    }
997}
998
999template <class Impl>
1000inline void
1001DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1002{
1003    typename RenameMap::RenameInfo rename_result;
1004
1005    unsigned num_dest_regs = inst->numDestRegs();
1006
1007    // Rename the destination registers.
1008    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1009        RegIndex dest_reg = inst->destRegIdx(dest_idx);
1010        RegIndex flat_dest_reg = dest_reg;
1011        if (dest_reg < TheISA::FP_Base_DepTag) {
1012            // Integer registers are flattened.
1013            flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
1014            DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
1015        } else if (dest_reg < TheISA::Max_DepTag) {
1016            // Floating point and Miscellaneous registers need their indexes
1017            // adjusted to account for the expanded number of flattened int regs.
1018            flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
1019            DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", dest_reg, flat_dest_reg);
1020        } else {
1021            panic("Reg index is out of bound: %d.", dest_reg);
1022        }
1023
1024        inst->flattenDestReg(dest_idx, flat_dest_reg);
1025
1026        // Get the physical register that the destination will be
1027        // renamed to.
1028        rename_result = renameMap[tid]->rename(flat_dest_reg);
1029
1030        //Mark Scoreboard entry as not ready
1031        scoreboard->unsetReg(rename_result.first);
1032
1033        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1034                "reg %i.\n", tid, (int)flat_dest_reg,
1035                (int)rename_result.first);
1036
1037        // Record the rename information so that a history can be kept.
1038        RenameHistory hb_entry(inst->seqNum, flat_dest_reg,
1039                               rename_result.first,
1040                               rename_result.second);
1041
1042        historyBuffer[tid].push_front(hb_entry);
1043
1044        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1045                "(size=%i), [sn:%lli].\n",tid,
1046                historyBuffer[tid].size(),
1047                (*historyBuffer[tid].begin()).instSeqNum);
1048
1049        // Tell the instruction to rename the appropriate destination
1050        // register (dest_idx) to the new physical register
1051        // (rename_result.first), and record the previous physical
1052        // register that the same logical register was renamed to
1053        // (rename_result.second).
1054        inst->renameDestReg(dest_idx,
1055                            rename_result.first,
1056                            rename_result.second);
1057
1058        ++renameRenamedOperands;
1059    }
1060}
1061
1062template <class Impl>
1063inline int
1064DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1065{
1066    int num_free = freeEntries[tid].robEntries -
1067                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1068
1069    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1070
1071    return num_free;
1072}
1073
1074template <class Impl>
1075inline int
1076DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1077{
1078    int num_free = freeEntries[tid].iqEntries -
1079                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1080
1081    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1082
1083    return num_free;
1084}
1085
1086template <class Impl>
1087inline int
1088DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
1089{
1090    int num_free = freeEntries[tid].lsqEntries -
1091                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1092
1093    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1094
1095    return num_free;
1096}
1097
1098template <class Impl>
1099unsigned
1100DefaultRename<Impl>::validInsts()
1101{
1102    unsigned inst_count = 0;
1103
1104    for (int i=0; i<fromDecode->size; i++) {
1105        if (!fromDecode->insts[i]->isSquashed())
1106            inst_count++;
1107    }
1108
1109    return inst_count;
1110}
1111
1112template <class Impl>
1113void
1114DefaultRename<Impl>::readStallSignals(ThreadID tid)
1115{
1116    if (fromIEW->iewBlock[tid]) {
1117        stalls[tid].iew = true;
1118    }
1119
1120    if (fromIEW->iewUnblock[tid]) {
1121        assert(stalls[tid].iew);
1122        stalls[tid].iew = false;
1123    }
1124
1125    if (fromCommit->commitBlock[tid]) {
1126        stalls[tid].commit = true;
1127    }
1128
1129    if (fromCommit->commitUnblock[tid]) {
1130        assert(stalls[tid].commit);
1131        stalls[tid].commit = false;
1132    }
1133}
1134
1135template <class Impl>
1136bool
1137DefaultRename<Impl>::checkStall(ThreadID tid)
1138{
1139    bool ret_val = false;
1140
1141    if (stalls[tid].iew) {
1142        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1143        ret_val = true;
1144    } else if (stalls[tid].commit) {
1145        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1146        ret_val = true;
1147    } else if (calcFreeROBEntries(tid) <= 0) {
1148        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1149        ret_val = true;
1150    } else if (calcFreeIQEntries(tid) <= 0) {
1151        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1152        ret_val = true;
1153    } else if (calcFreeLSQEntries(tid) <= 0) {
1154        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1155        ret_val = true;
1156    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1157        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1158        ret_val = true;
1159    } else if (renameStatus[tid] == SerializeStall &&
1160               (!emptyROB[tid] || instsInProgress[tid])) {
1161        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1162                "empty.\n",
1163                tid);
1164        ret_val = true;
1165    }
1166
1167    return ret_val;
1168}
1169
1170template <class Impl>
1171void
1172DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1173{
1174    bool updated = false;
1175    if (fromIEW->iewInfo[tid].usedIQ) {
1176        freeEntries[tid].iqEntries =
1177            fromIEW->iewInfo[tid].freeIQEntries;
1178        updated = true;
1179    }
1180
1181    if (fromIEW->iewInfo[tid].usedLSQ) {
1182        freeEntries[tid].lsqEntries =
1183            fromIEW->iewInfo[tid].freeLSQEntries;
1184        updated = true;
1185    }
1186
1187    if (fromCommit->commitInfo[tid].usedROB) {
1188        freeEntries[tid].robEntries =
1189            fromCommit->commitInfo[tid].freeROBEntries;
1190        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1191        updated = true;
1192    }
1193
1194    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1195            tid,
1196            freeEntries[tid].iqEntries,
1197            freeEntries[tid].robEntries,
1198            freeEntries[tid].lsqEntries);
1199
1200    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1201            tid, instsInProgress[tid]);
1202}
1203
1204template <class Impl>
1205bool
1206DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1207{
1208    // Check if there's a squash signal, squash if there is
1209    // Check stall signals, block if necessary.
1210    // If status was blocked
1211    //     check if stall conditions have passed
1212    //         if so then go to unblocking
1213    // If status was Squashing
1214    //     check if squashing is not high.  Switch to running this cycle.
1215    // If status was serialize stall
1216    //     check if ROB is empty and no insts are in flight to the ROB
1217
1218    readFreeEntries(tid);
1219    readStallSignals(tid);
1220
1221    if (fromCommit->commitInfo[tid].squash) {
1222        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1223                "commit.\n", tid);
1224
1225        squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1226
1227        return true;
1228    }
1229
1230    if (fromCommit->commitInfo[tid].robSquashing) {
1231        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1232
1233        renameStatus[tid] = Squashing;
1234
1235        return true;
1236    }
1237
1238    if (checkStall(tid)) {
1239        return block(tid);
1240    }
1241
1242    if (renameStatus[tid] == Blocked) {
1243        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1244                tid);
1245
1246        renameStatus[tid] = Unblocking;
1247
1248        unblock(tid);
1249
1250        return true;
1251    }
1252
1253    if (renameStatus[tid] == Squashing) {
1254        // Switch status to running if rename isn't being told to block or
1255        // squash this cycle.
1256        if (resumeSerialize) {
1257            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1258                    tid);
1259
1260            renameStatus[tid] = SerializeStall;
1261            return true;
1262        } else if (resumeUnblocking) {
1263            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1264                    tid);
1265            renameStatus[tid] = Unblocking;
1266            return true;
1267        } else {
1268            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1269                    tid);
1270
1271            renameStatus[tid] = Running;
1272            return false;
1273        }
1274    }
1275
1276    if (renameStatus[tid] == SerializeStall) {
1277        // Stall ends once the ROB is free.
1278        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1279                "unblocking.\n", tid);
1280
1281        DynInstPtr serial_inst = serializeInst[tid];
1282
1283        renameStatus[tid] = Unblocking;
1284
1285        unblock(tid);
1286
1287        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1288                "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1289
1290        // Put instruction into queue here.
1291        serial_inst->clearSerializeBefore();
1292
1293        if (!skidBuffer[tid].empty()) {
1294            skidBuffer[tid].push_front(serial_inst);
1295        } else {
1296            insts[tid].push_front(serial_inst);
1297        }
1298
1299        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1300                " Adding to front of list.\n", tid);
1301
1302        serializeInst[tid] = NULL;
1303
1304        return true;
1305    }
1306
1307    // If we've reached this point, we have not gotten any signals that
1308    // cause rename to change its status.  Rename remains the same as before.
1309    return false;
1310}
1311
1312template<class Impl>
1313void
1314DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1315{
1316    if (inst_list.empty()) {
1317        // Mark a bit to say that I must serialize on the next instruction.
1318        serializeOnNextInst[tid] = true;
1319        return;
1320    }
1321
1322    // Set the next instruction as serializing.
1323    inst_list.front()->setSerializeBefore();
1324}
1325
1326template <class Impl>
1327inline void
1328DefaultRename<Impl>::incrFullStat(const FullSource &source)
1329{
1330    switch (source) {
1331      case ROB:
1332        ++renameROBFullEvents;
1333        break;
1334      case IQ:
1335        ++renameIQFullEvents;
1336        break;
1337      case LSQ:
1338        ++renameLSQFullEvents;
1339        break;
1340      default:
1341        panic("Rename full stall stat should be incremented for a reason!");
1342        break;
1343    }
1344}
1345
1346template <class Impl>
1347void
1348DefaultRename<Impl>::dumpHistory()
1349{
1350    typename std::list<RenameHistory>::iterator buf_it;
1351
1352    for (ThreadID tid = 0; tid < numThreads; tid++) {
1353
1354        buf_it = historyBuffer[tid].begin();
1355
1356        while (buf_it != historyBuffer[tid].end()) {
1357            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1358                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1359                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1360
1361            buf_it++;
1362        }
1363    }
1364}
1365