rename_impl.hh revision 3867:807483cfab77 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#include <list>
33
34#include "config/full_system.hh"
35#include "cpu/o3/rename.hh"
36
37template <class Impl>
38DefaultRename<Impl>::DefaultRename(Params *params)
39    : iewToRenameDelay(params->iewToRenameDelay),
40      decodeToRenameDelay(params->decodeToRenameDelay),
41      commitToRenameDelay(params->commitToRenameDelay),
42      renameWidth(params->renameWidth),
43      commitWidth(params->commitWidth),
44      numThreads(params->numberOfThreads),
45      maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
46{
47    _status = Inactive;
48
49    for (int i=0; i< numThreads; i++) {
50        renameStatus[i] = Idle;
51
52        freeEntries[i].iqEntries = 0;
53        freeEntries[i].lsqEntries = 0;
54        freeEntries[i].robEntries = 0;
55
56        stalls[i].iew = false;
57        stalls[i].commit = false;
58        serializeInst[i] = NULL;
59
60        instsInProgress[i] = 0;
61
62        emptyROB[i] = true;
63
64        serializeOnNextInst[i] = false;
65    }
66
67    // @todo: Make into a parameter.
68    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
69}
70
71template <class Impl>
72std::string
73DefaultRename<Impl>::name() const
74{
75    return cpu->name() + ".rename";
76}
77
78template <class Impl>
79void
80DefaultRename<Impl>::regStats()
81{
82    renameSquashCycles
83        .name(name() + ".RENAME:SquashCycles")
84        .desc("Number of cycles rename is squashing")
85        .prereq(renameSquashCycles);
86    renameIdleCycles
87        .name(name() + ".RENAME:IdleCycles")
88        .desc("Number of cycles rename is idle")
89        .prereq(renameIdleCycles);
90    renameBlockCycles
91        .name(name() + ".RENAME:BlockCycles")
92        .desc("Number of cycles rename is blocking")
93        .prereq(renameBlockCycles);
94    renameSerializeStallCycles
95        .name(name() + ".RENAME:serializeStallCycles")
96        .desc("count of cycles rename stalled for serializing inst")
97        .flags(Stats::total);
98    renameRunCycles
99        .name(name() + ".RENAME:RunCycles")
100        .desc("Number of cycles rename is running")
101        .prereq(renameIdleCycles);
102    renameUnblockCycles
103        .name(name() + ".RENAME:UnblockCycles")
104        .desc("Number of cycles rename is unblocking")
105        .prereq(renameUnblockCycles);
106    renameRenamedInsts
107        .name(name() + ".RENAME:RenamedInsts")
108        .desc("Number of instructions processed by rename")
109        .prereq(renameRenamedInsts);
110    renameSquashedInsts
111        .name(name() + ".RENAME:SquashedInsts")
112        .desc("Number of squashed instructions processed by rename")
113        .prereq(renameSquashedInsts);
114    renameROBFullEvents
115        .name(name() + ".RENAME:ROBFullEvents")
116        .desc("Number of times rename has blocked due to ROB full")
117        .prereq(renameROBFullEvents);
118    renameIQFullEvents
119        .name(name() + ".RENAME:IQFullEvents")
120        .desc("Number of times rename has blocked due to IQ full")
121        .prereq(renameIQFullEvents);
122    renameLSQFullEvents
123        .name(name() + ".RENAME:LSQFullEvents")
124        .desc("Number of times rename has blocked due to LSQ full")
125        .prereq(renameLSQFullEvents);
126    renameFullRegistersEvents
127        .name(name() + ".RENAME:FullRegisterEvents")
128        .desc("Number of times there has been no free registers")
129        .prereq(renameFullRegistersEvents);
130    renameRenamedOperands
131        .name(name() + ".RENAME:RenamedOperands")
132        .desc("Number of destination operands rename has renamed")
133        .prereq(renameRenamedOperands);
134    renameRenameLookups
135        .name(name() + ".RENAME:RenameLookups")
136        .desc("Number of register rename lookups that rename has made")
137        .prereq(renameRenameLookups);
138    renameCommittedMaps
139        .name(name() + ".RENAME:CommittedMaps")
140        .desc("Number of HB maps that are committed")
141        .prereq(renameCommittedMaps);
142    renameUndoneMaps
143        .name(name() + ".RENAME:UndoneMaps")
144        .desc("Number of HB maps that are undone due to squashing")
145        .prereq(renameUndoneMaps);
146    renamedSerializing
147        .name(name() + ".RENAME:serializingInsts")
148        .desc("count of serializing insts renamed")
149        .flags(Stats::total)
150        ;
151    renamedTempSerializing
152        .name(name() + ".RENAME:tempSerializingInsts")
153        .desc("count of temporary serializing insts renamed")
154        .flags(Stats::total)
155        ;
156    renameSkidInsts
157        .name(name() + ".RENAME:skidInsts")
158        .desc("count of insts added to the skid buffer")
159        .flags(Stats::total)
160        ;
161}
162
163template <class Impl>
164void
165DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
166{
167    DPRINTF(Rename, "Setting CPU pointer.\n");
168    cpu = cpu_ptr;
169}
170
171template <class Impl>
172void
173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174{
175    DPRINTF(Rename, "Setting time buffer pointer.\n");
176    timeBuffer = tb_ptr;
177
178    // Setup wire to read information from time buffer, from IEW stage.
179    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181    // Setup wire to read infromation from time buffer, from commit stage.
182    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184    // Setup wire to write information to previous stages.
185    toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192    DPRINTF(Rename, "Setting rename queue pointer.\n");
193    renameQueue = rq_ptr;
194
195    // Setup wire to write information to future stages.
196    toIEW = renameQueue->getWire(0);
197}
198
199template <class Impl>
200void
201DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
202{
203    DPRINTF(Rename, "Setting decode queue pointer.\n");
204    decodeQueue = dq_ptr;
205
206    // Setup wire to get information from decode.
207    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::initStage()
213{
214    // Grab the number of free entries directly from the stages.
215    for (int tid=0; tid < numThreads; tid++) {
216        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
217        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
218        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
219        emptyROB[tid] = true;
220    }
221}
222
223template<class Impl>
224void
225DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
226{
227    DPRINTF(Rename, "Setting active threads list pointer.\n");
228    activeThreads = at_ptr;
229}
230
231
232template <class Impl>
233void
234DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
235{
236    DPRINTF(Rename, "Setting rename map pointers.\n");
237
238    for (int i=0; i<numThreads; i++) {
239        renameMap[i] = &rm_ptr[i];
240    }
241}
242
243template <class Impl>
244void
245DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
246{
247    DPRINTF(Rename, "Setting free list pointer.\n");
248    freeList = fl_ptr;
249}
250
251template<class Impl>
252void
253DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
254{
255    DPRINTF(Rename, "Setting scoreboard pointer.\n");
256    scoreboard = _scoreboard;
257}
258
259template <class Impl>
260bool
261DefaultRename<Impl>::drain()
262{
263    // Rename is ready to switch out at any time.
264    cpu->signalDrained();
265    return true;
266}
267
268template <class Impl>
269void
270DefaultRename<Impl>::switchOut()
271{
272    // Clear any state, fix up the rename map.
273    for (int i = 0; i < numThreads; i++) {
274        typename std::list<RenameHistory>::iterator hb_it =
275            historyBuffer[i].begin();
276
277        while (!historyBuffer[i].empty()) {
278            assert(hb_it != historyBuffer[i].end());
279
280            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
281                    "number %i.\n", i, (*hb_it).instSeqNum);
282
283            // Tell the rename map to set the architected register to the
284            // previous physical register that it was renamed to.
285            renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
286
287            // Put the renamed physical register back on the free list.
288            freeList->addReg(hb_it->newPhysReg);
289
290            // Be sure to mark its register as ready if it's a misc register.
291            if (hb_it->newPhysReg >= maxPhysicalRegs) {
292                scoreboard->setReg(hb_it->newPhysReg);
293            }
294
295            historyBuffer[i].erase(hb_it++);
296        }
297        insts[i].clear();
298        skidBuffer[i].clear();
299    }
300}
301
302template <class Impl>
303void
304DefaultRename<Impl>::takeOverFrom()
305{
306    _status = Inactive;
307    initStage();
308
309    // Reset all state prior to taking over from the other CPU.
310    for (int i=0; i< numThreads; i++) {
311        renameStatus[i] = Idle;
312
313        stalls[i].iew = false;
314        stalls[i].commit = false;
315        serializeInst[i] = NULL;
316
317        instsInProgress[i] = 0;
318
319        emptyROB[i] = true;
320
321        serializeOnNextInst[i] = false;
322    }
323}
324
325template <class Impl>
326void
327DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
328{
329    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
330
331    // Clear the stall signal if rename was blocked or unblocking before.
332    // If it still needs to block, the blocking should happen the next
333    // cycle and there should be space to hold everything due to the squash.
334    if (renameStatus[tid] == Blocked ||
335        renameStatus[tid] == Unblocking ||
336        renameStatus[tid] == SerializeStall) {
337
338        toDecode->renameUnblock[tid] = 1;
339
340        serializeInst[tid] = NULL;
341    }
342
343    // Set the status to Squashing.
344    renameStatus[tid] = Squashing;
345
346    // Squash any instructions from decode.
347    unsigned squashCount = 0;
348
349    for (int i=0; i<fromDecode->size; i++) {
350        if (fromDecode->insts[i]->threadNumber == tid &&
351            fromDecode->insts[i]->seqNum > squash_seq_num) {
352            fromDecode->insts[i]->setSquashed();
353            wroteToTimeBuffer = true;
354            squashCount++;
355        }
356
357    }
358
359    // Clear the instruction list and skid buffer in case they have any
360    // insts in them. Since we support multiple ISAs, we cant just:
361    // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is
362    // a possible delay slot inst for different architectures
363    // insts[tid].clear();
364#if ISA_HAS_DELAY_SLOT
365    DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until "
366            "[sn:%i].\n",tid, squash_seq_num);
367    ListIt ilist_it = insts[tid].begin();
368    while (ilist_it != insts[tid].end()) {
369        if ((*ilist_it)->seqNum > squash_seq_num) {
370            (*ilist_it)->setSquashed();
371            DPRINTF(Rename, "Squashing incoming decode instruction, "
372                    "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC);
373        }
374        ilist_it++;
375    }
376#else
377    insts[tid].clear();
378#endif
379
380    // Clear the skid buffer in case it has any data in it.
381    // See comments above.
382    //     skidBuffer[tid].clear();
383#if ISA_HAS_DELAY_SLOT
384    DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions "
385            "until [sn:%i].\n", tid, squash_seq_num);
386    ListIt slist_it = skidBuffer[tid].begin();
387    while (slist_it != skidBuffer[tid].end()) {
388        if ((*slist_it)->seqNum > squash_seq_num) {
389            (*slist_it)->setSquashed();
390            DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]"
391                    "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC);
392        }
393        slist_it++;
394    }
395#else
396    skidBuffer[tid].clear();
397#endif
398    doSquash(squash_seq_num, tid);
399}
400
401template <class Impl>
402void
403DefaultRename<Impl>::tick()
404{
405    wroteToTimeBuffer = false;
406
407    blockThisCycle = false;
408
409    bool status_change = false;
410
411    toIEWIndex = 0;
412
413    sortInsts();
414
415    std::list<unsigned>::iterator threads = activeThreads->begin();
416    std::list<unsigned>::iterator end = activeThreads->end();
417
418    // Check stall and squash signals.
419    while (threads != end) {
420        unsigned tid = *threads++;
421
422        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
423
424        status_change = checkSignalsAndUpdate(tid) || status_change;
425
426        rename(status_change, tid);
427    }
428
429    if (status_change) {
430        updateStatus();
431    }
432
433    if (wroteToTimeBuffer) {
434        DPRINTF(Activity, "Activity this cycle.\n");
435        cpu->activityThisCycle();
436    }
437
438    threads = activeThreads->begin();
439
440    while (threads != end) {
441        unsigned tid = *threads++;
442
443        // If we committed this cycle then doneSeqNum will be > 0
444        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
445            !fromCommit->commitInfo[tid].squash &&
446            renameStatus[tid] != Squashing) {
447
448            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
449                                  tid);
450        }
451    }
452
453    // @todo: make into updateProgress function
454    for (int tid=0; tid < numThreads; tid++) {
455        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
456
457        assert(instsInProgress[tid] >=0);
458    }
459
460}
461
462template<class Impl>
463void
464DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
465{
466    // If status is Running or idle,
467    //     call renameInsts()
468    // If status is Unblocking,
469    //     buffer any instructions coming from decode
470    //     continue trying to empty skid buffer
471    //     check if stall conditions have passed
472
473    if (renameStatus[tid] == Blocked) {
474        ++renameBlockCycles;
475    } else if (renameStatus[tid] == Squashing) {
476        ++renameSquashCycles;
477    } else if (renameStatus[tid] == SerializeStall) {
478        ++renameSerializeStallCycles;
479    }
480
481    if (renameStatus[tid] == Running ||
482        renameStatus[tid] == Idle) {
483        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
484                "stage.\n", tid);
485
486        renameInsts(tid);
487    } else if (renameStatus[tid] == Unblocking) {
488        renameInsts(tid);
489
490        if (validInsts()) {
491            // Add the current inputs to the skid buffer so they can be
492            // reprocessed when this stage unblocks.
493            skidInsert(tid);
494        }
495
496        // If we switched over to blocking, then there's a potential for
497        // an overall status change.
498        status_change = unblock(tid) || status_change || blockThisCycle;
499    }
500}
501
502template <class Impl>
503void
504DefaultRename<Impl>::renameInsts(unsigned tid)
505{
506    // Instructions can be either in the skid buffer or the queue of
507    // instructions coming from decode, depending on the status.
508    int insts_available = renameStatus[tid] == Unblocking ?
509        skidBuffer[tid].size() : insts[tid].size();
510
511    // Check the decode queue to see if instructions are available.
512    // If there are no available instructions to rename, then do nothing.
513    if (insts_available == 0) {
514        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
515                tid);
516        // Should I change status to idle?
517        ++renameIdleCycles;
518        return;
519    } else if (renameStatus[tid] == Unblocking) {
520        ++renameUnblockCycles;
521    } else if (renameStatus[tid] == Running) {
522        ++renameRunCycles;
523    }
524
525    DynInstPtr inst;
526
527    // Will have to do a different calculation for the number of free
528    // entries.
529    int free_rob_entries = calcFreeROBEntries(tid);
530    int free_iq_entries  = calcFreeIQEntries(tid);
531    int free_lsq_entries = calcFreeLSQEntries(tid);
532    int min_free_entries = free_rob_entries;
533
534    FullSource source = ROB;
535
536    if (free_iq_entries < min_free_entries) {
537        min_free_entries = free_iq_entries;
538        source = IQ;
539    }
540
541    if (free_lsq_entries < min_free_entries) {
542        min_free_entries = free_lsq_entries;
543        source = LSQ;
544    }
545
546    // Check if there's any space left.
547    if (min_free_entries <= 0) {
548        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
549                "entries.\n"
550                "ROB has %i free entries.\n"
551                "IQ has %i free entries.\n"
552                "LSQ has %i free entries.\n",
553                tid,
554                free_rob_entries,
555                free_iq_entries,
556                free_lsq_entries);
557
558        blockThisCycle = true;
559
560        block(tid);
561
562        incrFullStat(source);
563
564        return;
565    } else if (min_free_entries < insts_available) {
566        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
567                "%i insts available, but only %i insts can be "
568                "renamed due to ROB/IQ/LSQ limits.\n",
569                tid, insts_available, min_free_entries);
570
571        insts_available = min_free_entries;
572
573        blockThisCycle = true;
574
575        incrFullStat(source);
576    }
577
578    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
579        skidBuffer[tid] : insts[tid];
580
581    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
582            "send iew.\n", tid, insts_available);
583
584    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
585            "dispatched to IQ last cycle.\n",
586            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
587
588    // Handle serializing the next instruction if necessary.
589    if (serializeOnNextInst[tid]) {
590        if (emptyROB[tid] && instsInProgress[tid] == 0) {
591            // ROB already empty; no need to serialize.
592            serializeOnNextInst[tid] = false;
593        } else if (!insts_to_rename.empty()) {
594            insts_to_rename.front()->setSerializeBefore();
595        }
596    }
597
598    int renamed_insts = 0;
599
600    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
601        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
602
603        assert(!insts_to_rename.empty());
604
605        inst = insts_to_rename.front();
606
607        insts_to_rename.pop_front();
608
609        if (renameStatus[tid] == Unblocking) {
610            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
611                    "skidBuffer\n",
612                    tid, inst->seqNum, inst->readPC());
613        }
614
615        if (inst->isSquashed()) {
616            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
617                    "squashed, skipping.\n",
618                    tid, inst->seqNum, inst->readPC());
619
620            ++renameSquashedInsts;
621
622            // Decrement how many instructions are available.
623            --insts_available;
624
625            continue;
626        }
627
628        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
629                "PC %#x.\n",
630                tid, inst->seqNum, inst->readPC());
631
632        // Handle serializeAfter/serializeBefore instructions.
633        // serializeAfter marks the next instruction as serializeBefore.
634        // serializeBefore makes the instruction wait in rename until the ROB
635        // is empty.
636
637        // In this model, IPR accesses are serialize before
638        // instructions, and store conditionals are serialize after
639        // instructions.  This is mainly due to lack of support for
640        // out-of-order operations of either of those classes of
641        // instructions.
642        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
643            !inst->isSerializeHandled()) {
644            DPRINTF(Rename, "Serialize before instruction encountered.\n");
645
646            if (!inst->isTempSerializeBefore()) {
647                renamedSerializing++;
648                inst->setSerializeHandled();
649            } else {
650                renamedTempSerializing++;
651            }
652
653            // Change status over to SerializeStall so that other stages know
654            // what this is blocked on.
655            renameStatus[tid] = SerializeStall;
656
657            serializeInst[tid] = inst;
658
659            blockThisCycle = true;
660
661            break;
662        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
663                   !inst->isSerializeHandled()) {
664            DPRINTF(Rename, "Serialize after instruction encountered.\n");
665
666            renamedSerializing++;
667
668            inst->setSerializeHandled();
669
670            serializeAfter(insts_to_rename, tid);
671        }
672
673        // Check here to make sure there are enough destination registers
674        // to rename to.  Otherwise block.
675        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
676            DPRINTF(Rename, "Blocking due to lack of free "
677                    "physical registers to rename to.\n");
678            blockThisCycle = true;
679
680            ++renameFullRegistersEvents;
681
682            break;
683        }
684
685        renameSrcRegs(inst, inst->threadNumber);
686
687        renameDestRegs(inst, inst->threadNumber);
688
689        ++renamed_insts;
690
691        // Put instruction in rename queue.
692        toIEW->insts[toIEWIndex] = inst;
693        ++(toIEW->size);
694
695        // Increment which instruction we're on.
696        ++toIEWIndex;
697
698        // Decrement how many instructions are available.
699        --insts_available;
700    }
701
702    instsInProgress[tid] += renamed_insts;
703    renameRenamedInsts += renamed_insts;
704
705    // If we wrote to the time buffer, record this.
706    if (toIEWIndex) {
707        wroteToTimeBuffer = true;
708    }
709
710    // Check if there's any instructions left that haven't yet been renamed.
711    // If so then block.
712    if (insts_available) {
713        blockThisCycle = true;
714    }
715
716    if (blockThisCycle) {
717        block(tid);
718        toDecode->renameUnblock[tid] = false;
719    }
720}
721
722template<class Impl>
723void
724DefaultRename<Impl>::skidInsert(unsigned tid)
725{
726    DynInstPtr inst = NULL;
727
728    while (!insts[tid].empty()) {
729        inst = insts[tid].front();
730
731        insts[tid].pop_front();
732
733        assert(tid == inst->threadNumber);
734
735        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
736                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
737
738        ++renameSkidInsts;
739
740        skidBuffer[tid].push_back(inst);
741    }
742
743    if (skidBuffer[tid].size() > skidBufferMax)
744        panic("Skidbuffer Exceeded Max Size");
745}
746
747template <class Impl>
748void
749DefaultRename<Impl>::sortInsts()
750{
751    int insts_from_decode = fromDecode->size;
752#ifdef DEBUG
753#if !ISA_HAS_DELAY_SLOT
754    for (int i=0; i < numThreads; i++)
755        assert(insts[i].empty());
756#endif
757#endif
758    for (int i = 0; i < insts_from_decode; ++i) {
759        DynInstPtr inst = fromDecode->insts[i];
760        insts[inst->threadNumber].push_back(inst);
761    }
762}
763
764template<class Impl>
765bool
766DefaultRename<Impl>::skidsEmpty()
767{
768    std::list<unsigned>::iterator threads = activeThreads->begin();
769    std::list<unsigned>::iterator end = activeThreads->end();
770
771    while (threads != end) {
772        unsigned tid = *threads++;
773
774        if (!skidBuffer[tid].empty())
775            return false;
776    }
777
778    return true;
779}
780
781template<class Impl>
782void
783DefaultRename<Impl>::updateStatus()
784{
785    bool any_unblocking = false;
786
787    std::list<unsigned>::iterator threads = activeThreads->begin();
788    std::list<unsigned>::iterator end = activeThreads->end();
789
790    while (threads != end) {
791        unsigned tid = *threads++;
792
793        if (renameStatus[tid] == Unblocking) {
794            any_unblocking = true;
795            break;
796        }
797    }
798
799    // Rename will have activity if it's unblocking.
800    if (any_unblocking) {
801        if (_status == Inactive) {
802            _status = Active;
803
804            DPRINTF(Activity, "Activating stage.\n");
805
806            cpu->activateStage(O3CPU::RenameIdx);
807        }
808    } else {
809        // If it's not unblocking, then rename will not have any internal
810        // activity.  Switch it to inactive.
811        if (_status == Active) {
812            _status = Inactive;
813            DPRINTF(Activity, "Deactivating stage.\n");
814
815            cpu->deactivateStage(O3CPU::RenameIdx);
816        }
817    }
818}
819
820template <class Impl>
821bool
822DefaultRename<Impl>::block(unsigned tid)
823{
824    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
825
826    // Add the current inputs onto the skid buffer, so they can be
827    // reprocessed when this stage unblocks.
828    skidInsert(tid);
829
830    // Only signal backwards to block if the previous stages do not think
831    // rename is already blocked.
832    if (renameStatus[tid] != Blocked) {
833        if (renameStatus[tid] != Unblocking) {
834            toDecode->renameBlock[tid] = true;
835            toDecode->renameUnblock[tid] = false;
836            wroteToTimeBuffer = true;
837        }
838
839        // Rename can not go from SerializeStall to Blocked, otherwise
840        // it would not know to complete the serialize stall.
841        if (renameStatus[tid] != SerializeStall) {
842            // Set status to Blocked.
843            renameStatus[tid] = Blocked;
844            return true;
845        }
846    }
847
848    return false;
849}
850
851template <class Impl>
852bool
853DefaultRename<Impl>::unblock(unsigned tid)
854{
855    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
856
857    // Rename is done unblocking if the skid buffer is empty.
858    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
859
860        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
861
862        toDecode->renameUnblock[tid] = true;
863        wroteToTimeBuffer = true;
864
865        renameStatus[tid] = Running;
866        return true;
867    }
868
869    return false;
870}
871
872template <class Impl>
873void
874DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
875{
876    typename std::list<RenameHistory>::iterator hb_it =
877        historyBuffer[tid].begin();
878
879    // After a syscall squashes everything, the history buffer may be empty
880    // but the ROB may still be squashing instructions.
881    if (historyBuffer[tid].empty()) {
882        return;
883    }
884
885    // Go through the most recent instructions, undoing the mappings
886    // they did and freeing up the registers.
887    while (!historyBuffer[tid].empty() &&
888           (*hb_it).instSeqNum > squashed_seq_num) {
889        assert(hb_it != historyBuffer[tid].end());
890
891        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
892                "number %i.\n", tid, (*hb_it).instSeqNum);
893
894        // Tell the rename map to set the architected register to the
895        // previous physical register that it was renamed to.
896        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
897
898        // Put the renamed physical register back on the free list.
899        freeList->addReg(hb_it->newPhysReg);
900
901        // Be sure to mark its register as ready if it's a misc register.
902        if (hb_it->newPhysReg >= maxPhysicalRegs) {
903            scoreboard->setReg(hb_it->newPhysReg);
904        }
905
906        historyBuffer[tid].erase(hb_it++);
907
908        ++renameUndoneMaps;
909    }
910}
911
912template<class Impl>
913void
914DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
915{
916    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
917            "history buffer %u (size=%i), until [sn:%lli].\n",
918            tid, tid, historyBuffer[tid].size(), inst_seq_num);
919
920    typename std::list<RenameHistory>::iterator hb_it =
921        historyBuffer[tid].end();
922
923    --hb_it;
924
925    if (historyBuffer[tid].empty()) {
926        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
927        return;
928    } else if (hb_it->instSeqNum > inst_seq_num) {
929        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
930                "that a syscall happened recently.\n", tid);
931        return;
932    }
933
934    // Commit all the renames up until (and including) the committed sequence
935    // number. Some or even all of the committed instructions may not have
936    // rename histories if they did not have destination registers that were
937    // renamed.
938    while (!historyBuffer[tid].empty() &&
939           hb_it != historyBuffer[tid].end() &&
940           (*hb_it).instSeqNum <= inst_seq_num) {
941
942        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
943                "[sn:%lli].\n",
944                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
945
946        freeList->addReg((*hb_it).prevPhysReg);
947        ++renameCommittedMaps;
948
949        historyBuffer[tid].erase(hb_it--);
950    }
951}
952
953template <class Impl>
954inline void
955DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
956{
957    assert(renameMap[tid] != 0);
958
959    unsigned num_src_regs = inst->numSrcRegs();
960
961    // Get the architectual register numbers from the source and
962    // destination operands, and redirect them to the right register.
963    // Will need to mark dependencies though.
964    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
965        RegIndex src_reg = inst->srcRegIdx(src_idx);
966
967        // Look up the source registers to get the phys. register they've
968        // been renamed to, and set the sources to those registers.
969        PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
970
971        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
972                "physical reg %i.\n", tid, (int)src_reg,
973                (int)renamed_reg);
974
975        inst->renameSrcReg(src_idx, renamed_reg);
976
977        // See if the register is ready or not.
978        if (scoreboard->getReg(renamed_reg) == true) {
979            DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
980
981            inst->markSrcRegReady(src_idx);
982        }
983
984        ++renameRenameLookups;
985    }
986}
987
988template <class Impl>
989inline void
990DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
991{
992    typename RenameMap::RenameInfo rename_result;
993
994    unsigned num_dest_regs = inst->numDestRegs();
995
996    // Rename the destination registers.
997    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
998        RegIndex dest_reg = inst->destRegIdx(dest_idx);
999
1000        // Get the physical register that the destination will be
1001        // renamed to.
1002        rename_result = renameMap[tid]->rename(dest_reg);
1003
1004        //Mark Scoreboard entry as not ready
1005        scoreboard->unsetReg(rename_result.first);
1006
1007        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
1008                "reg %i.\n", tid, (int)dest_reg,
1009                (int)rename_result.first);
1010
1011        // Record the rename information so that a history can be kept.
1012        RenameHistory hb_entry(inst->seqNum, dest_reg,
1013                               rename_result.first,
1014                               rename_result.second);
1015
1016        historyBuffer[tid].push_front(hb_entry);
1017
1018        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1019                "(size=%i), [sn:%lli].\n",tid,
1020                historyBuffer[tid].size(),
1021                (*historyBuffer[tid].begin()).instSeqNum);
1022
1023        // Tell the instruction to rename the appropriate destination
1024        // register (dest_idx) to the new physical register
1025        // (rename_result.first), and record the previous physical
1026        // register that the same logical register was renamed to
1027        // (rename_result.second).
1028        inst->renameDestReg(dest_idx,
1029                            rename_result.first,
1030                            rename_result.second);
1031
1032        ++renameRenamedOperands;
1033    }
1034}
1035
1036template <class Impl>
1037inline int
1038DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
1039{
1040    int num_free = freeEntries[tid].robEntries -
1041                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1042
1043    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1044
1045    return num_free;
1046}
1047
1048template <class Impl>
1049inline int
1050DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1051{
1052    int num_free = freeEntries[tid].iqEntries -
1053                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1054
1055    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1056
1057    return num_free;
1058}
1059
1060template <class Impl>
1061inline int
1062DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1063{
1064    int num_free = freeEntries[tid].lsqEntries -
1065                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1066
1067    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1068
1069    return num_free;
1070}
1071
1072template <class Impl>
1073unsigned
1074DefaultRename<Impl>::validInsts()
1075{
1076    unsigned inst_count = 0;
1077
1078    for (int i=0; i<fromDecode->size; i++) {
1079        if (!fromDecode->insts[i]->isSquashed())
1080            inst_count++;
1081    }
1082
1083    return inst_count;
1084}
1085
1086template <class Impl>
1087void
1088DefaultRename<Impl>::readStallSignals(unsigned tid)
1089{
1090    if (fromIEW->iewBlock[tid]) {
1091        stalls[tid].iew = true;
1092    }
1093
1094    if (fromIEW->iewUnblock[tid]) {
1095        assert(stalls[tid].iew);
1096        stalls[tid].iew = false;
1097    }
1098
1099    if (fromCommit->commitBlock[tid]) {
1100        stalls[tid].commit = true;
1101    }
1102
1103    if (fromCommit->commitUnblock[tid]) {
1104        assert(stalls[tid].commit);
1105        stalls[tid].commit = false;
1106    }
1107}
1108
1109template <class Impl>
1110bool
1111DefaultRename<Impl>::checkStall(unsigned tid)
1112{
1113    bool ret_val = false;
1114
1115    if (stalls[tid].iew) {
1116        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1117        ret_val = true;
1118    } else if (stalls[tid].commit) {
1119        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1120        ret_val = true;
1121    } else if (calcFreeROBEntries(tid) <= 0) {
1122        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1123        ret_val = true;
1124    } else if (calcFreeIQEntries(tid) <= 0) {
1125        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1126        ret_val = true;
1127    } else if (calcFreeLSQEntries(tid) <= 0) {
1128        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1129        ret_val = true;
1130    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1131        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1132        ret_val = true;
1133    } else if (renameStatus[tid] == SerializeStall &&
1134               (!emptyROB[tid] || instsInProgress[tid])) {
1135        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1136                "empty.\n",
1137                tid);
1138        ret_val = true;
1139    }
1140
1141    return ret_val;
1142}
1143
1144template <class Impl>
1145void
1146DefaultRename<Impl>::readFreeEntries(unsigned tid)
1147{
1148    bool updated = false;
1149    if (fromIEW->iewInfo[tid].usedIQ) {
1150        freeEntries[tid].iqEntries =
1151            fromIEW->iewInfo[tid].freeIQEntries;
1152        updated = true;
1153    }
1154
1155    if (fromIEW->iewInfo[tid].usedLSQ) {
1156        freeEntries[tid].lsqEntries =
1157            fromIEW->iewInfo[tid].freeLSQEntries;
1158        updated = true;
1159    }
1160
1161    if (fromCommit->commitInfo[tid].usedROB) {
1162        freeEntries[tid].robEntries =
1163            fromCommit->commitInfo[tid].freeROBEntries;
1164        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1165        updated = true;
1166    }
1167
1168    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1169            tid,
1170            freeEntries[tid].iqEntries,
1171            freeEntries[tid].robEntries,
1172            freeEntries[tid].lsqEntries);
1173
1174    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1175            tid, instsInProgress[tid]);
1176}
1177
1178template <class Impl>
1179bool
1180DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1181{
1182    // Check if there's a squash signal, squash if there is
1183    // Check stall signals, block if necessary.
1184    // If status was blocked
1185    //     check if stall conditions have passed
1186    //         if so then go to unblocking
1187    // If status was Squashing
1188    //     check if squashing is not high.  Switch to running this cycle.
1189    // If status was serialize stall
1190    //     check if ROB is empty and no insts are in flight to the ROB
1191
1192    readFreeEntries(tid);
1193    readStallSignals(tid);
1194
1195    if (fromCommit->commitInfo[tid].squash) {
1196        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1197                "commit.\n", tid);
1198
1199#if ISA_HAS_DELAY_SLOT
1200        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
1201#else
1202        InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
1203#endif
1204
1205        squash(squashed_seq_num, tid);
1206
1207        return true;
1208    }
1209
1210    if (fromCommit->commitInfo[tid].robSquashing) {
1211        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1212
1213        renameStatus[tid] = Squashing;
1214
1215        return true;
1216    }
1217
1218    if (checkStall(tid)) {
1219        return block(tid);
1220    }
1221
1222    if (renameStatus[tid] == Blocked) {
1223        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1224                tid);
1225
1226        renameStatus[tid] = Unblocking;
1227
1228        unblock(tid);
1229
1230        return true;
1231    }
1232
1233    if (renameStatus[tid] == Squashing) {
1234        // Switch status to running if rename isn't being told to block or
1235        // squash this cycle.
1236        DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1237                tid);
1238
1239        renameStatus[tid] = Running;
1240
1241        return false;
1242    }
1243
1244    if (renameStatus[tid] == SerializeStall) {
1245        // Stall ends once the ROB is free.
1246        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1247                "unblocking.\n", tid);
1248
1249        DynInstPtr serial_inst = serializeInst[tid];
1250
1251        renameStatus[tid] = Unblocking;
1252
1253        unblock(tid);
1254
1255        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1256                "PC %#x.\n",
1257                tid, serial_inst->seqNum, serial_inst->readPC());
1258
1259        // Put instruction into queue here.
1260        serial_inst->clearSerializeBefore();
1261
1262        if (!skidBuffer[tid].empty()) {
1263            skidBuffer[tid].push_front(serial_inst);
1264        } else {
1265            insts[tid].push_front(serial_inst);
1266        }
1267
1268        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1269                " Adding to front of list.\n", tid);
1270
1271        serializeInst[tid] = NULL;
1272
1273        return true;
1274    }
1275
1276    // If we've reached this point, we have not gotten any signals that
1277    // cause rename to change its status.  Rename remains the same as before.
1278    return false;
1279}
1280
1281template<class Impl>
1282void
1283DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1284                                   unsigned tid)
1285{
1286    if (inst_list.empty()) {
1287        // Mark a bit to say that I must serialize on the next instruction.
1288        serializeOnNextInst[tid] = true;
1289        return;
1290    }
1291
1292    // Set the next instruction as serializing.
1293    inst_list.front()->setSerializeBefore();
1294}
1295
1296template <class Impl>
1297inline void
1298DefaultRename<Impl>::incrFullStat(const FullSource &source)
1299{
1300    switch (source) {
1301      case ROB:
1302        ++renameROBFullEvents;
1303        break;
1304      case IQ:
1305        ++renameIQFullEvents;
1306        break;
1307      case LSQ:
1308        ++renameLSQFullEvents;
1309        break;
1310      default:
1311        panic("Rename full stall stat should be incremented for a reason!");
1312        break;
1313    }
1314}
1315
1316template <class Impl>
1317void
1318DefaultRename<Impl>::dumpHistory()
1319{
1320    typename std::list<RenameHistory>::iterator buf_it;
1321
1322    for (int i = 0; i < numThreads; i++) {
1323
1324        buf_it = historyBuffer[i].begin();
1325
1326        while (buf_it != historyBuffer[i].end()) {
1327            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1328                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1329                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1330
1331            buf_it++;
1332        }
1333    }
1334}
1335