rename_impl.hh revision 2863:2592e056dc5c 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <list>
32
33#include "config/full_system.hh"
34#include "cpu/o3/rename.hh"
35
36using namespace std;
37
38template <class Impl>
39DefaultRename<Impl>::DefaultRename(Params *params)
40    : iewToRenameDelay(params->iewToRenameDelay),
41      decodeToRenameDelay(params->decodeToRenameDelay),
42      commitToRenameDelay(params->commitToRenameDelay),
43      renameWidth(params->renameWidth),
44      commitWidth(params->commitWidth),
45      numThreads(params->numberOfThreads)
46{
47    _status = Inactive;
48
49    for (int i=0; i< numThreads; i++) {
50        renameStatus[i] = Idle;
51
52        freeEntries[i].iqEntries = 0;
53        freeEntries[i].lsqEntries = 0;
54        freeEntries[i].robEntries = 0;
55
56        stalls[i].iew = false;
57        stalls[i].commit = false;
58        serializeInst[i] = NULL;
59
60        instsInProgress[i] = 0;
61
62        emptyROB[i] = true;
63
64        serializeOnNextInst[i] = false;
65    }
66
67    // @todo: Make into a parameter.
68    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
69}
70
71template <class Impl>
72std::string
73DefaultRename<Impl>::name() const
74{
75    return cpu->name() + ".rename";
76}
77
78template <class Impl>
79void
80DefaultRename<Impl>::regStats()
81{
82    renameSquashCycles
83        .name(name() + ".RENAME:SquashCycles")
84        .desc("Number of cycles rename is squashing")
85        .prereq(renameSquashCycles);
86    renameIdleCycles
87        .name(name() + ".RENAME:IdleCycles")
88        .desc("Number of cycles rename is idle")
89        .prereq(renameIdleCycles);
90    renameBlockCycles
91        .name(name() + ".RENAME:BlockCycles")
92        .desc("Number of cycles rename is blocking")
93        .prereq(renameBlockCycles);
94    renameSerializeStallCycles
95        .name(name() + ".RENAME:serializeStallCycles")
96        .desc("count of cycles rename stalled for serializing inst")
97        .flags(Stats::total);
98    renameRunCycles
99        .name(name() + ".RENAME:RunCycles")
100        .desc("Number of cycles rename is running")
101        .prereq(renameIdleCycles);
102    renameUnblockCycles
103        .name(name() + ".RENAME:UnblockCycles")
104        .desc("Number of cycles rename is unblocking")
105        .prereq(renameUnblockCycles);
106    renameRenamedInsts
107        .name(name() + ".RENAME:RenamedInsts")
108        .desc("Number of instructions processed by rename")
109        .prereq(renameRenamedInsts);
110    renameSquashedInsts
111        .name(name() + ".RENAME:SquashedInsts")
112        .desc("Number of squashed instructions processed by rename")
113        .prereq(renameSquashedInsts);
114    renameROBFullEvents
115        .name(name() + ".RENAME:ROBFullEvents")
116        .desc("Number of times rename has blocked due to ROB full")
117        .prereq(renameROBFullEvents);
118    renameIQFullEvents
119        .name(name() + ".RENAME:IQFullEvents")
120        .desc("Number of times rename has blocked due to IQ full")
121        .prereq(renameIQFullEvents);
122    renameLSQFullEvents
123        .name(name() + ".RENAME:LSQFullEvents")
124        .desc("Number of times rename has blocked due to LSQ full")
125        .prereq(renameLSQFullEvents);
126    renameFullRegistersEvents
127        .name(name() + ".RENAME:FullRegisterEvents")
128        .desc("Number of times there has been no free registers")
129        .prereq(renameFullRegistersEvents);
130    renameRenamedOperands
131        .name(name() + ".RENAME:RenamedOperands")
132        .desc("Number of destination operands rename has renamed")
133        .prereq(renameRenamedOperands);
134    renameRenameLookups
135        .name(name() + ".RENAME:RenameLookups")
136        .desc("Number of register rename lookups that rename has made")
137        .prereq(renameRenameLookups);
138    renameCommittedMaps
139        .name(name() + ".RENAME:CommittedMaps")
140        .desc("Number of HB maps that are committed")
141        .prereq(renameCommittedMaps);
142    renameUndoneMaps
143        .name(name() + ".RENAME:UndoneMaps")
144        .desc("Number of HB maps that are undone due to squashing")
145        .prereq(renameUndoneMaps);
146    renamedSerializing
147        .name(name() + ".RENAME:serializingInsts")
148        .desc("count of serializing insts renamed")
149        .flags(Stats::total)
150        ;
151    renamedTempSerializing
152        .name(name() + ".RENAME:tempSerializingInsts")
153        .desc("count of temporary serializing insts renamed")
154        .flags(Stats::total)
155        ;
156    renameSkidInsts
157        .name(name() + ".RENAME:skidInsts")
158        .desc("count of insts added to the skid buffer")
159        .flags(Stats::total)
160        ;
161}
162
163template <class Impl>
164void
165DefaultRename<Impl>::setCPU(O3CPU *cpu_ptr)
166{
167    DPRINTF(Rename, "Setting CPU pointer.\n");
168    cpu = cpu_ptr;
169}
170
171template <class Impl>
172void
173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174{
175    DPRINTF(Rename, "Setting time buffer pointer.\n");
176    timeBuffer = tb_ptr;
177
178    // Setup wire to read information from time buffer, from IEW stage.
179    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181    // Setup wire to read infromation from time buffer, from commit stage.
182    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184    // Setup wire to write information to previous stages.
185    toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192    DPRINTF(Rename, "Setting rename queue pointer.\n");
193    renameQueue = rq_ptr;
194
195    // Setup wire to write information to future stages.
196    toIEW = renameQueue->getWire(0);
197}
198
199template <class Impl>
200void
201DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
202{
203    DPRINTF(Rename, "Setting decode queue pointer.\n");
204    decodeQueue = dq_ptr;
205
206    // Setup wire to get information from decode.
207    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::initStage()
213{
214    // Grab the number of free entries directly from the stages.
215    for (int tid=0; tid < numThreads; tid++) {
216        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
217        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
218        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
219        emptyROB[tid] = true;
220    }
221}
222
223template<class Impl>
224void
225DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
226{
227    DPRINTF(Rename, "Setting active threads list pointer.\n");
228    activeThreads = at_ptr;
229}
230
231
232template <class Impl>
233void
234DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
235{
236    DPRINTF(Rename, "Setting rename map pointers.\n");
237
238    for (int i=0; i<numThreads; i++) {
239        renameMap[i] = &rm_ptr[i];
240    }
241}
242
243template <class Impl>
244void
245DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
246{
247    DPRINTF(Rename, "Setting free list pointer.\n");
248    freeList = fl_ptr;
249}
250
251template<class Impl>
252void
253DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
254{
255    DPRINTF(Rename, "Setting scoreboard pointer.\n");
256    scoreboard = _scoreboard;
257}
258
259template <class Impl>
260bool
261DefaultRename<Impl>::drain()
262{
263    // Rename is ready to switch out at any time.
264    cpu->signalDrained();
265    return true;
266}
267
268template <class Impl>
269void
270DefaultRename<Impl>::switchOut()
271{
272    // Clear any state, fix up the rename map.
273    for (int i = 0; i < numThreads; i++) {
274        typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
275
276        while (!historyBuffer[i].empty()) {
277            assert(hb_it != historyBuffer[i].end());
278
279            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
280                    "number %i.\n", i, (*hb_it).instSeqNum);
281
282            // Tell the rename map to set the architected register to the
283            // previous physical register that it was renamed to.
284            renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
285
286            // Put the renamed physical register back on the free list.
287            freeList->addReg(hb_it->newPhysReg);
288
289            historyBuffer[i].erase(hb_it++);
290        }
291        insts[i].clear();
292        skidBuffer[i].clear();
293    }
294}
295
296template <class Impl>
297void
298DefaultRename<Impl>::takeOverFrom()
299{
300    _status = Inactive;
301    initStage();
302
303    // Reset all state prior to taking over from the other CPU.
304    for (int i=0; i< numThreads; i++) {
305        renameStatus[i] = Idle;
306
307        stalls[i].iew = false;
308        stalls[i].commit = false;
309        serializeInst[i] = NULL;
310
311        instsInProgress[i] = 0;
312
313        emptyROB[i] = true;
314
315        serializeOnNextInst[i] = false;
316    }
317}
318
319template <class Impl>
320void
321DefaultRename<Impl>::squash(unsigned tid)
322{
323    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
324
325    // Clear the stall signal if rename was blocked or unblocking before.
326    // If it still needs to block, the blocking should happen the next
327    // cycle and there should be space to hold everything due to the squash.
328    if (renameStatus[tid] == Blocked ||
329        renameStatus[tid] == Unblocking ||
330        renameStatus[tid] == SerializeStall) {
331
332        toDecode->renameUnblock[tid] = 1;
333
334        serializeInst[tid] = NULL;
335    }
336
337    // Set the status to Squashing.
338    renameStatus[tid] = Squashing;
339
340    // Squash any instructions from decode.
341    unsigned squashCount = 0;
342
343    for (int i=0; i<fromDecode->size; i++) {
344        if (fromDecode->insts[i]->threadNumber == tid) {
345            fromDecode->insts[i]->setSquashed();
346            wroteToTimeBuffer = true;
347            squashCount++;
348        }
349    }
350
351    insts[tid].clear();
352
353    // Clear the skid buffer in case it has any data in it.
354    skidBuffer[tid].clear();
355
356    doSquash(tid);
357}
358
359template <class Impl>
360void
361DefaultRename<Impl>::tick()
362{
363    wroteToTimeBuffer = false;
364
365    blockThisCycle = false;
366
367    bool status_change = false;
368
369    toIEWIndex = 0;
370
371    sortInsts();
372
373    list<unsigned>::iterator threads = (*activeThreads).begin();
374
375    // Check stall and squash signals.
376    while (threads != (*activeThreads).end()) {
377        unsigned tid = *threads++;
378
379        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
380
381        status_change = checkSignalsAndUpdate(tid) || status_change;
382
383        rename(status_change, tid);
384    }
385
386    if (status_change) {
387        updateStatus();
388    }
389
390    if (wroteToTimeBuffer) {
391        DPRINTF(Activity, "Activity this cycle.\n");
392        cpu->activityThisCycle();
393    }
394
395    threads = (*activeThreads).begin();
396
397    while (threads != (*activeThreads).end()) {
398        unsigned tid = *threads++;
399
400        // If we committed this cycle then doneSeqNum will be > 0
401        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
402            !fromCommit->commitInfo[tid].squash &&
403            renameStatus[tid] != Squashing) {
404
405            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
406                                  tid);
407        }
408    }
409
410    // @todo: make into updateProgress function
411    for (int tid=0; tid < numThreads; tid++) {
412        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
413
414        assert(instsInProgress[tid] >=0);
415    }
416
417}
418
419template<class Impl>
420void
421DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
422{
423    // If status is Running or idle,
424    //     call renameInsts()
425    // If status is Unblocking,
426    //     buffer any instructions coming from decode
427    //     continue trying to empty skid buffer
428    //     check if stall conditions have passed
429
430    if (renameStatus[tid] == Blocked) {
431        ++renameBlockCycles;
432    } else if (renameStatus[tid] == Squashing) {
433        ++renameSquashCycles;
434    } else if (renameStatus[tid] == SerializeStall) {
435        ++renameSerializeStallCycles;
436    }
437
438    if (renameStatus[tid] == Running ||
439        renameStatus[tid] == Idle) {
440        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
441                "stage.\n", tid);
442
443        renameInsts(tid);
444    } else if (renameStatus[tid] == Unblocking) {
445        renameInsts(tid);
446
447        if (validInsts()) {
448            // Add the current inputs to the skid buffer so they can be
449            // reprocessed when this stage unblocks.
450            skidInsert(tid);
451        }
452
453        // If we switched over to blocking, then there's a potential for
454        // an overall status change.
455        status_change = unblock(tid) || status_change || blockThisCycle;
456    }
457}
458
459template <class Impl>
460void
461DefaultRename<Impl>::renameInsts(unsigned tid)
462{
463    // Instructions can be either in the skid buffer or the queue of
464    // instructions coming from decode, depending on the status.
465    int insts_available = renameStatus[tid] == Unblocking ?
466        skidBuffer[tid].size() : insts[tid].size();
467
468    // Check the decode queue to see if instructions are available.
469    // If there are no available instructions to rename, then do nothing.
470    if (insts_available == 0) {
471        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
472                tid);
473        // Should I change status to idle?
474        ++renameIdleCycles;
475        return;
476    } else if (renameStatus[tid] == Unblocking) {
477        ++renameUnblockCycles;
478    } else if (renameStatus[tid] == Running) {
479        ++renameRunCycles;
480    }
481
482    DynInstPtr inst;
483
484    // Will have to do a different calculation for the number of free
485    // entries.
486    int free_rob_entries = calcFreeROBEntries(tid);
487    int free_iq_entries  = calcFreeIQEntries(tid);
488    int free_lsq_entries = calcFreeLSQEntries(tid);
489    int min_free_entries = free_rob_entries;
490
491    FullSource source = ROB;
492
493    if (free_iq_entries < min_free_entries) {
494        min_free_entries = free_iq_entries;
495        source = IQ;
496    }
497
498    if (free_lsq_entries < min_free_entries) {
499        min_free_entries = free_lsq_entries;
500        source = LSQ;
501    }
502
503    // Check if there's any space left.
504    if (min_free_entries <= 0) {
505        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
506                "entries.\n"
507                "ROB has %i free entries.\n"
508                "IQ has %i free entries.\n"
509                "LSQ has %i free entries.\n",
510                tid,
511                free_rob_entries,
512                free_iq_entries,
513                free_lsq_entries);
514
515        blockThisCycle = true;
516
517        block(tid);
518
519        incrFullStat(source);
520
521        return;
522    } else if (min_free_entries < insts_available) {
523        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
524                "%i insts available, but only %i insts can be "
525                "renamed due to ROB/IQ/LSQ limits.\n",
526                tid, insts_available, min_free_entries);
527
528        insts_available = min_free_entries;
529
530        blockThisCycle = true;
531
532        incrFullStat(source);
533    }
534
535    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
536        skidBuffer[tid] : insts[tid];
537
538    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
539            "send iew.\n", tid, insts_available);
540
541    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
542            "dispatched to IQ last cycle.\n",
543            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
544
545    // Handle serializing the next instruction if necessary.
546    if (serializeOnNextInst[tid]) {
547        if (emptyROB[tid] && instsInProgress[tid] == 0) {
548            // ROB already empty; no need to serialize.
549            serializeOnNextInst[tid] = false;
550        } else if (!insts_to_rename.empty()) {
551            insts_to_rename.front()->setSerializeBefore();
552        }
553    }
554
555    int renamed_insts = 0;
556
557    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
558        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
559
560        assert(!insts_to_rename.empty());
561
562        inst = insts_to_rename.front();
563
564        insts_to_rename.pop_front();
565
566        if (renameStatus[tid] == Unblocking) {
567            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
568                    "skidBuffer\n",
569                    tid, inst->seqNum, inst->readPC());
570        }
571
572        if (inst->isSquashed()) {
573            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
574                    "squashed, skipping.\n",
575                    tid, inst->seqNum, inst->threadNumber,inst->readPC());
576
577            ++renameSquashedInsts;
578
579            // Decrement how many instructions are available.
580            --insts_available;
581
582            continue;
583        }
584
585        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
586                "PC %#x.\n",
587                tid, inst->seqNum, inst->readPC());
588
589        // Handle serializeAfter/serializeBefore instructions.
590        // serializeAfter marks the next instruction as serializeBefore.
591        // serializeBefore makes the instruction wait in rename until the ROB
592        // is empty.
593
594        // In this model, IPR accesses are serialize before
595        // instructions, and store conditionals are serialize after
596        // instructions.  This is mainly due to lack of support for
597        // out-of-order operations of either of those classes of
598        // instructions.
599        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
600            !inst->isSerializeHandled()) {
601            DPRINTF(Rename, "Serialize before instruction encountered.\n");
602
603            if (!inst->isTempSerializeBefore()) {
604                renamedSerializing++;
605                inst->setSerializeHandled();
606            } else {
607                renamedTempSerializing++;
608            }
609
610            // Change status over to SerializeStall so that other stages know
611            // what this is blocked on.
612            renameStatus[tid] = SerializeStall;
613
614            serializeInst[tid] = inst;
615
616            blockThisCycle = true;
617
618            break;
619        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
620                   !inst->isSerializeHandled()) {
621            DPRINTF(Rename, "Serialize after instruction encountered.\n");
622
623            renamedSerializing++;
624
625            inst->setSerializeHandled();
626
627            serializeAfter(insts_to_rename, tid);
628        }
629
630        // Check here to make sure there are enough destination registers
631        // to rename to.  Otherwise block.
632        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
633            DPRINTF(Rename, "Blocking due to lack of free "
634                    "physical registers to rename to.\n");
635            blockThisCycle = true;
636
637            ++renameFullRegistersEvents;
638
639            break;
640        }
641
642        renameSrcRegs(inst, inst->threadNumber);
643
644        renameDestRegs(inst, inst->threadNumber);
645
646        ++renamed_insts;
647
648        // Put instruction in rename queue.
649        toIEW->insts[toIEWIndex] = inst;
650        ++(toIEW->size);
651
652        // Increment which instruction we're on.
653        ++toIEWIndex;
654
655        // Decrement how many instructions are available.
656        --insts_available;
657    }
658
659    instsInProgress[tid] += renamed_insts;
660    renameRenamedInsts += renamed_insts;
661
662    // If we wrote to the time buffer, record this.
663    if (toIEWIndex) {
664        wroteToTimeBuffer = true;
665    }
666
667    // Check if there's any instructions left that haven't yet been renamed.
668    // If so then block.
669    if (insts_available) {
670        blockThisCycle = true;
671    }
672
673    if (blockThisCycle) {
674        block(tid);
675        toDecode->renameUnblock[tid] = false;
676    }
677}
678
679template<class Impl>
680void
681DefaultRename<Impl>::skidInsert(unsigned tid)
682{
683    DynInstPtr inst = NULL;
684
685    while (!insts[tid].empty()) {
686        inst = insts[tid].front();
687
688        insts[tid].pop_front();
689
690        assert(tid == inst->threadNumber);
691
692        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
693                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
694
695        ++renameSkidInsts;
696
697        skidBuffer[tid].push_back(inst);
698    }
699
700    if (skidBuffer[tid].size() > skidBufferMax)
701        panic("Skidbuffer Exceeded Max Size");
702}
703
704template <class Impl>
705void
706DefaultRename<Impl>::sortInsts()
707{
708    int insts_from_decode = fromDecode->size;
709#ifdef DEBUG
710    for (int i=0; i < numThreads; i++)
711        assert(insts[i].empty());
712#endif
713    for (int i = 0; i < insts_from_decode; ++i) {
714        DynInstPtr inst = fromDecode->insts[i];
715        insts[inst->threadNumber].push_back(inst);
716    }
717}
718
719template<class Impl>
720bool
721DefaultRename<Impl>::skidsEmpty()
722{
723    list<unsigned>::iterator threads = (*activeThreads).begin();
724
725    while (threads != (*activeThreads).end()) {
726        if (!skidBuffer[*threads++].empty())
727            return false;
728    }
729
730    return true;
731}
732
733template<class Impl>
734void
735DefaultRename<Impl>::updateStatus()
736{
737    bool any_unblocking = false;
738
739    list<unsigned>::iterator threads = (*activeThreads).begin();
740
741    threads = (*activeThreads).begin();
742
743    while (threads != (*activeThreads).end()) {
744        unsigned tid = *threads++;
745
746        if (renameStatus[tid] == Unblocking) {
747            any_unblocking = true;
748            break;
749        }
750    }
751
752    // Rename will have activity if it's unblocking.
753    if (any_unblocking) {
754        if (_status == Inactive) {
755            _status = Active;
756
757            DPRINTF(Activity, "Activating stage.\n");
758
759            cpu->activateStage(O3CPU::RenameIdx);
760        }
761    } else {
762        // If it's not unblocking, then rename will not have any internal
763        // activity.  Switch it to inactive.
764        if (_status == Active) {
765            _status = Inactive;
766            DPRINTF(Activity, "Deactivating stage.\n");
767
768            cpu->deactivateStage(O3CPU::RenameIdx);
769        }
770    }
771}
772
773template <class Impl>
774bool
775DefaultRename<Impl>::block(unsigned tid)
776{
777    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
778
779    // Add the current inputs onto the skid buffer, so they can be
780    // reprocessed when this stage unblocks.
781    skidInsert(tid);
782
783    // Only signal backwards to block if the previous stages do not think
784    // rename is already blocked.
785    if (renameStatus[tid] != Blocked) {
786        if (renameStatus[tid] != Unblocking) {
787            toDecode->renameBlock[tid] = true;
788            toDecode->renameUnblock[tid] = false;
789            wroteToTimeBuffer = true;
790        }
791
792        // Rename can not go from SerializeStall to Blocked, otherwise
793        // it would not know to complete the serialize stall.
794        if (renameStatus[tid] != SerializeStall) {
795            // Set status to Blocked.
796            renameStatus[tid] = Blocked;
797            return true;
798        }
799    }
800
801    return false;
802}
803
804template <class Impl>
805bool
806DefaultRename<Impl>::unblock(unsigned tid)
807{
808    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
809
810    // Rename is done unblocking if the skid buffer is empty.
811    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
812
813        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
814
815        toDecode->renameUnblock[tid] = true;
816        wroteToTimeBuffer = true;
817
818        renameStatus[tid] = Running;
819        return true;
820    }
821
822    return false;
823}
824
825template <class Impl>
826void
827DefaultRename<Impl>::doSquash(unsigned tid)
828{
829    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
830
831    InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
832
833    // After a syscall squashes everything, the history buffer may be empty
834    // but the ROB may still be squashing instructions.
835    if (historyBuffer[tid].empty()) {
836        return;
837    }
838
839    // Go through the most recent instructions, undoing the mappings
840    // they did and freeing up the registers.
841    while (!historyBuffer[tid].empty() &&
842           (*hb_it).instSeqNum > squashed_seq_num) {
843        assert(hb_it != historyBuffer[tid].end());
844
845        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
846                "number %i.\n", tid, (*hb_it).instSeqNum);
847
848        // Tell the rename map to set the architected register to the
849        // previous physical register that it was renamed to.
850        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
851
852        // Put the renamed physical register back on the free list.
853        freeList->addReg(hb_it->newPhysReg);
854
855        historyBuffer[tid].erase(hb_it++);
856
857        ++renameUndoneMaps;
858    }
859}
860
861template<class Impl>
862void
863DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
864{
865    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
866            "history buffer %u (size=%i), until [sn:%lli].\n",
867            tid, tid, historyBuffer[tid].size(), inst_seq_num);
868
869    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
870
871    --hb_it;
872
873    if (historyBuffer[tid].empty()) {
874        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
875        return;
876    } else if (hb_it->instSeqNum > inst_seq_num) {
877        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
878                "that a syscall happened recently.\n", tid);
879        return;
880    }
881
882    // Commit all the renames up until (and including) the committed sequence
883    // number. Some or even all of the committed instructions may not have
884    // rename histories if they did not have destination registers that were
885    // renamed.
886    while (!historyBuffer[tid].empty() &&
887           hb_it != historyBuffer[tid].end() &&
888           (*hb_it).instSeqNum <= inst_seq_num) {
889
890        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
891                "[sn:%lli].\n",
892                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
893
894        freeList->addReg((*hb_it).prevPhysReg);
895        ++renameCommittedMaps;
896
897        historyBuffer[tid].erase(hb_it--);
898    }
899}
900
901template <class Impl>
902inline void
903DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
904{
905    assert(renameMap[tid] != 0);
906
907    unsigned num_src_regs = inst->numSrcRegs();
908
909    // Get the architectual register numbers from the source and
910    // destination operands, and redirect them to the right register.
911    // Will need to mark dependencies though.
912    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
913        RegIndex src_reg = inst->srcRegIdx(src_idx);
914
915        // Look up the source registers to get the phys. register they've
916        // been renamed to, and set the sources to those registers.
917        PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
918
919        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
920                "physical reg %i.\n", tid, (int)src_reg,
921                (int)renamed_reg);
922
923        inst->renameSrcReg(src_idx, renamed_reg);
924
925        // See if the register is ready or not.
926        if (scoreboard->getReg(renamed_reg) == true) {
927            DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
928
929            inst->markSrcRegReady(src_idx);
930        }
931
932        ++renameRenameLookups;
933    }
934}
935
936template <class Impl>
937inline void
938DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
939{
940    typename RenameMap::RenameInfo rename_result;
941
942    unsigned num_dest_regs = inst->numDestRegs();
943
944    // Rename the destination registers.
945    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
946        RegIndex dest_reg = inst->destRegIdx(dest_idx);
947
948        // Get the physical register that the destination will be
949        // renamed to.
950        rename_result = renameMap[tid]->rename(dest_reg);
951
952        //Mark Scoreboard entry as not ready
953        scoreboard->unsetReg(rename_result.first);
954
955        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
956                "reg %i.\n", tid, (int)dest_reg,
957                (int)rename_result.first);
958
959        // Record the rename information so that a history can be kept.
960        RenameHistory hb_entry(inst->seqNum, dest_reg,
961                               rename_result.first,
962                               rename_result.second);
963
964        historyBuffer[tid].push_front(hb_entry);
965
966        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
967                "[sn:%lli].\n",tid,
968                (*historyBuffer[tid].begin()).instSeqNum);
969
970        // Tell the instruction to rename the appropriate destination
971        // register (dest_idx) to the new physical register
972        // (rename_result.first), and record the previous physical
973        // register that the same logical register was renamed to
974        // (rename_result.second).
975        inst->renameDestReg(dest_idx,
976                            rename_result.first,
977                            rename_result.second);
978
979        ++renameRenamedOperands;
980    }
981}
982
983template <class Impl>
984inline int
985DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
986{
987    int num_free = freeEntries[tid].robEntries -
988                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
989
990    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
991
992    return num_free;
993}
994
995template <class Impl>
996inline int
997DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
998{
999    int num_free = freeEntries[tid].iqEntries -
1000                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1001
1002    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1003
1004    return num_free;
1005}
1006
1007template <class Impl>
1008inline int
1009DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1010{
1011    int num_free = freeEntries[tid].lsqEntries -
1012                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1013
1014    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1015
1016    return num_free;
1017}
1018
1019template <class Impl>
1020unsigned
1021DefaultRename<Impl>::validInsts()
1022{
1023    unsigned inst_count = 0;
1024
1025    for (int i=0; i<fromDecode->size; i++) {
1026        if (!fromDecode->insts[i]->isSquashed())
1027            inst_count++;
1028    }
1029
1030    return inst_count;
1031}
1032
1033template <class Impl>
1034void
1035DefaultRename<Impl>::readStallSignals(unsigned tid)
1036{
1037    if (fromIEW->iewBlock[tid]) {
1038        stalls[tid].iew = true;
1039    }
1040
1041    if (fromIEW->iewUnblock[tid]) {
1042        assert(stalls[tid].iew);
1043        stalls[tid].iew = false;
1044    }
1045
1046    if (fromCommit->commitBlock[tid]) {
1047        stalls[tid].commit = true;
1048    }
1049
1050    if (fromCommit->commitUnblock[tid]) {
1051        assert(stalls[tid].commit);
1052        stalls[tid].commit = false;
1053    }
1054}
1055
1056template <class Impl>
1057bool
1058DefaultRename<Impl>::checkStall(unsigned tid)
1059{
1060    bool ret_val = false;
1061
1062    if (stalls[tid].iew) {
1063        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1064        ret_val = true;
1065    } else if (stalls[tid].commit) {
1066        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1067        ret_val = true;
1068    } else if (calcFreeROBEntries(tid) <= 0) {
1069        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1070        ret_val = true;
1071    } else if (calcFreeIQEntries(tid) <= 0) {
1072        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1073        ret_val = true;
1074    } else if (calcFreeLSQEntries(tid) <= 0) {
1075        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1076        ret_val = true;
1077    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1078        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1079        ret_val = true;
1080    } else if (renameStatus[tid] == SerializeStall &&
1081               (!emptyROB[tid] || instsInProgress[tid])) {
1082        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1083                "empty.\n",
1084                tid);
1085        ret_val = true;
1086    }
1087
1088    return ret_val;
1089}
1090
1091template <class Impl>
1092void
1093DefaultRename<Impl>::readFreeEntries(unsigned tid)
1094{
1095    bool updated = false;
1096    if (fromIEW->iewInfo[tid].usedIQ) {
1097        freeEntries[tid].iqEntries =
1098            fromIEW->iewInfo[tid].freeIQEntries;
1099        updated = true;
1100    }
1101
1102    if (fromIEW->iewInfo[tid].usedLSQ) {
1103        freeEntries[tid].lsqEntries =
1104            fromIEW->iewInfo[tid].freeLSQEntries;
1105        updated = true;
1106    }
1107
1108    if (fromCommit->commitInfo[tid].usedROB) {
1109        freeEntries[tid].robEntries =
1110            fromCommit->commitInfo[tid].freeROBEntries;
1111        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1112        updated = true;
1113    }
1114
1115    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1116            tid,
1117            freeEntries[tid].iqEntries,
1118            freeEntries[tid].robEntries,
1119            freeEntries[tid].lsqEntries);
1120
1121    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1122            tid, instsInProgress[tid]);
1123}
1124
1125template <class Impl>
1126bool
1127DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1128{
1129    // Check if there's a squash signal, squash if there is
1130    // Check stall signals, block if necessary.
1131    // If status was blocked
1132    //     check if stall conditions have passed
1133    //         if so then go to unblocking
1134    // If status was Squashing
1135    //     check if squashing is not high.  Switch to running this cycle.
1136    // If status was serialize stall
1137    //     check if ROB is empty and no insts are in flight to the ROB
1138
1139    readFreeEntries(tid);
1140    readStallSignals(tid);
1141
1142    if (fromCommit->commitInfo[tid].squash) {
1143        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1144                "commit.\n", tid);
1145
1146        squash(tid);
1147
1148        return true;
1149    }
1150
1151    if (fromCommit->commitInfo[tid].robSquashing) {
1152        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1153
1154        renameStatus[tid] = Squashing;
1155
1156        return true;
1157    }
1158
1159    if (checkStall(tid)) {
1160        return block(tid);
1161    }
1162
1163    if (renameStatus[tid] == Blocked) {
1164        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1165                tid);
1166
1167        renameStatus[tid] = Unblocking;
1168
1169        unblock(tid);
1170
1171        return true;
1172    }
1173
1174    if (renameStatus[tid] == Squashing) {
1175        // Switch status to running if rename isn't being told to block or
1176        // squash this cycle.
1177        DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1178                tid);
1179
1180        renameStatus[tid] = Running;
1181
1182        return false;
1183    }
1184
1185    if (renameStatus[tid] == SerializeStall) {
1186        // Stall ends once the ROB is free.
1187        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1188                "unblocking.\n", tid);
1189
1190        DynInstPtr serial_inst = serializeInst[tid];
1191
1192        renameStatus[tid] = Unblocking;
1193
1194        unblock(tid);
1195
1196        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1197                "PC %#x.\n",
1198                tid, serial_inst->seqNum, serial_inst->readPC());
1199
1200        // Put instruction into queue here.
1201        serial_inst->clearSerializeBefore();
1202
1203        if (!skidBuffer[tid].empty()) {
1204            skidBuffer[tid].push_front(serial_inst);
1205        } else {
1206            insts[tid].push_front(serial_inst);
1207        }
1208
1209        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1210                " Adding to front of list.\n", tid);
1211
1212        serializeInst[tid] = NULL;
1213
1214        return true;
1215    }
1216
1217    // If we've reached this point, we have not gotten any signals that
1218    // cause rename to change its status.  Rename remains the same as before.
1219    return false;
1220}
1221
1222template<class Impl>
1223void
1224DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1225                                   unsigned tid)
1226{
1227    if (inst_list.empty()) {
1228        // Mark a bit to say that I must serialize on the next instruction.
1229        serializeOnNextInst[tid] = true;
1230        return;
1231    }
1232
1233    // Set the next instruction as serializing.
1234    inst_list.front()->setSerializeBefore();
1235}
1236
1237template <class Impl>
1238inline void
1239DefaultRename<Impl>::incrFullStat(const FullSource &source)
1240{
1241    switch (source) {
1242      case ROB:
1243        ++renameROBFullEvents;
1244        break;
1245      case IQ:
1246        ++renameIQFullEvents;
1247        break;
1248      case LSQ:
1249        ++renameLSQFullEvents;
1250        break;
1251      default:
1252        panic("Rename full stall stat should be incremented for a reason!");
1253        break;
1254    }
1255}
1256
1257template <class Impl>
1258void
1259DefaultRename<Impl>::dumpHistory()
1260{
1261    typename list<RenameHistory>::iterator buf_it;
1262
1263    for (int i = 0; i < numThreads; i++) {
1264
1265        buf_it = historyBuffer[i].begin();
1266
1267        while (buf_it != historyBuffer[i].end()) {
1268            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1269                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1270                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1271
1272            buf_it++;
1273        }
1274    }
1275}
1276