rename_impl.hh revision 2674:6d4afef73a20 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <list>
32
33#include "config/full_system.hh"
34#include "cpu/o3/rename.hh"
35
36using namespace std;
37
38template <class Impl>
39DefaultRename<Impl>::DefaultRename(Params *params)
40    : iewToRenameDelay(params->iewToRenameDelay),
41      decodeToRenameDelay(params->decodeToRenameDelay),
42      commitToRenameDelay(params->commitToRenameDelay),
43      renameWidth(params->renameWidth),
44      commitWidth(params->commitWidth),
45      numThreads(params->numberOfThreads)
46{
47    _status = Inactive;
48
49    for (int i=0; i< numThreads; i++) {
50        renameStatus[i] = Idle;
51
52        freeEntries[i].iqEntries = 0;
53        freeEntries[i].lsqEntries = 0;
54        freeEntries[i].robEntries = 0;
55
56        stalls[i].iew = false;
57        stalls[i].commit = false;
58        serializeInst[i] = NULL;
59
60        instsInProgress[i] = 0;
61
62        emptyROB[i] = true;
63
64        serializeOnNextInst[i] = false;
65    }
66
67    // @todo: Make into a parameter.
68    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
69}
70
71template <class Impl>
72std::string
73DefaultRename<Impl>::name() const
74{
75    return cpu->name() + ".rename";
76}
77
78template <class Impl>
79void
80DefaultRename<Impl>::regStats()
81{
82    renameSquashCycles
83        .name(name() + ".RENAME:SquashCycles")
84        .desc("Number of cycles rename is squashing")
85        .prereq(renameSquashCycles);
86    renameIdleCycles
87        .name(name() + ".RENAME:IdleCycles")
88        .desc("Number of cycles rename is idle")
89        .prereq(renameIdleCycles);
90    renameBlockCycles
91        .name(name() + ".RENAME:BlockCycles")
92        .desc("Number of cycles rename is blocking")
93        .prereq(renameBlockCycles);
94    renameSerializeStallCycles
95        .name(name() + ".RENAME:serializeStallCycles")
96        .desc("count of cycles rename stalled for serializing inst")
97        .flags(Stats::total);
98    renameRunCycles
99        .name(name() + ".RENAME:RunCycles")
100        .desc("Number of cycles rename is running")
101        .prereq(renameIdleCycles);
102    renameUnblockCycles
103        .name(name() + ".RENAME:UnblockCycles")
104        .desc("Number of cycles rename is unblocking")
105        .prereq(renameUnblockCycles);
106    renameRenamedInsts
107        .name(name() + ".RENAME:RenamedInsts")
108        .desc("Number of instructions processed by rename")
109        .prereq(renameRenamedInsts);
110    renameSquashedInsts
111        .name(name() + ".RENAME:SquashedInsts")
112        .desc("Number of squashed instructions processed by rename")
113        .prereq(renameSquashedInsts);
114    renameROBFullEvents
115        .name(name() + ".RENAME:ROBFullEvents")
116        .desc("Number of times rename has blocked due to ROB full")
117        .prereq(renameROBFullEvents);
118    renameIQFullEvents
119        .name(name() + ".RENAME:IQFullEvents")
120        .desc("Number of times rename has blocked due to IQ full")
121        .prereq(renameIQFullEvents);
122    renameLSQFullEvents
123        .name(name() + ".RENAME:LSQFullEvents")
124        .desc("Number of times rename has blocked due to LSQ full")
125        .prereq(renameLSQFullEvents);
126    renameFullRegistersEvents
127        .name(name() + ".RENAME:FullRegisterEvents")
128        .desc("Number of times there has been no free registers")
129        .prereq(renameFullRegistersEvents);
130    renameRenamedOperands
131        .name(name() + ".RENAME:RenamedOperands")
132        .desc("Number of destination operands rename has renamed")
133        .prereq(renameRenamedOperands);
134    renameRenameLookups
135        .name(name() + ".RENAME:RenameLookups")
136        .desc("Number of register rename lookups that rename has made")
137        .prereq(renameRenameLookups);
138    renameCommittedMaps
139        .name(name() + ".RENAME:CommittedMaps")
140        .desc("Number of HB maps that are committed")
141        .prereq(renameCommittedMaps);
142    renameUndoneMaps
143        .name(name() + ".RENAME:UndoneMaps")
144        .desc("Number of HB maps that are undone due to squashing")
145        .prereq(renameUndoneMaps);
146    renamedSerializing
147        .name(name() + ".RENAME:serializingInsts")
148        .desc("count of serializing insts renamed")
149        .flags(Stats::total)
150        ;
151    renamedTempSerializing
152        .name(name() + ".RENAME:tempSerializingInsts")
153        .desc("count of temporary serializing insts renamed")
154        .flags(Stats::total)
155        ;
156    renameSkidInsts
157        .name(name() + ".RENAME:skidInsts")
158        .desc("count of insts added to the skid buffer")
159        .flags(Stats::total)
160        ;
161}
162
163template <class Impl>
164void
165DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr)
166{
167    DPRINTF(Rename, "Setting CPU pointer.\n");
168    cpu = cpu_ptr;
169}
170
171template <class Impl>
172void
173DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
174{
175    DPRINTF(Rename, "Setting time buffer pointer.\n");
176    timeBuffer = tb_ptr;
177
178    // Setup wire to read information from time buffer, from IEW stage.
179    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
180
181    // Setup wire to read infromation from time buffer, from commit stage.
182    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
183
184    // Setup wire to write information to previous stages.
185    toDecode = timeBuffer->getWire(0);
186}
187
188template <class Impl>
189void
190DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
191{
192    DPRINTF(Rename, "Setting rename queue pointer.\n");
193    renameQueue = rq_ptr;
194
195    // Setup wire to write information to future stages.
196    toIEW = renameQueue->getWire(0);
197}
198
199template <class Impl>
200void
201DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
202{
203    DPRINTF(Rename, "Setting decode queue pointer.\n");
204    decodeQueue = dq_ptr;
205
206    // Setup wire to get information from decode.
207    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
208}
209
210template <class Impl>
211void
212DefaultRename<Impl>::initStage()
213{
214    // Grab the number of free entries directly from the stages.
215    for (int tid=0; tid < numThreads; tid++) {
216        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
217        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
218        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
219        emptyROB[tid] = true;
220    }
221}
222
223template<class Impl>
224void
225DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
226{
227    DPRINTF(Rename, "Setting active threads list pointer.\n");
228    activeThreads = at_ptr;
229}
230
231
232template <class Impl>
233void
234DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
235{
236    DPRINTF(Rename, "Setting rename map pointers.\n");
237
238    for (int i=0; i<numThreads; i++) {
239        renameMap[i] = &rm_ptr[i];
240    }
241}
242
243template <class Impl>
244void
245DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
246{
247    DPRINTF(Rename, "Setting free list pointer.\n");
248    freeList = fl_ptr;
249}
250
251template<class Impl>
252void
253DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
254{
255    DPRINTF(Rename, "Setting scoreboard pointer.\n");
256    scoreboard = _scoreboard;
257}
258
259template <class Impl>
260void
261DefaultRename<Impl>::switchOut()
262{
263    // Rename is ready to switch out at any time.
264    cpu->signalSwitched();
265}
266
267template <class Impl>
268void
269DefaultRename<Impl>::doSwitchOut()
270{
271    // Clear any state, fix up the rename map.
272    for (int i = 0; i < numThreads; i++) {
273        typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
274
275        while (!historyBuffer[i].empty()) {
276            assert(hb_it != historyBuffer[i].end());
277
278            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
279                    "number %i.\n", i, (*hb_it).instSeqNum);
280
281            // Tell the rename map to set the architected register to the
282            // previous physical register that it was renamed to.
283            renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
284
285            // Put the renamed physical register back on the free list.
286            freeList->addReg(hb_it->newPhysReg);
287
288            historyBuffer[i].erase(hb_it++);
289        }
290        insts[i].clear();
291        skidBuffer[i].clear();
292    }
293}
294
295template <class Impl>
296void
297DefaultRename<Impl>::takeOverFrom()
298{
299    _status = Inactive;
300    initStage();
301
302    // Reset all state prior to taking over from the other CPU.
303    for (int i=0; i< numThreads; i++) {
304        renameStatus[i] = Idle;
305
306        stalls[i].iew = false;
307        stalls[i].commit = false;
308        serializeInst[i] = NULL;
309
310        instsInProgress[i] = 0;
311
312        emptyROB[i] = true;
313
314        serializeOnNextInst[i] = false;
315    }
316}
317
318template <class Impl>
319void
320DefaultRename<Impl>::squash(unsigned tid)
321{
322    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
323
324    // Clear the stall signal if rename was blocked or unblocking before.
325    // If it still needs to block, the blocking should happen the next
326    // cycle and there should be space to hold everything due to the squash.
327    if (renameStatus[tid] == Blocked ||
328        renameStatus[tid] == Unblocking ||
329        renameStatus[tid] == SerializeStall) {
330#if 0
331        // In syscall emulation, we can have both a block and a squash due
332        // to a syscall in the same cycle.  This would cause both signals to
333        // be high.  This shouldn't happen in full system.
334        if (toDecode->renameBlock[tid]) {
335            toDecode->renameBlock[tid] = 0;
336        } else {
337            toDecode->renameUnblock[tid] = 1;
338        }
339#else
340        toDecode->renameUnblock[tid] = 1;
341#endif
342        serializeInst[tid] = NULL;
343    }
344
345    // Set the status to Squashing.
346    renameStatus[tid] = Squashing;
347
348    // Squash any instructions from decode.
349    unsigned squashCount = 0;
350
351    for (int i=0; i<fromDecode->size; i++) {
352        if (fromDecode->insts[i]->threadNumber == tid) {
353            fromDecode->insts[i]->squashed = true;
354            wroteToTimeBuffer = true;
355            squashCount++;
356        }
357    }
358
359    insts[tid].clear();
360
361    // Clear the skid buffer in case it has any data in it.
362    skidBuffer[tid].clear();
363
364    doSquash(tid);
365}
366
367template <class Impl>
368void
369DefaultRename<Impl>::tick()
370{
371    wroteToTimeBuffer = false;
372
373    blockThisCycle = false;
374
375    bool status_change = false;
376
377    toIEWIndex = 0;
378
379    sortInsts();
380
381    list<unsigned>::iterator threads = (*activeThreads).begin();
382
383    // Check stall and squash signals.
384    while (threads != (*activeThreads).end()) {
385        unsigned tid = *threads++;
386
387        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
388
389        status_change = checkSignalsAndUpdate(tid) || status_change;
390
391        rename(status_change, tid);
392    }
393
394    if (status_change) {
395        updateStatus();
396    }
397
398    if (wroteToTimeBuffer) {
399        DPRINTF(Activity, "Activity this cycle.\n");
400        cpu->activityThisCycle();
401    }
402
403    threads = (*activeThreads).begin();
404
405    while (threads != (*activeThreads).end()) {
406        unsigned tid = *threads++;
407
408        // If we committed this cycle then doneSeqNum will be > 0
409        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
410            !fromCommit->commitInfo[tid].squash &&
411            renameStatus[tid] != Squashing) {
412
413            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
414                                  tid);
415        }
416    }
417
418    // @todo: make into updateProgress function
419    for (int tid=0; tid < numThreads; tid++) {
420        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
421
422        assert(instsInProgress[tid] >=0);
423    }
424
425}
426
427template<class Impl>
428void
429DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
430{
431    // If status is Running or idle,
432    //     call renameInsts()
433    // If status is Unblocking,
434    //     buffer any instructions coming from decode
435    //     continue trying to empty skid buffer
436    //     check if stall conditions have passed
437
438    if (renameStatus[tid] == Blocked) {
439        ++renameBlockCycles;
440    } else if (renameStatus[tid] == Squashing) {
441        ++renameSquashCycles;
442    } else if (renameStatus[tid] == SerializeStall) {
443        ++renameSerializeStallCycles;
444    }
445
446    if (renameStatus[tid] == Running ||
447        renameStatus[tid] == Idle) {
448        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
449                "stage.\n", tid);
450
451        renameInsts(tid);
452    } else if (renameStatus[tid] == Unblocking) {
453        renameInsts(tid);
454
455        if (validInsts()) {
456            // Add the current inputs to the skid buffer so they can be
457            // reprocessed when this stage unblocks.
458            skidInsert(tid);
459        }
460
461        // If we switched over to blocking, then there's a potential for
462        // an overall status change.
463        status_change = unblock(tid) || status_change || blockThisCycle;
464    }
465}
466
467template <class Impl>
468void
469DefaultRename<Impl>::renameInsts(unsigned tid)
470{
471    // Instructions can be either in the skid buffer or the queue of
472    // instructions coming from decode, depending on the status.
473    int insts_available = renameStatus[tid] == Unblocking ?
474        skidBuffer[tid].size() : insts[tid].size();
475
476    // Check the decode queue to see if instructions are available.
477    // If there are no available instructions to rename, then do nothing.
478    if (insts_available == 0) {
479        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
480                tid);
481        // Should I change status to idle?
482        ++renameIdleCycles;
483        return;
484    } else if (renameStatus[tid] == Unblocking) {
485        ++renameUnblockCycles;
486    } else if (renameStatus[tid] == Running) {
487        ++renameRunCycles;
488    }
489
490    DynInstPtr inst;
491
492    // Will have to do a different calculation for the number of free
493    // entries.
494    int free_rob_entries = calcFreeROBEntries(tid);
495    int free_iq_entries  = calcFreeIQEntries(tid);
496    int free_lsq_entries = calcFreeLSQEntries(tid);
497    int min_free_entries = free_rob_entries;
498
499    FullSource source = ROB;
500
501    if (free_iq_entries < min_free_entries) {
502        min_free_entries = free_iq_entries;
503        source = IQ;
504    }
505
506    if (free_lsq_entries < min_free_entries) {
507        min_free_entries = free_lsq_entries;
508        source = LSQ;
509    }
510
511    // Check if there's any space left.
512    if (min_free_entries <= 0) {
513        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
514                "entries.\n"
515                "ROB has %i free entries.\n"
516                "IQ has %i free entries.\n"
517                "LSQ has %i free entries.\n",
518                tid,
519                free_rob_entries,
520                free_iq_entries,
521                free_lsq_entries);
522
523        blockThisCycle = true;
524
525        block(tid);
526
527        incrFullStat(source);
528
529        return;
530    } else if (min_free_entries < insts_available) {
531        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
532                "%i insts available, but only %i insts can be "
533                "renamed due to ROB/IQ/LSQ limits.\n",
534                tid, insts_available, min_free_entries);
535
536        insts_available = min_free_entries;
537
538        blockThisCycle = true;
539
540        incrFullStat(source);
541    }
542
543    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
544        skidBuffer[tid] : insts[tid];
545
546    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
547            "send iew.\n", tid, insts_available);
548
549    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
550            "dispatched to IQ last cycle.\n",
551            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
552
553    // Handle serializing the next instruction if necessary.
554    if (serializeOnNextInst[tid]) {
555        if (emptyROB[tid] && instsInProgress[tid] == 0) {
556            // ROB already empty; no need to serialize.
557            serializeOnNextInst[tid] = false;
558        } else if (!insts_to_rename.empty()) {
559            insts_to_rename.front()->setSerializeBefore();
560        }
561    }
562
563    int renamed_insts = 0;
564
565    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
566        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
567
568        assert(!insts_to_rename.empty());
569
570        inst = insts_to_rename.front();
571
572        insts_to_rename.pop_front();
573
574        if (renameStatus[tid] == Unblocking) {
575            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
576                    "skidBuffer\n",
577                    tid, inst->seqNum, inst->readPC());
578        }
579
580        if (inst->isSquashed()) {
581            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
582                    "squashed, skipping.\n",
583                    tid, inst->seqNum, inst->threadNumber,inst->readPC());
584
585            ++renameSquashedInsts;
586
587            // Decrement how many instructions are available.
588            --insts_available;
589
590            continue;
591        }
592
593        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
594                "PC %#x.\n",
595                tid, inst->seqNum, inst->readPC());
596
597        // Handle serializeAfter/serializeBefore instructions.
598        // serializeAfter marks the next instruction as serializeBefore.
599        // serializeBefore makes the instruction wait in rename until the ROB
600        // is empty.
601
602        // In this model, IPR accesses are serialize before
603        // instructions, and store conditionals are serialize after
604        // instructions.  This is mainly due to lack of support for
605        // out-of-order operations of either of those classes of
606        // instructions.
607        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
608            !inst->isSerializeHandled()) {
609            DPRINTF(Rename, "Serialize before instruction encountered.\n");
610
611            if (!inst->isTempSerializeBefore()) {
612                renamedSerializing++;
613                inst->setSerializeHandled();
614            } else {
615                renamedTempSerializing++;
616            }
617
618            // Change status over to SerializeStall so that other stages know
619            // what this is blocked on.
620            renameStatus[tid] = SerializeStall;
621
622            serializeInst[tid] = inst;
623
624            blockThisCycle = true;
625
626            break;
627        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
628                   !inst->isSerializeHandled()) {
629            DPRINTF(Rename, "Serialize after instruction encountered.\n");
630
631            renamedSerializing++;
632
633            inst->setSerializeHandled();
634
635            serializeAfter(insts_to_rename, tid);
636        }
637
638        // Check here to make sure there are enough destination registers
639        // to rename to.  Otherwise block.
640        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
641            DPRINTF(Rename, "Blocking due to lack of free "
642                    "physical registers to rename to.\n");
643            blockThisCycle = true;
644
645            ++renameFullRegistersEvents;
646
647            break;
648        }
649
650        renameSrcRegs(inst, inst->threadNumber);
651
652        renameDestRegs(inst, inst->threadNumber);
653
654        ++renamed_insts;
655
656        // Put instruction in rename queue.
657        toIEW->insts[toIEWIndex] = inst;
658        ++(toIEW->size);
659
660        // Increment which instruction we're on.
661        ++toIEWIndex;
662
663        // Decrement how many instructions are available.
664        --insts_available;
665    }
666
667    instsInProgress[tid] += renamed_insts;
668    renameRenamedInsts += renamed_insts;
669
670    // If we wrote to the time buffer, record this.
671    if (toIEWIndex) {
672        wroteToTimeBuffer = true;
673    }
674
675    // Check if there's any instructions left that haven't yet been renamed.
676    // If so then block.
677    if (insts_available) {
678        blockThisCycle = true;
679    }
680
681    if (blockThisCycle) {
682        block(tid);
683        toDecode->renameUnblock[tid] = false;
684    }
685}
686
687template<class Impl>
688void
689DefaultRename<Impl>::skidInsert(unsigned tid)
690{
691    DynInstPtr inst = NULL;
692
693    while (!insts[tid].empty()) {
694        inst = insts[tid].front();
695
696        insts[tid].pop_front();
697
698        assert(tid == inst->threadNumber);
699
700        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
701                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
702
703        ++renameSkidInsts;
704
705        skidBuffer[tid].push_back(inst);
706    }
707
708    if (skidBuffer[tid].size() > skidBufferMax)
709        panic("Skidbuffer Exceeded Max Size");
710}
711
712template <class Impl>
713void
714DefaultRename<Impl>::sortInsts()
715{
716    int insts_from_decode = fromDecode->size;
717#ifdef DEBUG
718    for (int i=0; i < numThreads; i++)
719        assert(insts[i].empty());
720#endif
721    for (int i = 0; i < insts_from_decode; ++i) {
722        DynInstPtr inst = fromDecode->insts[i];
723        insts[inst->threadNumber].push_back(inst);
724    }
725}
726
727template<class Impl>
728bool
729DefaultRename<Impl>::skidsEmpty()
730{
731    list<unsigned>::iterator threads = (*activeThreads).begin();
732
733    while (threads != (*activeThreads).end()) {
734        if (!skidBuffer[*threads++].empty())
735            return false;
736    }
737
738    return true;
739}
740
741template<class Impl>
742void
743DefaultRename<Impl>::updateStatus()
744{
745    bool any_unblocking = false;
746
747    list<unsigned>::iterator threads = (*activeThreads).begin();
748
749    threads = (*activeThreads).begin();
750
751    while (threads != (*activeThreads).end()) {
752        unsigned tid = *threads++;
753
754        if (renameStatus[tid] == Unblocking) {
755            any_unblocking = true;
756            break;
757        }
758    }
759
760    // Rename will have activity if it's unblocking.
761    if (any_unblocking) {
762        if (_status == Inactive) {
763            _status = Active;
764
765            DPRINTF(Activity, "Activating stage.\n");
766
767            cpu->activateStage(FullCPU::RenameIdx);
768        }
769    } else {
770        // If it's not unblocking, then rename will not have any internal
771        // activity.  Switch it to inactive.
772        if (_status == Active) {
773            _status = Inactive;
774            DPRINTF(Activity, "Deactivating stage.\n");
775
776            cpu->deactivateStage(FullCPU::RenameIdx);
777        }
778    }
779}
780
781template <class Impl>
782bool
783DefaultRename<Impl>::block(unsigned tid)
784{
785    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
786
787    // Add the current inputs onto the skid buffer, so they can be
788    // reprocessed when this stage unblocks.
789    skidInsert(tid);
790
791    // Only signal backwards to block if the previous stages do not think
792    // rename is already blocked.
793    if (renameStatus[tid] != Blocked) {
794        if (renameStatus[tid] != Unblocking) {
795            toDecode->renameBlock[tid] = true;
796            toDecode->renameUnblock[tid] = false;
797            wroteToTimeBuffer = true;
798        }
799
800        // Rename can not go from SerializeStall to Blocked, otherwise
801        // it would not know to complete the serialize stall.
802        if (renameStatus[tid] != SerializeStall) {
803            // Set status to Blocked.
804            renameStatus[tid] = Blocked;
805            return true;
806        }
807    }
808
809    return false;
810}
811
812template <class Impl>
813bool
814DefaultRename<Impl>::unblock(unsigned tid)
815{
816    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
817
818    // Rename is done unblocking if the skid buffer is empty.
819    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
820
821        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
822
823        toDecode->renameUnblock[tid] = true;
824        wroteToTimeBuffer = true;
825
826        renameStatus[tid] = Running;
827        return true;
828    }
829
830    return false;
831}
832
833template <class Impl>
834void
835DefaultRename<Impl>::doSquash(unsigned tid)
836{
837    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
838
839    InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
840
841    // After a syscall squashes everything, the history buffer may be empty
842    // but the ROB may still be squashing instructions.
843    if (historyBuffer[tid].empty()) {
844        return;
845    }
846
847    // Go through the most recent instructions, undoing the mappings
848    // they did and freeing up the registers.
849    while (!historyBuffer[tid].empty() &&
850           (*hb_it).instSeqNum > squashed_seq_num) {
851        assert(hb_it != historyBuffer[tid].end());
852
853        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
854                "number %i.\n", tid, (*hb_it).instSeqNum);
855
856        // Tell the rename map to set the architected register to the
857        // previous physical register that it was renamed to.
858        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
859
860        // Put the renamed physical register back on the free list.
861        freeList->addReg(hb_it->newPhysReg);
862
863        historyBuffer[tid].erase(hb_it++);
864
865        ++renameUndoneMaps;
866    }
867}
868
869template<class Impl>
870void
871DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
872{
873    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
874            "history buffer %u (size=%i), until [sn:%lli].\n",
875            tid, tid, historyBuffer[tid].size(), inst_seq_num);
876
877    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
878
879    --hb_it;
880
881    if (historyBuffer[tid].empty()) {
882        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
883        return;
884    } else if (hb_it->instSeqNum > inst_seq_num) {
885        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
886                "that a syscall happened recently.\n", tid);
887        return;
888    }
889
890    // Commit all the renames up until (and including) the committed sequence
891    // number. Some or even all of the committed instructions may not have
892    // rename histories if they did not have destination registers that were
893    // renamed.
894    while (!historyBuffer[tid].empty() &&
895           hb_it != historyBuffer[tid].end() &&
896           (*hb_it).instSeqNum <= inst_seq_num) {
897
898        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
899                "[sn:%lli].\n",
900                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
901
902        freeList->addReg((*hb_it).prevPhysReg);
903        ++renameCommittedMaps;
904
905        historyBuffer[tid].erase(hb_it--);
906    }
907}
908
909template <class Impl>
910inline void
911DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
912{
913    assert(renameMap[tid] != 0);
914
915    unsigned num_src_regs = inst->numSrcRegs();
916
917    // Get the architectual register numbers from the source and
918    // destination operands, and redirect them to the right register.
919    // Will need to mark dependencies though.
920    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
921        RegIndex src_reg = inst->srcRegIdx(src_idx);
922
923        // Look up the source registers to get the phys. register they've
924        // been renamed to, and set the sources to those registers.
925        PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
926
927        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
928                "physical reg %i.\n", tid, (int)src_reg,
929                (int)renamed_reg);
930
931        inst->renameSrcReg(src_idx, renamed_reg);
932
933        // See if the register is ready or not.
934        if (scoreboard->getReg(renamed_reg) == true) {
935            DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
936
937            inst->markSrcRegReady(src_idx);
938        }
939
940        ++renameRenameLookups;
941    }
942}
943
944template <class Impl>
945inline void
946DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
947{
948    typename RenameMap::RenameInfo rename_result;
949
950    unsigned num_dest_regs = inst->numDestRegs();
951
952    // Rename the destination registers.
953    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
954        RegIndex dest_reg = inst->destRegIdx(dest_idx);
955
956        // Get the physical register that the destination will be
957        // renamed to.
958        rename_result = renameMap[tid]->rename(dest_reg);
959
960        //Mark Scoreboard entry as not ready
961        scoreboard->unsetReg(rename_result.first);
962
963        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
964                "reg %i.\n", tid, (int)dest_reg,
965                (int)rename_result.first);
966
967        // Record the rename information so that a history can be kept.
968        RenameHistory hb_entry(inst->seqNum, dest_reg,
969                               rename_result.first,
970                               rename_result.second);
971
972        historyBuffer[tid].push_front(hb_entry);
973
974        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
975                "[sn:%lli].\n",tid,
976                (*historyBuffer[tid].begin()).instSeqNum);
977
978        // Tell the instruction to rename the appropriate destination
979        // register (dest_idx) to the new physical register
980        // (rename_result.first), and record the previous physical
981        // register that the same logical register was renamed to
982        // (rename_result.second).
983        inst->renameDestReg(dest_idx,
984                            rename_result.first,
985                            rename_result.second);
986
987        ++renameRenamedOperands;
988    }
989}
990
991template <class Impl>
992inline int
993DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
994{
995    int num_free = freeEntries[tid].robEntries -
996                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
997
998    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
999
1000    return num_free;
1001}
1002
1003template <class Impl>
1004inline int
1005DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1006{
1007    int num_free = freeEntries[tid].iqEntries -
1008                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1009
1010    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1011
1012    return num_free;
1013}
1014
1015template <class Impl>
1016inline int
1017DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1018{
1019    int num_free = freeEntries[tid].lsqEntries -
1020                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1021
1022    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1023
1024    return num_free;
1025}
1026
1027template <class Impl>
1028unsigned
1029DefaultRename<Impl>::validInsts()
1030{
1031    unsigned inst_count = 0;
1032
1033    for (int i=0; i<fromDecode->size; i++) {
1034        if (!fromDecode->insts[i]->squashed)
1035            inst_count++;
1036    }
1037
1038    return inst_count;
1039}
1040
1041template <class Impl>
1042void
1043DefaultRename<Impl>::readStallSignals(unsigned tid)
1044{
1045    if (fromIEW->iewBlock[tid]) {
1046        stalls[tid].iew = true;
1047    }
1048
1049    if (fromIEW->iewUnblock[tid]) {
1050        assert(stalls[tid].iew);
1051        stalls[tid].iew = false;
1052    }
1053
1054    if (fromCommit->commitBlock[tid]) {
1055        stalls[tid].commit = true;
1056    }
1057
1058    if (fromCommit->commitUnblock[tid]) {
1059        assert(stalls[tid].commit);
1060        stalls[tid].commit = false;
1061    }
1062}
1063
1064template <class Impl>
1065bool
1066DefaultRename<Impl>::checkStall(unsigned tid)
1067{
1068    bool ret_val = false;
1069
1070    if (stalls[tid].iew) {
1071        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1072        ret_val = true;
1073    } else if (stalls[tid].commit) {
1074        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1075        ret_val = true;
1076    } else if (calcFreeROBEntries(tid) <= 0) {
1077        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1078        ret_val = true;
1079    } else if (calcFreeIQEntries(tid) <= 0) {
1080        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1081        ret_val = true;
1082    } else if (calcFreeLSQEntries(tid) <= 0) {
1083        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1084        ret_val = true;
1085    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1086        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1087        ret_val = true;
1088    } else if (renameStatus[tid] == SerializeStall &&
1089               (!emptyROB[tid] || instsInProgress[tid])) {
1090        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1091                "empty.\n",
1092                tid);
1093        ret_val = true;
1094    }
1095
1096    return ret_val;
1097}
1098
1099template <class Impl>
1100void
1101DefaultRename<Impl>::readFreeEntries(unsigned tid)
1102{
1103    bool updated = false;
1104    if (fromIEW->iewInfo[tid].usedIQ) {
1105        freeEntries[tid].iqEntries =
1106            fromIEW->iewInfo[tid].freeIQEntries;
1107        updated = true;
1108    }
1109
1110    if (fromIEW->iewInfo[tid].usedLSQ) {
1111        freeEntries[tid].lsqEntries =
1112            fromIEW->iewInfo[tid].freeLSQEntries;
1113        updated = true;
1114    }
1115
1116    if (fromCommit->commitInfo[tid].usedROB) {
1117        freeEntries[tid].robEntries =
1118            fromCommit->commitInfo[tid].freeROBEntries;
1119        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1120        updated = true;
1121    }
1122
1123    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1124            tid,
1125            freeEntries[tid].iqEntries,
1126            freeEntries[tid].robEntries,
1127            freeEntries[tid].lsqEntries);
1128
1129    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1130            tid, instsInProgress[tid]);
1131}
1132
1133template <class Impl>
1134bool
1135DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1136{
1137    // Check if there's a squash signal, squash if there is
1138    // Check stall signals, block if necessary.
1139    // If status was blocked
1140    //     check if stall conditions have passed
1141    //         if so then go to unblocking
1142    // If status was Squashing
1143    //     check if squashing is not high.  Switch to running this cycle.
1144    // If status was serialize stall
1145    //     check if ROB is empty and no insts are in flight to the ROB
1146
1147    readFreeEntries(tid);
1148    readStallSignals(tid);
1149
1150    if (fromCommit->commitInfo[tid].squash) {
1151        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1152                "commit.\n", tid);
1153
1154        squash(tid);
1155
1156        return true;
1157    }
1158
1159    if (fromCommit->commitInfo[tid].robSquashing) {
1160        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1161
1162        renameStatus[tid] = Squashing;
1163
1164        return true;
1165    }
1166
1167    if (checkStall(tid)) {
1168        return block(tid);
1169    }
1170
1171    if (renameStatus[tid] == Blocked) {
1172        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1173                tid);
1174
1175        renameStatus[tid] = Unblocking;
1176
1177        unblock(tid);
1178
1179        return true;
1180    }
1181
1182    if (renameStatus[tid] == Squashing) {
1183        // Switch status to running if rename isn't being told to block or
1184        // squash this cycle.
1185        DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1186                tid);
1187
1188        renameStatus[tid] = Running;
1189
1190        return false;
1191    }
1192
1193    if (renameStatus[tid] == SerializeStall) {
1194        // Stall ends once the ROB is free.
1195        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1196                "unblocking.\n", tid);
1197
1198        DynInstPtr serial_inst = serializeInst[tid];
1199
1200        renameStatus[tid] = Unblocking;
1201
1202        unblock(tid);
1203
1204        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1205                "PC %#x.\n",
1206                tid, serial_inst->seqNum, serial_inst->readPC());
1207
1208        // Put instruction into queue here.
1209        serial_inst->clearSerializeBefore();
1210
1211        if (!skidBuffer[tid].empty()) {
1212            skidBuffer[tid].push_front(serial_inst);
1213        } else {
1214            insts[tid].push_front(serial_inst);
1215        }
1216
1217        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1218                " Adding to front of list.", tid);
1219
1220        serializeInst[tid] = NULL;
1221
1222        return true;
1223    }
1224
1225    // If we've reached this point, we have not gotten any signals that
1226    // cause rename to change its status.  Rename remains the same as before.
1227    return false;
1228}
1229
1230template<class Impl>
1231void
1232DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1233                                   unsigned tid)
1234{
1235    if (inst_list.empty()) {
1236        // Mark a bit to say that I must serialize on the next instruction.
1237        serializeOnNextInst[tid] = true;
1238        return;
1239    }
1240
1241    // Set the next instruction as serializing.
1242    inst_list.front()->setSerializeBefore();
1243}
1244
1245template <class Impl>
1246inline void
1247DefaultRename<Impl>::incrFullStat(const FullSource &source)
1248{
1249    switch (source) {
1250      case ROB:
1251        ++renameROBFullEvents;
1252        break;
1253      case IQ:
1254        ++renameIQFullEvents;
1255        break;
1256      case LSQ:
1257        ++renameLSQFullEvents;
1258        break;
1259      default:
1260        panic("Rename full stall stat should be incremented for a reason!");
1261        break;
1262    }
1263}
1264
1265template <class Impl>
1266void
1267DefaultRename<Impl>::dumpHistory()
1268{
1269    typename list<RenameHistory>::iterator buf_it;
1270
1271    for (int i = 0; i < numThreads; i++) {
1272
1273        buf_it = historyBuffer[i].begin();
1274
1275        while (buf_it != historyBuffer[i].end()) {
1276            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1277                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1278                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1279
1280            buf_it++;
1281        }
1282    }
1283}
1284