rename_impl.hh revision 2307
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <list> 30 31#include "config/full_system.hh" 32#include "cpu/o3/rename.hh" 33 34using namespace std; 35 36template <class Impl> 37DefaultRename<Impl>::DefaultRename(Params *params) 38 : iewToRenameDelay(params->iewToRenameDelay), 39 decodeToRenameDelay(params->decodeToRenameDelay), 40 commitToRenameDelay(params->commitToRenameDelay), 41 renameWidth(params->renameWidth), 42 commitWidth(params->commitWidth), 43 numThreads(params->numberOfThreads) 44{ 45 _status = Inactive; 46 47 for (int i=0; i< numThreads; i++) { 48 renameStatus[i] = Idle; 49 50 freeEntries[i].iqEntries = 0; 51 freeEntries[i].lsqEntries = 0; 52 freeEntries[i].robEntries = 0; 53 54 stalls[i].iew = false; 55 stalls[i].commit = false; 56 serializeInst[i] = NULL; 57 58 instsInProgress[i] = 0; 59 60 emptyROB[i] = true; 61 62 serializeOnNextInst[i] = false; 63 } 64 65 // @todo: Make into a parameter. 66 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 67} 68 69template <class Impl> 70std::string 71DefaultRename<Impl>::name() const 72{ 73 return cpu->name() + ".rename"; 74} 75 76template <class Impl> 77void 78DefaultRename<Impl>::regStats() 79{ 80 renameSquashCycles 81 .name(name() + ".RENAME:SquashCycles") 82 .desc("Number of cycles rename is squashing") 83 .prereq(renameSquashCycles); 84 renameIdleCycles 85 .name(name() + ".RENAME:IdleCycles") 86 .desc("Number of cycles rename is idle") 87 .prereq(renameIdleCycles); 88 renameBlockCycles 89 .name(name() + ".RENAME:BlockCycles") 90 .desc("Number of cycles rename is blocking") 91 .prereq(renameBlockCycles); 92 renameSerializeStallCycles 93 .name(name() + ".RENAME:serializeStallCycles") 94 .desc("count of cycles rename stalled for serializing inst") 95 .flags(Stats::total); 96 renameRunCycles 97 .name(name() + ".RENAME:RunCycles") 98 .desc("Number of cycles rename is running") 99 .prereq(renameIdleCycles); 100 renameUnblockCycles 101 .name(name() + ".RENAME:UnblockCycles") 102 .desc("Number of cycles rename is unblocking") 103 .prereq(renameUnblockCycles); 104 renameRenamedInsts 105 .name(name() + ".RENAME:RenamedInsts") 106 .desc("Number of instructions processed by rename") 107 .prereq(renameRenamedInsts); 108 renameSquashedInsts 109 .name(name() + ".RENAME:SquashedInsts") 110 .desc("Number of squashed instructions processed by rename") 111 .prereq(renameSquashedInsts); 112 renameROBFullEvents 113 .name(name() + ".RENAME:ROBFullEvents") 114 .desc("Number of times rename has blocked due to ROB full") 115 .prereq(renameROBFullEvents); 116 renameIQFullEvents 117 .name(name() + ".RENAME:IQFullEvents") 118 .desc("Number of times rename has blocked due to IQ full") 119 .prereq(renameIQFullEvents); 120 renameLSQFullEvents 121 .name(name() + ".RENAME:LSQFullEvents") 122 .desc("Number of times rename has blocked due to LSQ full") 123 .prereq(renameLSQFullEvents); 124 renameFullRegistersEvents 125 .name(name() + ".RENAME:FullRegisterEvents") 126 .desc("Number of times there has been no free registers") 127 .prereq(renameFullRegistersEvents); 128 renameRenamedOperands 129 .name(name() + ".RENAME:RenamedOperands") 130 .desc("Number of destination operands rename has renamed") 131 .prereq(renameRenamedOperands); 132 renameRenameLookups 133 .name(name() + ".RENAME:RenameLookups") 134 .desc("Number of register rename lookups that rename has made") 135 .prereq(renameRenameLookups); 136 renameCommittedMaps 137 .name(name() + ".RENAME:CommittedMaps") 138 .desc("Number of HB maps that are committed") 139 .prereq(renameCommittedMaps); 140 renameUndoneMaps 141 .name(name() + ".RENAME:UndoneMaps") 142 .desc("Number of HB maps that are undone due to squashing") 143 .prereq(renameUndoneMaps); 144 renamedSerializing 145 .name(name() + ".RENAME:serializingInsts") 146 .desc("count of serializing insts renamed") 147 .flags(Stats::total) 148 ; 149 renamedTempSerializing 150 .name(name() + ".RENAME:tempSerializingInsts") 151 .desc("count of temporary serializing insts renamed") 152 .flags(Stats::total) 153 ; 154 renameSkidInsts 155 .name(name() + ".RENAME:skidInsts") 156 .desc("count of insts added to the skid buffer") 157 .flags(Stats::total) 158 ; 159} 160 161template <class Impl> 162void 163DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 164{ 165 DPRINTF(Rename, "Setting CPU pointer.\n"); 166 cpu = cpu_ptr; 167} 168 169template <class Impl> 170void 171DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 172{ 173 DPRINTF(Rename, "Setting time buffer pointer.\n"); 174 timeBuffer = tb_ptr; 175 176 // Setup wire to read information from time buffer, from IEW stage. 177 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 178 179 // Setup wire to read infromation from time buffer, from commit stage. 180 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 181 182 // Setup wire to write information to previous stages. 183 toDecode = timeBuffer->getWire(0); 184} 185 186template <class Impl> 187void 188DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 189{ 190 DPRINTF(Rename, "Setting rename queue pointer.\n"); 191 renameQueue = rq_ptr; 192 193 // Setup wire to write information to future stages. 194 toIEW = renameQueue->getWire(0); 195} 196 197template <class Impl> 198void 199DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 200{ 201 DPRINTF(Rename, "Setting decode queue pointer.\n"); 202 decodeQueue = dq_ptr; 203 204 // Setup wire to get information from decode. 205 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 206} 207 208template <class Impl> 209void 210DefaultRename<Impl>::initStage() 211{ 212 for (int tid=0; tid < numThreads; tid++) { 213 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 214 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 215 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 216 emptyROB[tid] = true; 217 } 218 219 // Clear these pointers so they are not accidentally used in 220 // non-initialization code. 221// iew_ptr = NULL; 222// commit_ptr = NULL; 223} 224 225template<class Impl> 226void 227DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 228{ 229 DPRINTF(Rename, "Setting active threads list pointer.\n"); 230 activeThreads = at_ptr; 231} 232 233 234template <class Impl> 235void 236DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 237{ 238 DPRINTF(Rename, "Setting rename map pointers.\n"); 239 240 for (int i=0; i<numThreads; i++) { 241 renameMap[i] = &rm_ptr[i]; 242 } 243} 244 245template <class Impl> 246void 247DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 248{ 249 DPRINTF(Rename, "Setting free list pointer.\n"); 250 freeList = fl_ptr; 251} 252 253template<class Impl> 254void 255DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 256{ 257 DPRINTF(Rename, "Setting scoreboard pointer.\n"); 258 scoreboard = _scoreboard; 259} 260 261template <class Impl> 262void 263DefaultRename<Impl>::switchOut() 264{ 265 for (int i = 0; i < numThreads; i++) { 266 typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 267 268 while (!historyBuffer[i].empty()) { 269 assert(hb_it != historyBuffer[i].end()); 270 271 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 272 "number %i.\n", i, (*hb_it).instSeqNum); 273 274 // Tell the rename map to set the architected register to the 275 // previous physical register that it was renamed to. 276 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 277 278 // Put the renamed physical register back on the free list. 279 freeList->addReg(hb_it->newPhysReg); 280 281 historyBuffer[i].erase(hb_it++); 282 } 283 insts[i].clear(); 284 skidBuffer[i].clear(); 285 } 286} 287 288template <class Impl> 289void 290DefaultRename<Impl>::takeOverFrom() 291{ 292 _status = Inactive; 293 initStage(); 294 295 for (int i=0; i< numThreads; i++) { 296 renameStatus[i] = Idle; 297 298 stalls[i].iew = false; 299 stalls[i].commit = false; 300 serializeInst[i] = NULL; 301 302 instsInProgress[i] = 0; 303 304 emptyROB[i] = true; 305 306 serializeOnNextInst[i] = false; 307 } 308} 309 310template <class Impl> 311void 312DefaultRename<Impl>::squash(unsigned tid) 313{ 314 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 315 316 // Clear the stall signal if rename was blocked or unblocking before. 317 // If it still needs to block, the blocking should happen the next 318 // cycle and there should be space to hold everything due to the squash. 319 if (renameStatus[tid] == Blocked || 320 renameStatus[tid] == Unblocking || 321 renameStatus[tid] == SerializeStall) { 322#if !FULL_SYSTEM 323 // In syscall emulation, we can have both a block and a squash due 324 // to a syscall in the same cycle. This would cause both signals to 325 // be high. This shouldn't happen in full system. 326 if (toDecode->renameBlock[tid]) { 327 toDecode->renameBlock[tid] = 0; 328 } else { 329 toDecode->renameUnblock[tid] = 1; 330 } 331#else 332 toDecode->renameUnblock[tid] = 1; 333#endif 334 serializeInst[tid] = NULL; 335 } 336 337 // Set the status to Squashing. 338 renameStatus[tid] = Squashing; 339 340 // Clear the skid buffer in case it has any data in it. 341 unsigned squashCount = 0; 342 343 for (int i=0; i<fromDecode->size; i++) { 344 if (fromDecode->insts[i]->threadNumber == tid) { 345 fromDecode->insts[i]->squashed = true; 346 wroteToTimeBuffer = true; 347 squashCount++; 348 } 349 } 350 351 insts[tid].clear(); 352 353 // Clear the skid buffer in case it has any data in it. 354 skidBuffer[tid].clear(); 355 356 doSquash(tid); 357} 358 359template <class Impl> 360void 361DefaultRename<Impl>::tick() 362{ 363 // Rename will need to try to rename as many instructions as it 364 // has bandwidth, unless it is blocked. 365 366 wroteToTimeBuffer = false; 367 368 blockThisCycle = false; 369 370 bool status_change = false; 371 372 toIEWIndex = 0; 373 374 sortInsts(); 375 376 list<unsigned>::iterator threads = (*activeThreads).begin(); 377 378 // Check stall and squash signals. 379 while (threads != (*activeThreads).end()) { 380 unsigned tid = *threads++; 381 382 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 383 384 status_change = checkSignalsAndUpdate(tid) || status_change; 385 386 rename(status_change, tid); 387 } 388 389 if (status_change) { 390 updateStatus(); 391 } 392 393 if (wroteToTimeBuffer) { 394 DPRINTF(Activity, "Activity this cycle.\n"); 395 cpu->activityThisCycle(); 396 } 397 398 threads = (*activeThreads).begin(); 399 400 while (threads != (*activeThreads).end()) { 401 unsigned tid = *threads++; 402 403 // If we committed this cycle then doneSeqNum will be > 0 404 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 405 !fromCommit->commitInfo[tid].squash && 406 renameStatus[tid] != Squashing) { 407 408 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 409 tid); 410 } 411 } 412 413 // @todo: make into updateProgress function 414 for (int tid=0; tid < numThreads; tid++) { 415 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 416 417 assert(instsInProgress[tid] >=0); 418 } 419 420} 421 422template<class Impl> 423void 424DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 425{ 426 // If status is Running or idle, 427 // call renameInsts() 428 // If status is Unblocking, 429 // buffer any instructions coming from decode 430 // continue trying to empty skid buffer 431 // check if stall conditions have passed 432 433 if (renameStatus[tid] == Blocked) { 434 ++renameBlockCycles; 435 } else if (renameStatus[tid] == Squashing) { 436 ++renameSquashCycles; 437 } else if (renameStatus[tid] == SerializeStall) { 438 ++renameSerializeStallCycles; 439 } 440 441 if (renameStatus[tid] == Running || 442 renameStatus[tid] == Idle) { 443 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 444 "stage.\n", tid); 445 446 renameInsts(tid); 447 } else if (renameStatus[tid] == Unblocking) { 448 renameInsts(tid); 449 450// ++renameUnblockCycles; 451 452 if (validInsts()) { 453 // Add the current inputs to the skid buffer so they can be 454 // reprocessed when this stage unblocks. 455 skidInsert(tid); 456 } 457 458 // If we switched over to blocking, then there's a potential for 459 // an overall status change. 460 status_change = unblock(tid) || status_change || blockThisCycle; 461 } 462} 463 464template <class Impl> 465void 466DefaultRename<Impl>::renameInsts(unsigned tid) 467{ 468 // Instructions can be either in the skid buffer or the queue of 469 // instructions coming from decode, depending on the status. 470 int insts_available = renameStatus[tid] == Unblocking ? 471 skidBuffer[tid].size() : insts[tid].size(); 472 473 // Check the decode queue to see if instructions are available. 474 // If there are no available instructions to rename, then do nothing. 475 if (insts_available == 0) { 476 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 477 tid); 478 // Should I change status to idle? 479 ++renameIdleCycles; 480 return; 481 } else if (renameStatus[tid] == Unblocking) { 482 ++renameUnblockCycles; 483 } else if (renameStatus[tid] == Running) { 484 ++renameRunCycles; 485 } 486 487 DynInstPtr inst; 488 489 // Will have to do a different calculation for the number of free 490 // entries. 491 int free_rob_entries = calcFreeROBEntries(tid); 492 int free_iq_entries = calcFreeIQEntries(tid); 493 int free_lsq_entries = calcFreeLSQEntries(tid); 494 int min_free_entries = free_rob_entries; 495 496 FullSource source = ROB; 497 498 if (free_iq_entries < min_free_entries) { 499 min_free_entries = free_iq_entries; 500 source = IQ; 501 } 502 503 if (free_lsq_entries < min_free_entries) { 504 min_free_entries = free_lsq_entries; 505 source = LSQ; 506 } 507 508 // Check if there's any space left. 509 if (min_free_entries <= 0) { 510 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 511 "entries.\n" 512 "ROB has %i free entries.\n" 513 "IQ has %i free entries.\n" 514 "LSQ has %i free entries.\n", 515 tid, 516 free_rob_entries, 517 free_iq_entries, 518 free_lsq_entries); 519 520 blockThisCycle = true; 521 522 block(tid); 523 524 incrFullStat(source); 525 526 return; 527 } else if (min_free_entries < insts_available) { 528 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 529 "%i insts available, but only %i insts can be " 530 "renamed due to ROB/IQ/LSQ limits.\n", 531 tid, insts_available, min_free_entries); 532 533 insts_available = min_free_entries; 534 535 blockThisCycle = true; 536 537 incrFullStat(source); 538 } 539 540 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 541 skidBuffer[tid] : insts[tid]; 542 543 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 544 "send iew.\n", tid, insts_available); 545 546 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 547 "dispatched to IQ last cycle.\n", 548 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 549 550 // Handle serializing the next instruction if necessary. 551 if (serializeOnNextInst[tid]) { 552 if (emptyROB[tid] && instsInProgress[tid] == 0) { 553 // ROB already empty; no need to serialize. 554 serializeOnNextInst[tid] = false; 555 } else if (!insts_to_rename.empty()) { 556 insts_to_rename.front()->setSerializeBefore(); 557 } 558 } 559 560 int renamed_insts = 0; 561 562 while (insts_available > 0 && toIEWIndex < renameWidth) { 563 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 564 565 assert(!insts_to_rename.empty()); 566 567 inst = insts_to_rename.front(); 568 569 insts_to_rename.pop_front(); 570 571 //Use skidBuffer with oldest instructions 572 if (renameStatus[tid] == Unblocking) { 573 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 574 "skidBuffer\n", 575 tid, inst->seqNum, inst->readPC()); 576 } 577 578 if (inst->isSquashed()) { 579 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 580 "squashed, skipping.\n", 581 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 582 583 ++renameSquashedInsts; 584 585 // Decrement how many instructions are available. 586 --insts_available; 587 588 continue; 589 } 590 591 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 592 "PC %#x.\n", 593 tid, inst->seqNum, inst->readPC()); 594 595 // Handle serializeAfter/serializeBefore instructions. 596 // serializeAfter marks the next instruction as serializeBefore. 597 // serializeBefore makes the instruction wait in rename until the ROB 598 // is empty. 599 if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { 600 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 601 602 if (!inst->isTempSerializeBefore()) { 603 renamedSerializing++; 604 inst->setSerializeHandled(); 605 } else { 606 renamedTempSerializing++; 607 } 608 609 // Change status over to SerializeStall so that other stages know 610 // what this is blocked on. 611 renameStatus[tid] = SerializeStall; 612 613 serializeInst[tid] = inst; 614 615 blockThisCycle = true; 616 617 break; 618 } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { 619 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 620 621 renamedSerializing++; 622 623 inst->setSerializeHandled(); 624 625 serializeAfter(insts_to_rename, tid); 626 } 627 628 // Check here to make sure there are enough destination registers 629 // to rename to. Otherwise block. 630 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 631 DPRINTF(Rename, "Blocking due to lack of free " 632 "physical registers to rename to.\n"); 633 blockThisCycle = true; 634 635 ++renameFullRegistersEvents; 636 637 break; 638 } 639 640 renameSrcRegs(inst, inst->threadNumber); 641 642 renameDestRegs(inst, inst->threadNumber); 643 644 ++renamed_insts; 645 646 // Put instruction in rename queue. 647 toIEW->insts[toIEWIndex] = inst; 648 ++(toIEW->size); 649 650 // Increment which instruction we're on. 651 ++toIEWIndex; 652 653 // Decrement how many instructions are available. 654 --insts_available; 655 } 656 657 instsInProgress[tid] += renamed_insts; 658 renameRenamedInsts += renamed_insts; 659 660 // If we wrote to the time buffer, record this. 661 if (toIEWIndex) { 662 wroteToTimeBuffer = true; 663 } 664 665 // Check if there's any instructions left that haven't yet been renamed. 666 // If so then block. 667 if (insts_available) { 668 blockThisCycle = true; 669 } 670 671 if (blockThisCycle) { 672 block(tid); 673 toDecode->renameUnblock[tid] = false; 674 } 675} 676 677template<class Impl> 678void 679DefaultRename<Impl>::skidInsert(unsigned tid) 680{ 681 DynInstPtr inst = NULL; 682 683 while (!insts[tid].empty()) { 684 inst = insts[tid].front(); 685 686 insts[tid].pop_front(); 687 688 assert(tid == inst->threadNumber); 689 690 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 691 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 692 693 ++renameSkidInsts; 694 695 skidBuffer[tid].push_back(inst); 696 } 697 698 if (skidBuffer[tid].size() > skidBufferMax) 699 panic("Skidbuffer Exceeded Max Size"); 700} 701 702template <class Impl> 703void 704DefaultRename<Impl>::sortInsts() 705{ 706 int insts_from_decode = fromDecode->size; 707 708 for (int i=0; i < numThreads; i++) 709 assert(insts[i].empty()); 710 711 for (int i = 0; i < insts_from_decode; ++i) { 712 DynInstPtr inst = fromDecode->insts[i]; 713 insts[inst->threadNumber].push_back(inst); 714 } 715} 716 717template<class Impl> 718bool 719DefaultRename<Impl>::skidsEmpty() 720{ 721 list<unsigned>::iterator threads = (*activeThreads).begin(); 722 723 while (threads != (*activeThreads).end()) { 724 if (!skidBuffer[*threads++].empty()) 725 return false; 726 } 727 728 return true; 729} 730 731template<class Impl> 732void 733DefaultRename<Impl>::updateStatus() 734{ 735 bool any_unblocking = false; 736 737 list<unsigned>::iterator threads = (*activeThreads).begin(); 738 739 threads = (*activeThreads).begin(); 740 741 while (threads != (*activeThreads).end()) { 742 unsigned tid = *threads++; 743 744 if (renameStatus[tid] == Unblocking) { 745 any_unblocking = true; 746 break; 747 } 748 } 749 750 // Rename will have activity if it's unblocking. 751 if (any_unblocking) { 752 if (_status == Inactive) { 753 _status = Active; 754 755 DPRINTF(Activity, "Activating stage.\n"); 756 757 cpu->activateStage(FullCPU::RenameIdx); 758 } 759 } else { 760 // If it's not unblocking, then rename will not have any internal 761 // activity. Switch it to inactive. 762 if (_status == Active) { 763 _status = Inactive; 764 DPRINTF(Activity, "Deactivating stage.\n"); 765 766 cpu->deactivateStage(FullCPU::RenameIdx); 767 } 768 } 769} 770 771template <class Impl> 772bool 773DefaultRename<Impl>::block(unsigned tid) 774{ 775 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 776 777 // Add the current inputs onto the skid buffer, so they can be 778 // reprocessed when this stage unblocks. 779 skidInsert(tid); 780 781 // Only signal backwards to block if the previous stages do not think 782 // rename is already blocked. 783 if (renameStatus[tid] != Blocked) { 784 if (renameStatus[tid] != Unblocking) { 785 toDecode->renameBlock[tid] = true; 786 toDecode->renameUnblock[tid] = false; 787 wroteToTimeBuffer = true; 788 } 789 790 // Rename can not go from SerializeStall to Blocked, otherwise it would 791 // not know to complete the serialize stall. 792 if (renameStatus[tid] != SerializeStall) { 793 // Set status to Blocked. 794 renameStatus[tid] = Blocked; 795 return true; 796 } 797 } 798 799 return false; 800} 801 802template <class Impl> 803bool 804DefaultRename<Impl>::unblock(unsigned tid) 805{ 806 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 807 808 // Rename is done unblocking if the skid buffer is empty. 809 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 810 811 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 812 813 toDecode->renameUnblock[tid] = true; 814 wroteToTimeBuffer = true; 815 816 renameStatus[tid] = Running; 817 return true; 818 } 819 820 return false; 821} 822 823template <class Impl> 824void 825DefaultRename<Impl>::doSquash(unsigned tid) 826{ 827 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 828 829 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 830 831//#if FULL_SYSTEM 832// assert(!historyBuffer[tid].empty()); 833//#else 834 // After a syscall squashes everything, the history buffer may be empty 835 // but the ROB may still be squashing instructions. 836 if (historyBuffer[tid].empty()) { 837 return; 838 } 839//#endif // FULL_SYSTEM 840 841 // Go through the most recent instructions, undoing the mappings 842 // they did and freeing up the registers. 843 while (!historyBuffer[tid].empty() && 844 (*hb_it).instSeqNum > squashed_seq_num) { 845 assert(hb_it != historyBuffer[tid].end()); 846 847 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 848 "number %i.\n", tid, (*hb_it).instSeqNum); 849 850 // Tell the rename map to set the architected register to the 851 // previous physical register that it was renamed to. 852 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 853 854 // Put the renamed physical register back on the free list. 855 freeList->addReg(hb_it->newPhysReg); 856 857 historyBuffer[tid].erase(hb_it++); 858 859 ++renameUndoneMaps; 860 } 861} 862 863template<class Impl> 864void 865DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 866{ 867 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 868 "history buffer %u (size=%i), until [sn:%lli].\n", 869 tid, tid, historyBuffer[tid].size(), inst_seq_num); 870 871 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 872 873 --hb_it; 874 875 if (historyBuffer[tid].empty()) { 876 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 877 return; 878 } else if (hb_it->instSeqNum > inst_seq_num) { 879 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 880 "that a syscall happened recently.\n", tid); 881 return; 882 } 883 884 // Commit all the renames up until (and including) the committed sequence 885 // number. Some or even all of the committed instructions may not have 886 // rename histories if they did not have destination registers that were 887 // renamed. 888 while (!historyBuffer[tid].empty() && 889 hb_it != historyBuffer[tid].end() && 890 (*hb_it).instSeqNum <= inst_seq_num) { 891 892 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, sequence" 893 " number %i.\n", 894 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 895 896 freeList->addReg((*hb_it).prevPhysReg); 897 ++renameCommittedMaps; 898 899 historyBuffer[tid].erase(hb_it--); 900 } 901} 902 903template <class Impl> 904inline void 905DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 906{ 907 assert(renameMap[tid] != 0); 908 909 unsigned num_src_regs = inst->numSrcRegs(); 910 911 // Get the architectual register numbers from the source and 912 // destination operands, and redirect them to the right register. 913 // Will need to mark dependencies though. 914 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 915 RegIndex src_reg = inst->srcRegIdx(src_idx); 916 917 // Look up the source registers to get the phys. register they've 918 // been renamed to, and set the sources to those registers. 919 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 920 921 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 922 "physical reg %i.\n", tid, (int)src_reg, 923 (int)renamed_reg); 924 925 inst->renameSrcReg(src_idx, renamed_reg); 926 927 // See if the register is ready or not. 928 if (scoreboard->getReg(renamed_reg) == true) { 929 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 930 931 inst->markSrcRegReady(src_idx); 932 } 933 934 ++renameRenameLookups; 935 } 936} 937 938template <class Impl> 939inline void 940DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 941{ 942 typename RenameMap::RenameInfo rename_result; 943 944 unsigned num_dest_regs = inst->numDestRegs(); 945 946 // Rename the destination registers. 947 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 948 RegIndex dest_reg = inst->destRegIdx(dest_idx); 949 950 // Get the physical register that the destination will be 951 // renamed to. 952 rename_result = renameMap[tid]->rename(dest_reg); 953 954 //Mark Scoreboard entry as not ready 955 scoreboard->unsetReg(rename_result.first); 956 957 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 958 "reg %i.\n", tid, (int)dest_reg, 959 (int)rename_result.first); 960 961 // Record the rename information so that a history can be kept. 962 RenameHistory hb_entry(inst->seqNum, dest_reg, 963 rename_result.first, 964 rename_result.second); 965 966 historyBuffer[tid].push_front(hb_entry); 967 968 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 969 "[sn:%lli].\n",tid, 970 (*historyBuffer[tid].begin()).instSeqNum); 971 972 // Tell the instruction to rename the appropriate destination 973 // register (dest_idx) to the new physical register 974 // (rename_result.first), and record the previous physical 975 // register that the same logical register was renamed to 976 // (rename_result.second). 977 inst->renameDestReg(dest_idx, 978 rename_result.first, 979 rename_result.second); 980 981 ++renameRenamedOperands; 982 } 983} 984 985template <class Impl> 986inline int 987DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 988{ 989 int num_free = freeEntries[tid].robEntries - 990 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 991 992 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 993 994 return num_free; 995} 996 997template <class Impl> 998inline int 999DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 1000{ 1001 int num_free = freeEntries[tid].iqEntries - 1002 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1003 1004 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1005 1006 return num_free; 1007} 1008 1009template <class Impl> 1010inline int 1011DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1012{ 1013 int num_free = freeEntries[tid].lsqEntries - 1014 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1015 1016 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1017 1018 return num_free; 1019} 1020 1021template <class Impl> 1022unsigned 1023DefaultRename<Impl>::validInsts() 1024{ 1025 unsigned inst_count = 0; 1026 1027 for (int i=0; i<fromDecode->size; i++) { 1028 if (!fromDecode->insts[i]->squashed) 1029 inst_count++; 1030 } 1031 1032 return inst_count; 1033} 1034 1035template <class Impl> 1036void 1037DefaultRename<Impl>::readStallSignals(unsigned tid) 1038{ 1039 if (fromIEW->iewBlock[tid]) { 1040 stalls[tid].iew = true; 1041 } 1042 1043 if (fromIEW->iewUnblock[tid]) { 1044 assert(stalls[tid].iew); 1045 stalls[tid].iew = false; 1046 } 1047 1048 if (fromCommit->commitBlock[tid]) { 1049 stalls[tid].commit = true; 1050 } 1051 1052 if (fromCommit->commitUnblock[tid]) { 1053 assert(stalls[tid].commit); 1054 stalls[tid].commit = false; 1055 } 1056} 1057 1058template <class Impl> 1059bool 1060DefaultRename<Impl>::checkStall(unsigned tid) 1061{ 1062 bool ret_val = false; 1063 1064 if (stalls[tid].iew) { 1065 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1066 ret_val = true; 1067 } else if (stalls[tid].commit) { 1068 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1069 ret_val = true; 1070 } else if (calcFreeROBEntries(tid) <= 0) { 1071 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1072 ret_val = true; 1073 } else if (calcFreeIQEntries(tid) <= 0) { 1074 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1075 ret_val = true; 1076 } else if (calcFreeLSQEntries(tid) <= 0) { 1077 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1078 ret_val = true; 1079 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1080 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1081 ret_val = true; 1082 } else if (renameStatus[tid] == SerializeStall && 1083 (!emptyROB[tid] || instsInProgress[tid])) { 1084 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1085 "empty.\n", 1086 tid); 1087 ret_val = true; 1088 } 1089 1090 return ret_val; 1091} 1092 1093template <class Impl> 1094void 1095DefaultRename<Impl>::readFreeEntries(unsigned tid) 1096{ 1097 bool updated = false; 1098 if (fromIEW->iewInfo[tid].usedIQ) { 1099 freeEntries[tid].iqEntries = 1100 fromIEW->iewInfo[tid].freeIQEntries; 1101 updated = true; 1102 } 1103 1104 if (fromIEW->iewInfo[tid].usedLSQ) { 1105 freeEntries[tid].lsqEntries = 1106 fromIEW->iewInfo[tid].freeLSQEntries; 1107 updated = true; 1108 } 1109 1110 if (fromCommit->commitInfo[tid].usedROB) { 1111 freeEntries[tid].robEntries = 1112 fromCommit->commitInfo[tid].freeROBEntries; 1113 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1114 updated = true; 1115 } 1116 1117 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1118 tid, 1119 freeEntries[tid].iqEntries, 1120 freeEntries[tid].robEntries, 1121 freeEntries[tid].lsqEntries); 1122 1123 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1124 tid, instsInProgress[tid]); 1125} 1126 1127template <class Impl> 1128bool 1129DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1130{ 1131 // Check if there's a squash signal, squash if there is 1132 // Check stall signals, block if necessary. 1133 // If status was blocked 1134 // check if stall conditions have passed 1135 // if so then go to unblocking 1136 // If status was Squashing 1137 // check if squashing is not high. Switch to running this cycle. 1138 // If status was serialize stall 1139 // check if ROB is empty and no insts are in flight to the ROB 1140 1141 readFreeEntries(tid); 1142 readStallSignals(tid); 1143 1144 if (fromCommit->commitInfo[tid].squash) { 1145 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1146 "commit.\n", tid); 1147 1148 squash(tid); 1149 1150 return true; 1151 } 1152 1153 if (fromCommit->commitInfo[tid].robSquashing) { 1154 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1155 1156 renameStatus[tid] = Squashing; 1157 1158 return true; 1159 } 1160 1161 if (checkStall(tid)) { 1162 return block(tid); 1163 } 1164 1165 if (renameStatus[tid] == Blocked) { 1166 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1167 tid); 1168 1169 renameStatus[tid] = Unblocking; 1170 1171 unblock(tid); 1172 1173 return true; 1174 } 1175 1176 if (renameStatus[tid] == Squashing) { 1177 // Switch status to running if rename isn't being told to block or 1178 // squash this cycle. 1179 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1180 tid); 1181 1182 renameStatus[tid] = Running; 1183 1184 return false; 1185 } 1186 1187 if (renameStatus[tid] == SerializeStall) { 1188 // Stall ends once the ROB is free. 1189 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1190 "unblocking.\n", tid); 1191 1192 DynInstPtr serial_inst = serializeInst[tid]; 1193 1194 renameStatus[tid] = Unblocking; 1195 1196 unblock(tid); 1197 1198 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1199 "PC %#x.\n", 1200 tid, serial_inst->seqNum, serial_inst->readPC()); 1201 1202 // Put instruction into queue here. 1203 serial_inst->clearSerializeBefore(); 1204 1205 if (!skidBuffer[tid].empty()) { 1206 skidBuffer[tid].push_front(serial_inst); 1207 } else { 1208 insts[tid].push_front(serial_inst); 1209 } 1210 1211 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1212 " Adding to front of list.", tid); 1213 1214 serializeInst[tid] = NULL; 1215 1216 return true; 1217 } 1218 1219 // If we've reached this point, we have not gotten any signals that 1220 // cause rename to change its status. Rename remains the same as before. 1221 return false; 1222} 1223 1224template<class Impl> 1225void 1226DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1227 unsigned tid) 1228{ 1229 if (inst_list.empty()) { 1230 // Mark a bit to say that I must serialize on the next instruction. 1231 serializeOnNextInst[tid] = true; 1232 return; 1233 } 1234 1235 // Set the next instruction as serializing. 1236 inst_list.front()->setSerializeBefore(); 1237} 1238 1239template <class Impl> 1240inline void 1241DefaultRename<Impl>::incrFullStat(const FullSource &source) 1242{ 1243 switch (source) { 1244 case ROB: 1245 ++renameROBFullEvents; 1246 break; 1247 case IQ: 1248 ++renameIQFullEvents; 1249 break; 1250 case LSQ: 1251 ++renameLSQFullEvents; 1252 break; 1253 default: 1254 panic("Rename full stall stat should be incremented for a reason!"); 1255 break; 1256 } 1257} 1258 1259template <class Impl> 1260void 1261DefaultRename<Impl>::dumpHistory() 1262{ 1263 typename list<RenameHistory>::iterator buf_it; 1264 1265 for (int i = 0; i < numThreads; i++) { 1266 1267 buf_it = historyBuffer[i].begin(); 1268 1269 while (buf_it != historyBuffer[i].end()) { 1270 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1271 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1272 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1273 1274 buf_it++; 1275 } 1276 } 1277} 1278