rename_impl.hh revision 2292
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <list> 30 31#include "config/full_system.hh" 32#include "cpu/o3/rename.hh" 33 34using namespace std; 35 36template <class Impl> 37DefaultRename<Impl>::DefaultRename(Params *params) 38 : iewToRenameDelay(params->iewToRenameDelay), 39 decodeToRenameDelay(params->decodeToRenameDelay), 40 commitToRenameDelay(params->commitToRenameDelay), 41 renameWidth(params->renameWidth), 42 commitWidth(params->commitWidth), 43 numThreads(params->numberOfThreads) 44{ 45 _status = Inactive; 46 47 for (int i=0; i< numThreads; i++) { 48 renameStatus[i] = Idle; 49 50 freeEntries[i].iqEntries = 0; 51 freeEntries[i].lsqEntries = 0; 52 freeEntries[i].robEntries = 0; 53 54 stalls[i].iew = false; 55 stalls[i].commit = false; 56 barrierInst[i] = NULL; 57 58 instsInProgress[i] = 0; 59 60 emptyROB[i] = true; 61 62 serializeOnNextInst[i] = false; 63 } 64 65 // @todo: Make into a parameter. 66 skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 67} 68 69template <class Impl> 70std::string 71DefaultRename<Impl>::name() const 72{ 73 return cpu->name() + ".rename"; 74} 75 76template <class Impl> 77void 78DefaultRename<Impl>::regStats() 79{ 80 renameSquashCycles 81 .name(name() + ".renameSquashCycles") 82 .desc("Number of cycles rename is squashing") 83 .prereq(renameSquashCycles); 84 renameIdleCycles 85 .name(name() + ".renameIdleCycles") 86 .desc("Number of cycles rename is idle") 87 .prereq(renameIdleCycles); 88 renameBlockCycles 89 .name(name() + ".renameBlockCycles") 90 .desc("Number of cycles rename is blocking") 91 .prereq(renameBlockCycles); 92 renameBarrierCycles 93 .name(name() + ".renameBarrierCycles") 94 .desc("Number of cycles rename is blocking due to a barrier stall") 95 .prereq(renameBarrierCycles); 96 renameRunCycles 97 .name(name() + ".renameRunCycles") 98 .desc("Number of cycles rename is running") 99 .prereq(renameIdleCycles); 100 renameUnblockCycles 101 .name(name() + ".renameUnblockCycles") 102 .desc("Number of cycles rename is unblocking") 103 .prereq(renameUnblockCycles); 104 renameRenamedInsts 105 .name(name() + ".renameRenamedInsts") 106 .desc("Number of instructions processed by rename") 107 .prereq(renameRenamedInsts); 108 renameSquashedInsts 109 .name(name() + ".renameSquashedInsts") 110 .desc("Number of squashed instructions processed by rename") 111 .prereq(renameSquashedInsts); 112 renameROBFullEvents 113 .name(name() + ".renameROBFullEvents") 114 .desc("Number of times rename has blocked due to ROB full") 115 .prereq(renameROBFullEvents); 116 renameIQFullEvents 117 .name(name() + ".renameIQFullEvents") 118 .desc("Number of times rename has blocked due to IQ full") 119 .prereq(renameIQFullEvents); 120 renameLSQFullEvents 121 .name(name() + ".renameLSQFullEvents") 122 .desc("Number of times rename has blocked due to LSQ full") 123 .prereq(renameLSQFullEvents); 124 renameFullRegistersEvents 125 .name(name() + ".renameFullRegisterEvents") 126 .desc("Number of times there has been no free registers") 127 .prereq(renameFullRegistersEvents); 128 renameRenamedOperands 129 .name(name() + ".renameRenamedOperands") 130 .desc("Number of destination operands rename has renamed") 131 .prereq(renameRenamedOperands); 132 renameRenameLookups 133 .name(name() + ".renameRenameLookups") 134 .desc("Number of register rename lookups that rename has made") 135 .prereq(renameRenameLookups); 136 renameCommittedMaps 137 .name(name() + ".renameCommittedMaps") 138 .desc("Number of HB maps that are committed") 139 .prereq(renameCommittedMaps); 140 renameUndoneMaps 141 .name(name() + ".renameUndoneMaps") 142 .desc("Number of HB maps that are undone due to squashing") 143 .prereq(renameUndoneMaps); 144} 145 146template <class Impl> 147void 148DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 149{ 150 DPRINTF(Rename, "Setting CPU pointer.\n"); 151 cpu = cpu_ptr; 152} 153 154template <class Impl> 155void 156DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 157{ 158 DPRINTF(Rename, "Setting time buffer pointer.\n"); 159 timeBuffer = tb_ptr; 160 161 // Setup wire to read information from time buffer, from IEW stage. 162 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 163 164 // Setup wire to read infromation from time buffer, from commit stage. 165 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 166 167 // Setup wire to write information to previous stages. 168 toDecode = timeBuffer->getWire(0); 169} 170 171template <class Impl> 172void 173DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 174{ 175 DPRINTF(Rename, "Setting rename queue pointer.\n"); 176 renameQueue = rq_ptr; 177 178 // Setup wire to write information to future stages. 179 toIEW = renameQueue->getWire(0); 180} 181 182template <class Impl> 183void 184DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 185{ 186 DPRINTF(Rename, "Setting decode queue pointer.\n"); 187 decodeQueue = dq_ptr; 188 189 // Setup wire to get information from decode. 190 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 191} 192 193template <class Impl> 194void 195DefaultRename<Impl>::initStage() 196{ 197 for (int tid=0; tid < numThreads; tid++) { 198 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 199 freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 200 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 201 emptyROB[tid] = true; 202 } 203 204 // Clear these pointers so they are not accidentally used in 205 // non-initialization code. 206 iew_ptr = NULL; 207 commit_ptr = NULL; 208} 209 210template<class Impl> 211void 212DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 213{ 214 DPRINTF(Rename, "Setting active threads list pointer.\n"); 215 activeThreads = at_ptr; 216} 217 218 219template <class Impl> 220void 221DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 222{ 223 DPRINTF(Rename, "Setting rename map pointers.\n"); 224 225 for (int i=0; i<numThreads; i++) { 226 renameMap[i] = &rm_ptr[i]; 227 } 228} 229 230template <class Impl> 231void 232DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 233{ 234 DPRINTF(Rename, "Setting free list pointer.\n"); 235 freeList = fl_ptr; 236} 237 238template<class Impl> 239void 240DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 241{ 242 DPRINTF(Rename, "Setting scoreboard pointer.\n"); 243 scoreboard = _scoreboard; 244} 245 246template <class Impl> 247void 248DefaultRename<Impl>::squash(unsigned tid) 249{ 250 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 251 252 // Clear the stall signal if rename was blocked or unblocking before. 253 // If it still needs to block, the blocking should happen the next 254 // cycle and there should be space to hold everything due to the squash. 255 if (renameStatus[tid] == Blocked || 256 renameStatus[tid] == Unblocking || 257 renameStatus[tid] == BarrierStall) { 258#if !FULL_SYSTEM 259 // In syscall emulation, we can have both a block and a squash due 260 // to a syscall in the same cycle. This would cause both signals to 261 // be high. This shouldn't happen in full system. 262 if (toDecode->renameBlock[tid]) { 263 toDecode->renameBlock[tid] = 0; 264 } else { 265 toDecode->renameUnblock[tid] = 1; 266 } 267#else 268 toDecode->renameUnblock[tid] = 1; 269#endif 270 barrierInst[tid] = NULL; 271 } 272 273 // Set the status to Squashing. 274 renameStatus[tid] = Squashing; 275 276 // Clear the skid buffer in case it has any data in it. 277 unsigned squashCount = 0; 278 279 for (int i=0; i<fromDecode->size; i++) { 280 if (fromDecode->insts[i]->threadNumber == tid) { 281 fromDecode->insts[i]->squashed = true; 282 wroteToTimeBuffer = true; 283 squashCount++; 284 } 285 } 286 287 insts[tid].clear(); 288 289 // Clear the skid buffer in case it has any data in it. 290 skidBuffer[tid].clear(); 291 292 doSquash(tid); 293} 294 295template <class Impl> 296void 297DefaultRename<Impl>::tick() 298{ 299 // Rename will need to try to rename as many instructions as it 300 // has bandwidth, unless it is blocked. 301 302 wroteToTimeBuffer = false; 303 304 blockThisCycle = false; 305 306 bool status_change = false; 307 308 toIEWIndex = 0; 309 310 sortInsts(); 311 312 list<unsigned>::iterator threads = (*activeThreads).begin(); 313 314 // Check stall and squash signals. 315 while (threads != (*activeThreads).end()) { 316 unsigned tid = *threads++; 317 318 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 319 320 status_change = checkSignalsAndUpdate(tid) || status_change; 321 322 rename(status_change, tid); 323 } 324 325 if (status_change) { 326 updateStatus(); 327 } 328 329 if (wroteToTimeBuffer) { 330 DPRINTF(Activity, "Activity this cycle.\n"); 331 cpu->activityThisCycle(); 332 } 333 334 threads = (*activeThreads).begin(); 335 336 while (threads != (*activeThreads).end()) { 337 unsigned tid = *threads++; 338 339 // If we committed this cycle then doneSeqNum will be > 0 340 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 341 !fromCommit->commitInfo[tid].squash && 342 renameStatus[tid] != Squashing) { 343 344 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 345 tid); 346 } 347 } 348 349 // @todo: make into updateProgress function 350 for (int tid=0; tid < numThreads; tid++) { 351 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 352 353 assert(instsInProgress[tid] >=0); 354 } 355 356} 357 358template<class Impl> 359void 360DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 361{ 362 // If status is Running or idle, 363 // call renameInsts() 364 // If status is Unblocking, 365 // buffer any instructions coming from decode 366 // continue trying to empty skid buffer 367 // check if stall conditions have passed 368 369 if (renameStatus[tid] == Blocked) { 370 ++renameBlockCycles; 371 } else if (renameStatus[tid] == Squashing) { 372 ++renameSquashCycles; 373 } else if (renameStatus[tid] == BarrierStall) { 374 ++renameBarrierCycles; 375 } 376 377 if (renameStatus[tid] == Running || 378 renameStatus[tid] == Idle) { 379 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 380 "stage.\n", tid); 381 382 renameInsts(tid); 383 } else if (renameStatus[tid] == Unblocking) { 384 renameInsts(tid); 385 386 ++renameUnblockCycles; 387 388 if (validInsts()) { 389 // Add the current inputs to the skid buffer so they can be 390 // reprocessed when this stage unblocks. 391 skidInsert(tid); 392 } 393 394 // If we switched over to blocking, then there's a potential for 395 // an overall status change. 396 status_change = unblock(tid) || status_change || blockThisCycle; 397 } 398} 399 400template <class Impl> 401void 402DefaultRename<Impl>::renameInsts(unsigned tid) 403{ 404 // Instructions can be either in the skid buffer or the queue of 405 // instructions coming from decode, depending on the status. 406 int insts_available = renameStatus[tid] == Unblocking ? 407 skidBuffer[tid].size() : insts[tid].size(); 408 409 // Check the decode queue to see if instructions are available. 410 // If there are no available instructions to rename, then do nothing. 411 if (insts_available == 0) { 412 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 413 tid); 414 // Should I change status to idle? 415 ++renameIdleCycles; 416 return; 417 } else if (renameStatus[tid] == Unblocking) { 418 ++renameUnblockCycles; 419 } else if (renameStatus[tid] == Running) { 420 ++renameRunCycles; 421 } 422 423 DynInstPtr inst; 424 425 // Will have to do a different calculation for the number of free 426 // entries. 427 int free_rob_entries = calcFreeROBEntries(tid); 428 int free_iq_entries = calcFreeIQEntries(tid); 429 int free_lsq_entries = calcFreeLSQEntries(tid); 430 int min_free_entries = free_rob_entries; 431 432 FullSource source = ROB; 433 434 if (free_iq_entries < min_free_entries) { 435 min_free_entries = free_iq_entries; 436 source = IQ; 437 } 438 439 if (free_lsq_entries < min_free_entries) { 440 min_free_entries = free_lsq_entries; 441 source = LSQ; 442 } 443 444 // Check if there's any space left. 445 if (min_free_entries <= 0) { 446 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 447 "entries.\n" 448 "ROB has %i free entries.\n" 449 "IQ has %i free entries.\n" 450 "LSQ has %i free entries.\n", 451 tid, 452 free_rob_entries, 453 free_iq_entries, 454 free_lsq_entries); 455 456 blockThisCycle = true; 457 458 block(tid); 459 460 incrFullStat(source); 461 462 return; 463 } else if (min_free_entries < insts_available) { 464 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 465 "%i insts available, but only %i insts can be " 466 "renamed due to ROB/IQ/LSQ limits.\n", 467 tid, insts_available, min_free_entries); 468 469 insts_available = min_free_entries; 470 471 blockThisCycle = true; 472 473 incrFullStat(source); 474 } 475 476 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 477 skidBuffer[tid] : insts[tid]; 478 479 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 480 "send iew.\n", tid, insts_available); 481 482 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 483 "dispatched to IQ last cycle.\n", 484 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 485 486 // Handle serializing the next instruction if necessary. 487 if (serializeOnNextInst[tid]) { 488 if (emptyROB[tid] && instsInProgress[tid] == 0) { 489 // ROB already empty; no need to serialize. 490 serializeOnNextInst[tid] = false; 491 } else if (!insts_to_rename.empty()) { 492 insts_to_rename.front()->setSerializeBefore(); 493 } 494 } 495 496 int renamed_insts = 0; 497 498 while (insts_available > 0 && toIEWIndex < renameWidth) { 499 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 500 501 assert(!insts_to_rename.empty()); 502 503 inst = insts_to_rename.front(); 504 505 insts_to_rename.pop_front(); 506 507 //Use skidBuffer with oldest instructions 508 if (renameStatus[tid] == Unblocking) { 509 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 510 "skidBuffer\n", 511 tid, inst->seqNum, inst->readPC()); 512 } 513 514 if (inst->isSquashed()) { 515 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 516 "squashed, skipping.\n", 517 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 518 519 ++renameSquashedInsts; 520 521 // Decrement how many instructions are available. 522 --insts_available; 523 524 continue; 525 } 526 527 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 528 "PC %#x.\n", 529 tid, inst->seqNum, inst->readPC()); 530 531 // Handle serializeAfter/serializeBefore instructions. 532 // serializeAfter marks the next instruction as serializeBefore. 533 // serializeBefore makes the instruction wait in rename until the ROB 534 // is empty. 535 if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { 536 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 537 538 if (!inst->isTempSerializeBefore()) 539 inst->setSerializeHandled(); 540 541 // Change status over to BarrierStall so that other stages know 542 // what this is blocked on. 543 renameStatus[tid] = BarrierStall; 544 545 barrierInst[tid] = inst; 546 547 blockThisCycle = true; 548 549 break; 550 } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { 551 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 552 553 inst->setSerializeHandled(); 554 555 serializeAfter(insts_to_rename, tid); 556 } 557 558 // Check here to make sure there are enough destination registers 559 // to rename to. Otherwise block. 560 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 561 DPRINTF(Rename, "Blocking due to lack of free " 562 "physical registers to rename to.\n"); 563 blockThisCycle = true; 564 565 ++renameFullRegistersEvents; 566 567 break; 568 } 569 570 renameSrcRegs(inst, inst->threadNumber); 571 572 renameDestRegs(inst, inst->threadNumber); 573 574 ++renamed_insts; 575 576 // Put instruction in rename queue. 577 toIEW->insts[toIEWIndex] = inst; 578 ++(toIEW->size); 579 580 // Increment which instruction we're on. 581 ++toIEWIndex; 582 583 ++renameRenamedInsts; 584 585 // Decrement how many instructions are available. 586 --insts_available; 587 } 588 589 instsInProgress[tid] += renamed_insts; 590 591 // If we wrote to the time buffer, record this. 592 if (toIEWIndex) { 593 wroteToTimeBuffer = true; 594 } 595 596 // Check if there's any instructions left that haven't yet been renamed. 597 // If so then block. 598 if (insts_available) { 599 blockThisCycle = true; 600 } 601 602 if (blockThisCycle) { 603 block(tid); 604 toDecode->renameUnblock[tid] = false; 605 } 606} 607 608template<class Impl> 609void 610DefaultRename<Impl>::skidInsert(unsigned tid) 611{ 612 DynInstPtr inst = NULL; 613 614 while (!insts[tid].empty()) { 615 inst = insts[tid].front(); 616 617 insts[tid].pop_front(); 618 619 assert(tid == inst->threadNumber); 620 621 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 622 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 623 624 skidBuffer[tid].push_back(inst); 625 } 626 627 if (skidBuffer[tid].size() > skidBufferMax) 628 panic("Skidbuffer Exceeded Max Size"); 629} 630 631template <class Impl> 632void 633DefaultRename<Impl>::sortInsts() 634{ 635 int insts_from_decode = fromDecode->size; 636 637 for (int i=0; i < numThreads; i++) 638 assert(insts[i].empty()); 639 640 for (int i = 0; i < insts_from_decode; ++i) { 641 DynInstPtr inst = fromDecode->insts[i]; 642 insts[inst->threadNumber].push_back(inst); 643 } 644} 645 646template<class Impl> 647bool 648DefaultRename<Impl>::skidsEmpty() 649{ 650 list<unsigned>::iterator threads = (*activeThreads).begin(); 651 652 while (threads != (*activeThreads).end()) { 653 if (!skidBuffer[*threads++].empty()) 654 return false; 655 } 656 657 return true; 658} 659 660template<class Impl> 661void 662DefaultRename<Impl>::updateStatus() 663{ 664 bool any_unblocking = false; 665 666 list<unsigned>::iterator threads = (*activeThreads).begin(); 667 668 threads = (*activeThreads).begin(); 669 670 while (threads != (*activeThreads).end()) { 671 unsigned tid = *threads++; 672 673 if (renameStatus[tid] == Unblocking) { 674 any_unblocking = true; 675 break; 676 } 677 } 678 679 // Rename will have activity if it's unblocking. 680 if (any_unblocking) { 681 if (_status == Inactive) { 682 _status = Active; 683 684 DPRINTF(Activity, "Activating stage.\n"); 685 686 cpu->activateStage(FullCPU::RenameIdx); 687 } 688 } else { 689 // If it's not unblocking, then rename will not have any internal 690 // activity. Switch it to inactive. 691 if (_status == Active) { 692 _status = Inactive; 693 DPRINTF(Activity, "Deactivating stage.\n"); 694 695 cpu->deactivateStage(FullCPU::RenameIdx); 696 } 697 } 698} 699 700template <class Impl> 701bool 702DefaultRename<Impl>::block(unsigned tid) 703{ 704 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 705 706 // Add the current inputs onto the skid buffer, so they can be 707 // reprocessed when this stage unblocks. 708 skidInsert(tid); 709 710 // Only signal backwards to block if the previous stages do not think 711 // rename is already blocked. 712 if (renameStatus[tid] != Blocked) { 713 if (renameStatus[tid] != Unblocking) { 714 toDecode->renameBlock[tid] = true; 715 toDecode->renameUnblock[tid] = false; 716 wroteToTimeBuffer = true; 717 } 718 719 // Rename can not go from BarrierStall to Blocked, otherwise it would 720 // not know to complete the barrier stall. 721 if (renameStatus[tid] != BarrierStall) { 722 // Set status to Blocked. 723 renameStatus[tid] = Blocked; 724 return true; 725 } 726 } 727 728 return false; 729} 730 731template <class Impl> 732bool 733DefaultRename<Impl>::unblock(unsigned tid) 734{ 735 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 736 737 // Rename is done unblocking if the skid buffer is empty. 738 if (skidBuffer[tid].empty() && renameStatus[tid] != BarrierStall) { 739 740 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 741 742 toDecode->renameUnblock[tid] = true; 743 wroteToTimeBuffer = true; 744 745 renameStatus[tid] = Running; 746 return true; 747 } 748 749 return false; 750} 751 752template <class Impl> 753void 754DefaultRename<Impl>::doSquash(unsigned tid) 755{ 756 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 757 758 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 759 760//#if FULL_SYSTEM 761// assert(!historyBuffer[tid].empty()); 762//#else 763 // After a syscall squashes everything, the history buffer may be empty 764 // but the ROB may still be squashing instructions. 765 if (historyBuffer[tid].empty()) { 766 return; 767 } 768//#endif // FULL_SYSTEM 769 770 // Go through the most recent instructions, undoing the mappings 771 // they did and freeing up the registers. 772 while (!historyBuffer[tid].empty() && 773 (*hb_it).instSeqNum > squashed_seq_num) { 774 assert(hb_it != historyBuffer[tid].end()); 775 776 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 777 "number %i.\n", tid, (*hb_it).instSeqNum); 778 779 // Tell the rename map to set the architected register to the 780 // previous physical register that it was renamed to. 781 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 782 783 // Put the renamed physical register back on the free list. 784 freeList->addReg(hb_it->newPhysReg); 785 786 historyBuffer[tid].erase(hb_it++); 787 788 ++renameUndoneMaps; 789 } 790} 791 792template<class Impl> 793void 794DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 795{ 796 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 797 "history buffer %u (size=%i), until [sn:%lli].\n", 798 tid, tid, historyBuffer[tid].size(), inst_seq_num); 799 800 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 801 802 --hb_it; 803 804 if (historyBuffer[tid].empty()) { 805 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 806 return; 807 } else if (hb_it->instSeqNum > inst_seq_num) { 808 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 809 "that a syscall happened recently.\n", tid); 810 return; 811 } 812 813 // Commit all the renames up until (and including) the committed sequence 814 // number. Some or even all of the committed instructions may not have 815 // rename histories if they did not have destination registers that were 816 // renamed. 817 while (!historyBuffer[tid].empty() && 818 hb_it != historyBuffer[tid].end() && 819 (*hb_it).instSeqNum <= inst_seq_num) { 820 821 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, sequence" 822 " number %i.\n", 823 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 824 825 freeList->addReg((*hb_it).prevPhysReg); 826 ++renameCommittedMaps; 827 828 historyBuffer[tid].erase(hb_it--); 829 } 830} 831 832template <class Impl> 833inline void 834DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 835{ 836 assert(renameMap[tid] != 0); 837 838 unsigned num_src_regs = inst->numSrcRegs(); 839 840 // Get the architectual register numbers from the source and 841 // destination operands, and redirect them to the right register. 842 // Will need to mark dependencies though. 843 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 844 RegIndex src_reg = inst->srcRegIdx(src_idx); 845 846 // Look up the source registers to get the phys. register they've 847 // been renamed to, and set the sources to those registers. 848 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 849 850 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 851 "physical reg %i.\n", tid, (int)src_reg, 852 (int)renamed_reg); 853 854 inst->renameSrcReg(src_idx, renamed_reg); 855 856 // See if the register is ready or not. 857 if (scoreboard->getReg(renamed_reg) == true) { 858 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 859 860 inst->markSrcRegReady(src_idx); 861 } 862 863 ++renameRenameLookups; 864 } 865} 866 867template <class Impl> 868inline void 869DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 870{ 871 typename RenameMap::RenameInfo rename_result; 872 873 unsigned num_dest_regs = inst->numDestRegs(); 874 875 // Rename the destination registers. 876 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 877 RegIndex dest_reg = inst->destRegIdx(dest_idx); 878 879 // Get the physical register that the destination will be 880 // renamed to. 881 rename_result = renameMap[tid]->rename(dest_reg); 882 883 //Mark Scoreboard entry as not ready 884 scoreboard->unsetReg(rename_result.first); 885 886 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 887 "reg %i.\n", tid, (int)dest_reg, 888 (int)rename_result.first); 889 890 // Record the rename information so that a history can be kept. 891 RenameHistory hb_entry(inst->seqNum, dest_reg, 892 rename_result.first, 893 rename_result.second); 894 895 historyBuffer[tid].push_front(hb_entry); 896 897 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 898 "[sn:%lli].\n",tid, 899 (*historyBuffer[tid].begin()).instSeqNum); 900 901 // Tell the instruction to rename the appropriate destination 902 // register (dest_idx) to the new physical register 903 // (rename_result.first), and record the previous physical 904 // register that the same logical register was renamed to 905 // (rename_result.second). 906 inst->renameDestReg(dest_idx, 907 rename_result.first, 908 rename_result.second); 909 910 ++renameRenamedOperands; 911 } 912} 913 914template <class Impl> 915inline int 916DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 917{ 918 int num_free = freeEntries[tid].robEntries - 919 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 920 921 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 922 923 return num_free; 924} 925 926template <class Impl> 927inline int 928DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 929{ 930 int num_free = freeEntries[tid].iqEntries - 931 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 932 933 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 934 935 return num_free; 936} 937 938template <class Impl> 939inline int 940DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 941{ 942 int num_free = freeEntries[tid].lsqEntries - 943 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 944 945 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 946 947 return num_free; 948} 949 950template <class Impl> 951unsigned 952DefaultRename<Impl>::validInsts() 953{ 954 unsigned inst_count = 0; 955 956 for (int i=0; i<fromDecode->size; i++) { 957 if (!fromDecode->insts[i]->squashed) 958 inst_count++; 959 } 960 961 return inst_count; 962} 963 964template <class Impl> 965void 966DefaultRename<Impl>::readStallSignals(unsigned tid) 967{ 968 if (fromIEW->iewBlock[tid]) { 969 stalls[tid].iew = true; 970 } 971 972 if (fromIEW->iewUnblock[tid]) { 973 assert(stalls[tid].iew); 974 stalls[tid].iew = false; 975 } 976 977 if (fromCommit->commitBlock[tid]) { 978 stalls[tid].commit = true; 979 } 980 981 if (fromCommit->commitUnblock[tid]) { 982 assert(stalls[tid].commit); 983 stalls[tid].commit = false; 984 } 985} 986 987template <class Impl> 988bool 989DefaultRename<Impl>::checkStall(unsigned tid) 990{ 991 bool ret_val = false; 992 993 if (stalls[tid].iew) { 994 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 995 ret_val = true; 996 } else if (stalls[tid].commit) { 997 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 998 ret_val = true; 999 } else if (calcFreeROBEntries(tid) <= 0) { 1000 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1001 ret_val = true; 1002 } else if (calcFreeIQEntries(tid) <= 0) { 1003 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1004 ret_val = true; 1005 } else if (calcFreeLSQEntries(tid) <= 0) { 1006 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1007 ret_val = true; 1008 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1009 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1010 ret_val = true; 1011 } else if (renameStatus[tid] == BarrierStall && 1012 (!emptyROB[tid] || instsInProgress[tid])) { 1013 DPRINTF(Rename,"[tid:%i]: Stall: Barrier stall and ROB is not " 1014 "empty.\n", 1015 tid); 1016 ret_val = true; 1017 } 1018 1019 return ret_val; 1020} 1021 1022template <class Impl> 1023void 1024DefaultRename<Impl>::readFreeEntries(unsigned tid) 1025{ 1026 bool updated = false; 1027 if (fromIEW->iewInfo[tid].usedIQ) { 1028 freeEntries[tid].iqEntries = 1029 fromIEW->iewInfo[tid].freeIQEntries; 1030 updated = true; 1031 } 1032 1033 if (fromIEW->iewInfo[tid].usedLSQ) { 1034 freeEntries[tid].lsqEntries = 1035 fromIEW->iewInfo[tid].freeLSQEntries; 1036 updated = true; 1037 } 1038 1039 if (fromCommit->commitInfo[tid].usedROB) { 1040 freeEntries[tid].robEntries = 1041 fromCommit->commitInfo[tid].freeROBEntries; 1042 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1043 updated = true; 1044 } 1045 1046 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1047 tid, 1048 freeEntries[tid].iqEntries, 1049 freeEntries[tid].robEntries, 1050 freeEntries[tid].lsqEntries); 1051 1052 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1053 tid, instsInProgress[tid]); 1054} 1055 1056template <class Impl> 1057bool 1058DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1059{ 1060 // Check if there's a squash signal, squash if there is 1061 // Check stall signals, block if necessary. 1062 // If status was blocked 1063 // check if stall conditions have passed 1064 // if so then go to unblocking 1065 // If status was Squashing 1066 // check if squashing is not high. Switch to running this cycle. 1067 // If status was barrier stall 1068 // check if ROB is empty and no insts are in flight to the ROB 1069 1070 readFreeEntries(tid); 1071 readStallSignals(tid); 1072 1073 if (fromCommit->commitInfo[tid].squash) { 1074 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1075 "commit.\n", tid); 1076 1077 squash(tid); 1078 1079 return true; 1080 } 1081 1082 if (fromCommit->commitInfo[tid].robSquashing) { 1083 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1084 1085 renameStatus[tid] = Squashing; 1086 1087 return true; 1088 } 1089 1090 if (checkStall(tid)) { 1091 return block(tid); 1092 } 1093 1094 if (renameStatus[tid] == Blocked) { 1095 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1096 tid); 1097 1098 renameStatus[tid] = Unblocking; 1099 1100 unblock(tid); 1101 1102 return true; 1103 } 1104 1105 if (renameStatus[tid] == Squashing) { 1106 // Switch status to running if rename isn't being told to block or 1107 // squash this cycle. 1108 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1109 tid); 1110 1111 renameStatus[tid] = Running; 1112 1113 return false; 1114 } 1115 1116 if (renameStatus[tid] == BarrierStall) { 1117 // Stall ends once the ROB is free. 1118 DPRINTF(Rename, "[tid:%u]: Done with barrier stall, switching to " 1119 "unblocking.\n", tid); 1120 1121 DynInstPtr barr_inst = barrierInst[tid]; 1122 1123 renameStatus[tid] = Unblocking; 1124 1125 unblock(tid); 1126 1127 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1128 "PC %#x.\n", 1129 tid, barr_inst->seqNum, barr_inst->readPC()); 1130 1131 // Put instruction into queue here. 1132 barr_inst->clearSerializeBefore(); 1133 1134 if (!skidBuffer[tid].empty()) { 1135 skidBuffer[tid].push_front(barr_inst); 1136 } else { 1137 insts[tid].push_front(barr_inst); 1138 } 1139 1140 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1141 " Adding to front of list.", tid); 1142 1143 barrierInst[tid] = NULL; 1144 1145 return true; 1146 } 1147 1148 // If we've reached this point, we have not gotten any signals that 1149 // cause rename to change its status. Rename remains the same as before. 1150 return false; 1151} 1152 1153template<class Impl> 1154void 1155DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1156 unsigned tid) 1157{ 1158 if (inst_list.empty()) { 1159 // Mark a bit to say that I must serialize on the next instruction. 1160 serializeOnNextInst[tid] = true; 1161 return; 1162 } 1163 1164 // Set the next instruction as serializing. 1165 inst_list.front()->setSerializeBefore(); 1166} 1167 1168template <class Impl> 1169inline void 1170DefaultRename<Impl>::incrFullStat(const FullSource &source) 1171{ 1172 switch (source) { 1173 case ROB: 1174 ++renameROBFullEvents; 1175 break; 1176 case IQ: 1177 ++renameIQFullEvents; 1178 break; 1179 case LSQ: 1180 ++renameLSQFullEvents; 1181 break; 1182 default: 1183 panic("Rename full stall stat should be incremented for a reason!"); 1184 break; 1185 } 1186} 1187 1188template <class Impl> 1189void 1190DefaultRename<Impl>::dumpHistory() 1191{ 1192 typename list<RenameHistory>::iterator buf_it; 1193 1194 for (int i = 0; i < numThreads; i++) { 1195 1196 buf_it = historyBuffer[i].begin(); 1197 1198 while (buf_it != historyBuffer[i].end()) { 1199 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1200 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1201 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1202 1203 buf_it++; 1204 } 1205 } 1206} 1207