rename_impl.hh revision 13831:4fba790d88be 
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64    : cpu(_cpu),
65      iewToRenameDelay(params->iewToRenameDelay),
66      decodeToRenameDelay(params->decodeToRenameDelay),
67      commitToRenameDelay(params->commitToRenameDelay),
68      renameWidth(params->renameWidth),
69      commitWidth(params->commitWidth),
70      numThreads(params->numThreads)
71{
72    if (renameWidth > Impl::MaxWidth)
73        fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
74             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
75             renameWidth, static_cast<int>(Impl::MaxWidth));
76
77    // @todo: Make into a parameter.
78    skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
79    for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
80        renameStatus[tid] = Idle;
81        renameMap[tid] = nullptr;
82        instsInProgress[tid] = 0;
83        loadsInProgress[tid] = 0;
84        storesInProgress[tid] = 0;
85        freeEntries[tid] = {0, 0, 0, 0};
86        emptyROB[tid] = true;
87        stalls[tid] = {false, false};
88        serializeInst[tid] = nullptr;
89        serializeOnNextInst[tid] = false;
90    }
91}
92
93template <class Impl>
94std::string
95DefaultRename<Impl>::name() const
96{
97    return cpu->name() + ".rename";
98}
99
100template <class Impl>
101void
102DefaultRename<Impl>::regStats()
103{
104    renameSquashCycles
105        .name(name() + ".SquashCycles")
106        .desc("Number of cycles rename is squashing")
107        .prereq(renameSquashCycles);
108    renameIdleCycles
109        .name(name() + ".IdleCycles")
110        .desc("Number of cycles rename is idle")
111        .prereq(renameIdleCycles);
112    renameBlockCycles
113        .name(name() + ".BlockCycles")
114        .desc("Number of cycles rename is blocking")
115        .prereq(renameBlockCycles);
116    renameSerializeStallCycles
117        .name(name() + ".serializeStallCycles")
118        .desc("count of cycles rename stalled for serializing inst")
119        .flags(Stats::total);
120    renameRunCycles
121        .name(name() + ".RunCycles")
122        .desc("Number of cycles rename is running")
123        .prereq(renameIdleCycles);
124    renameUnblockCycles
125        .name(name() + ".UnblockCycles")
126        .desc("Number of cycles rename is unblocking")
127        .prereq(renameUnblockCycles);
128    renameRenamedInsts
129        .name(name() + ".RenamedInsts")
130        .desc("Number of instructions processed by rename")
131        .prereq(renameRenamedInsts);
132    renameSquashedInsts
133        .name(name() + ".SquashedInsts")
134        .desc("Number of squashed instructions processed by rename")
135        .prereq(renameSquashedInsts);
136    renameROBFullEvents
137        .name(name() + ".ROBFullEvents")
138        .desc("Number of times rename has blocked due to ROB full")
139        .prereq(renameROBFullEvents);
140    renameIQFullEvents
141        .name(name() + ".IQFullEvents")
142        .desc("Number of times rename has blocked due to IQ full")
143        .prereq(renameIQFullEvents);
144    renameLQFullEvents
145        .name(name() + ".LQFullEvents")
146        .desc("Number of times rename has blocked due to LQ full")
147        .prereq(renameLQFullEvents);
148    renameSQFullEvents
149        .name(name() + ".SQFullEvents")
150        .desc("Number of times rename has blocked due to SQ full")
151        .prereq(renameSQFullEvents);
152    renameFullRegistersEvents
153        .name(name() + ".FullRegisterEvents")
154        .desc("Number of times there has been no free registers")
155        .prereq(renameFullRegistersEvents);
156    renameRenamedOperands
157        .name(name() + ".RenamedOperands")
158        .desc("Number of destination operands rename has renamed")
159        .prereq(renameRenamedOperands);
160    renameRenameLookups
161        .name(name() + ".RenameLookups")
162        .desc("Number of register rename lookups that rename has made")
163        .prereq(renameRenameLookups);
164    renameCommittedMaps
165        .name(name() + ".CommittedMaps")
166        .desc("Number of HB maps that are committed")
167        .prereq(renameCommittedMaps);
168    renameUndoneMaps
169        .name(name() + ".UndoneMaps")
170        .desc("Number of HB maps that are undone due to squashing")
171        .prereq(renameUndoneMaps);
172    renamedSerializing
173        .name(name() + ".serializingInsts")
174        .desc("count of serializing insts renamed")
175        .flags(Stats::total)
176        ;
177    renamedTempSerializing
178        .name(name() + ".tempSerializingInsts")
179        .desc("count of temporary serializing insts renamed")
180        .flags(Stats::total)
181        ;
182    renameSkidInsts
183        .name(name() + ".skidInsts")
184        .desc("count of insts added to the skid buffer")
185        .flags(Stats::total)
186        ;
187    intRenameLookups
188        .name(name() + ".int_rename_lookups")
189        .desc("Number of integer rename lookups")
190        .prereq(intRenameLookups);
191    fpRenameLookups
192        .name(name() + ".fp_rename_lookups")
193        .desc("Number of floating rename lookups")
194        .prereq(fpRenameLookups);
195    vecRenameLookups
196        .name(name() + ".vec_rename_lookups")
197        .desc("Number of vector rename lookups")
198        .prereq(vecRenameLookups);
199    vecPredRenameLookups
200        .name(name() + ".vec_pred_rename_lookups")
201        .desc("Number of vector predicate rename lookups")
202        .prereq(vecPredRenameLookups);
203}
204
205template <class Impl>
206void
207DefaultRename<Impl>::regProbePoints()
208{
209    ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
210    ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),
211                                                        "SquashInRename");
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
217{
218    timeBuffer = tb_ptr;
219
220    // Setup wire to read information from time buffer, from IEW stage.
221    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
222
223    // Setup wire to read infromation from time buffer, from commit stage.
224    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
225
226    // Setup wire to write information to previous stages.
227    toDecode = timeBuffer->getWire(0);
228}
229
230template <class Impl>
231void
232DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
233{
234    renameQueue = rq_ptr;
235
236    // Setup wire to write information to future stages.
237    toIEW = renameQueue->getWire(0);
238}
239
240template <class Impl>
241void
242DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
243{
244    decodeQueue = dq_ptr;
245
246    // Setup wire to get information from decode.
247    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
248}
249
250template <class Impl>
251void
252DefaultRename<Impl>::startupStage()
253{
254    resetStage();
255}
256
257template <class Impl>
258void
259DefaultRename<Impl>::clearStates(ThreadID tid)
260{
261    renameStatus[tid] = Idle;
262
263    freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
264    freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
265    freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid);
266    freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
267    emptyROB[tid] = true;
268
269    stalls[tid].iew = false;
270    serializeInst[tid] = NULL;
271
272    instsInProgress[tid] = 0;
273    loadsInProgress[tid] = 0;
274    storesInProgress[tid] = 0;
275
276    serializeOnNextInst[tid] = false;
277}
278
279template <class Impl>
280void
281DefaultRename<Impl>::resetStage()
282{
283    _status = Inactive;
284
285    resumeSerialize = false;
286    resumeUnblocking = false;
287
288    // Grab the number of free entries directly from the stages.
289    for (ThreadID tid = 0; tid < numThreads; tid++) {
290        renameStatus[tid] = Idle;
291
292        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
293        freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
294        freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid);
295        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
296        emptyROB[tid] = true;
297
298        stalls[tid].iew = false;
299        serializeInst[tid] = NULL;
300
301        instsInProgress[tid] = 0;
302        loadsInProgress[tid] = 0;
303        storesInProgress[tid] = 0;
304
305        serializeOnNextInst[tid] = false;
306    }
307}
308
309template<class Impl>
310void
311DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
312{
313    activeThreads = at_ptr;
314}
315
316
317template <class Impl>
318void
319DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
320{
321    for (ThreadID tid = 0; tid < numThreads; tid++)
322        renameMap[tid] = &rm_ptr[tid];
323}
324
325template <class Impl>
326void
327DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
328{
329    freeList = fl_ptr;
330}
331
332template<class Impl>
333void
334DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
335{
336    scoreboard = _scoreboard;
337}
338
339template <class Impl>
340bool
341DefaultRename<Impl>::isDrained() const
342{
343    for (ThreadID tid = 0; tid < numThreads; tid++) {
344        if (instsInProgress[tid] != 0 ||
345            !historyBuffer[tid].empty() ||
346            !skidBuffer[tid].empty() ||
347            !insts[tid].empty() ||
348            (renameStatus[tid] != Idle && renameStatus[tid] != Running))
349            return false;
350    }
351    return true;
352}
353
354template <class Impl>
355void
356DefaultRename<Impl>::takeOverFrom()
357{
358    resetStage();
359}
360
361template <class Impl>
362void
363DefaultRename<Impl>::drainSanityCheck() const
364{
365    for (ThreadID tid = 0; tid < numThreads; tid++) {
366        assert(historyBuffer[tid].empty());
367        assert(insts[tid].empty());
368        assert(skidBuffer[tid].empty());
369        assert(instsInProgress[tid] == 0);
370    }
371}
372
373template <class Impl>
374void
375DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
376{
377    DPRINTF(Rename, "[tid:%i] [squash sn:%llu] Squashing instructions.\n",
378        tid,squash_seq_num);
379
380    // Clear the stall signal if rename was blocked or unblocking before.
381    // If it still needs to block, the blocking should happen the next
382    // cycle and there should be space to hold everything due to the squash.
383    if (renameStatus[tid] == Blocked ||
384        renameStatus[tid] == Unblocking) {
385        toDecode->renameUnblock[tid] = 1;
386
387        resumeSerialize = false;
388        serializeInst[tid] = NULL;
389    } else if (renameStatus[tid] == SerializeStall) {
390        if (serializeInst[tid]->seqNum <= squash_seq_num) {
391            DPRINTF(Rename, "[tid:%i] [squash sn:%llu] "
392                "Rename will resume serializing after squash\n",
393                tid,squash_seq_num);
394            resumeSerialize = true;
395            assert(serializeInst[tid]);
396        } else {
397            resumeSerialize = false;
398            toDecode->renameUnblock[tid] = 1;
399
400            serializeInst[tid] = NULL;
401        }
402    }
403
404    // Set the status to Squashing.
405    renameStatus[tid] = Squashing;
406
407    // Squash any instructions from decode.
408    for (int i=0; i<fromDecode->size; i++) {
409        if (fromDecode->insts[i]->threadNumber == tid &&
410            fromDecode->insts[i]->seqNum > squash_seq_num) {
411            fromDecode->insts[i]->setSquashed();
412            wroteToTimeBuffer = true;
413        }
414
415    }
416
417    // Clear the instruction list and skid buffer in case they have any
418    // insts in them.
419    insts[tid].clear();
420
421    // Clear the skid buffer in case it has any data in it.
422    skidBuffer[tid].clear();
423
424    doSquash(squash_seq_num, tid);
425}
426
427template <class Impl>
428void
429DefaultRename<Impl>::tick()
430{
431    wroteToTimeBuffer = false;
432
433    blockThisCycle = false;
434
435    bool status_change = false;
436
437    toIEWIndex = 0;
438
439    sortInsts();
440
441    list<ThreadID>::iterator threads = activeThreads->begin();
442    list<ThreadID>::iterator end = activeThreads->end();
443
444    // Check stall and squash signals.
445    while (threads != end) {
446        ThreadID tid = *threads++;
447
448        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
449
450        status_change = checkSignalsAndUpdate(tid) || status_change;
451
452        rename(status_change, tid);
453    }
454
455    if (status_change) {
456        updateStatus();
457    }
458
459    if (wroteToTimeBuffer) {
460        DPRINTF(Activity, "Activity this cycle.\n");
461        cpu->activityThisCycle();
462    }
463
464    threads = activeThreads->begin();
465
466    while (threads != end) {
467        ThreadID tid = *threads++;
468
469        // If we committed this cycle then doneSeqNum will be > 0
470        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
471            !fromCommit->commitInfo[tid].squash &&
472            renameStatus[tid] != Squashing) {
473
474            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
475                                  tid);
476        }
477    }
478
479    // @todo: make into updateProgress function
480    for (ThreadID tid = 0; tid < numThreads; tid++) {
481        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
482        loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ;
483        storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ;
484        assert(loadsInProgress[tid] >= 0);
485        assert(storesInProgress[tid] >= 0);
486        assert(instsInProgress[tid] >=0);
487    }
488
489}
490
491template<class Impl>
492void
493DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
494{
495    // If status is Running or idle,
496    //     call renameInsts()
497    // If status is Unblocking,
498    //     buffer any instructions coming from decode
499    //     continue trying to empty skid buffer
500    //     check if stall conditions have passed
501
502    if (renameStatus[tid] == Blocked) {
503        ++renameBlockCycles;
504    } else if (renameStatus[tid] == Squashing) {
505        ++renameSquashCycles;
506    } else if (renameStatus[tid] == SerializeStall) {
507        ++renameSerializeStallCycles;
508        // If we are currently in SerializeStall and resumeSerialize
509        // was set, then that means that we are resuming serializing
510        // this cycle.  Tell the previous stages to block.
511        if (resumeSerialize) {
512            resumeSerialize = false;
513            block(tid);
514            toDecode->renameUnblock[tid] = false;
515        }
516    } else if (renameStatus[tid] == Unblocking) {
517        if (resumeUnblocking) {
518            block(tid);
519            resumeUnblocking = false;
520            toDecode->renameUnblock[tid] = false;
521        }
522    }
523
524    if (renameStatus[tid] == Running ||
525        renameStatus[tid] == Idle) {
526        DPRINTF(Rename,
527                "[tid:%i] "
528                "Not blocked, so attempting to run stage.\n",
529                tid);
530
531        renameInsts(tid);
532    } else if (renameStatus[tid] == Unblocking) {
533        renameInsts(tid);
534
535        if (validInsts()) {
536            // Add the current inputs to the skid buffer so they can be
537            // reprocessed when this stage unblocks.
538            skidInsert(tid);
539        }
540
541        // If we switched over to blocking, then there's a potential for
542        // an overall status change.
543        status_change = unblock(tid) || status_change || blockThisCycle;
544    }
545}
546
547template <class Impl>
548void
549DefaultRename<Impl>::renameInsts(ThreadID tid)
550{
551    // Instructions can be either in the skid buffer or the queue of
552    // instructions coming from decode, depending on the status.
553    int insts_available = renameStatus[tid] == Unblocking ?
554        skidBuffer[tid].size() : insts[tid].size();
555
556    // Check the decode queue to see if instructions are available.
557    // If there are no available instructions to rename, then do nothing.
558    if (insts_available == 0) {
559        DPRINTF(Rename, "[tid:%i] Nothing to do, breaking out early.\n",
560                tid);
561        // Should I change status to idle?
562        ++renameIdleCycles;
563        return;
564    } else if (renameStatus[tid] == Unblocking) {
565        ++renameUnblockCycles;
566    } else if (renameStatus[tid] == Running) {
567        ++renameRunCycles;
568    }
569
570    // Will have to do a different calculation for the number of free
571    // entries.
572    int free_rob_entries = calcFreeROBEntries(tid);
573    int free_iq_entries  = calcFreeIQEntries(tid);
574    int min_free_entries = free_rob_entries;
575
576    FullSource source = ROB;
577
578    if (free_iq_entries < min_free_entries) {
579        min_free_entries = free_iq_entries;
580        source = IQ;
581    }
582
583    // Check if there's any space left.
584    if (min_free_entries <= 0) {
585        DPRINTF(Rename,
586                "[tid:%i] Blocking due to no free ROB/IQ/ entries.\n"
587                "ROB has %i free entries.\n"
588                "IQ has %i free entries.\n",
589                tid, free_rob_entries, free_iq_entries);
590
591        blockThisCycle = true;
592
593        block(tid);
594
595        incrFullStat(source);
596
597        return;
598    } else if (min_free_entries < insts_available) {
599        DPRINTF(Rename,
600                "[tid:%i] "
601                "Will have to block this cycle. "
602                "%i insts available, "
603                "but only %i insts can be renamed due to ROB/IQ/LSQ limits.\n",
604                tid, insts_available, min_free_entries);
605
606        insts_available = min_free_entries;
607
608        blockThisCycle = true;
609
610        incrFullStat(source);
611    }
612
613    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
614        skidBuffer[tid] : insts[tid];
615
616    DPRINTF(Rename,
617            "[tid:%i] "
618            "%i available instructions to send iew.\n",
619            tid, insts_available);
620
621    DPRINTF(Rename,
622            "[tid:%i] "
623            "%i insts pipelining from Rename | "
624            "%i insts dispatched to IQ last cycle.\n",
625            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
626
627    // Handle serializing the next instruction if necessary.
628    if (serializeOnNextInst[tid]) {
629        if (emptyROB[tid] && instsInProgress[tid] == 0) {
630            // ROB already empty; no need to serialize.
631            serializeOnNextInst[tid] = false;
632        } else if (!insts_to_rename.empty()) {
633            insts_to_rename.front()->setSerializeBefore();
634        }
635    }
636
637    int renamed_insts = 0;
638
639    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
640        DPRINTF(Rename, "[tid:%i] Sending instructions to IEW.\n", tid);
641
642        assert(!insts_to_rename.empty());
643
644        DynInstPtr inst = insts_to_rename.front();
645
646        //For all kind of instructions, check ROB and IQ first
647        //For load instruction, check LQ size and take into account the inflight loads
648        //For store instruction, check SQ size and take into account the inflight stores
649
650        if (inst->isLoad()) {
651            if (calcFreeLQEntries(tid) <= 0) {
652                DPRINTF(Rename, "[tid:%i] Cannot rename due to no free LQ\n");
653                source = LQ;
654                incrFullStat(source);
655                break;
656            }
657        }
658
659        if (inst->isStore() || inst->isAtomic()) {
660            if (calcFreeSQEntries(tid) <= 0) {
661                DPRINTF(Rename, "[tid:%i] Cannot rename due to no free SQ\n");
662                source = SQ;
663                incrFullStat(source);
664                break;
665            }
666        }
667
668        insts_to_rename.pop_front();
669
670        if (renameStatus[tid] == Unblocking) {
671            DPRINTF(Rename,
672                    "[tid:%i] "
673                    "Removing [sn:%llu] PC:%s from rename skidBuffer\n",
674                    tid, inst->seqNum, inst->pcState());
675        }
676
677        if (inst->isSquashed()) {
678            DPRINTF(Rename,
679                    "[tid:%i] "
680                    "instruction %i with PC %s is squashed, skipping.\n",
681                    tid, inst->seqNum, inst->pcState());
682
683            ++renameSquashedInsts;
684
685            // Decrement how many instructions are available.
686            --insts_available;
687
688            continue;
689        }
690
691        DPRINTF(Rename,
692                "[tid:%i] "
693                "Processing instruction [sn:%llu] with PC %s.\n",
694                tid, inst->seqNum, inst->pcState());
695
696        // Check here to make sure there are enough destination registers
697        // to rename to.  Otherwise block.
698        if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
699                                       inst->numFPDestRegs(),
700                                       inst->numVecDestRegs(),
701                                       inst->numVecElemDestRegs(),
702                                       inst->numVecPredDestRegs(),
703                                       inst->numCCDestRegs())) {
704            DPRINTF(Rename,
705                    "Blocking due to "
706                    " lack of free physical registers to rename to.\n");
707            blockThisCycle = true;
708            insts_to_rename.push_front(inst);
709            ++renameFullRegistersEvents;
710
711            break;
712        }
713
714        // Handle serializeAfter/serializeBefore instructions.
715        // serializeAfter marks the next instruction as serializeBefore.
716        // serializeBefore makes the instruction wait in rename until the ROB
717        // is empty.
718
719        // In this model, IPR accesses are serialize before
720        // instructions, and store conditionals are serialize after
721        // instructions.  This is mainly due to lack of support for
722        // out-of-order operations of either of those classes of
723        // instructions.
724        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
725            !inst->isSerializeHandled()) {
726            DPRINTF(Rename, "Serialize before instruction encountered.\n");
727
728            if (!inst->isTempSerializeBefore()) {
729                renamedSerializing++;
730                inst->setSerializeHandled();
731            } else {
732                renamedTempSerializing++;
733            }
734
735            // Change status over to SerializeStall so that other stages know
736            // what this is blocked on.
737            renameStatus[tid] = SerializeStall;
738
739            serializeInst[tid] = inst;
740
741            blockThisCycle = true;
742
743            break;
744        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
745                   !inst->isSerializeHandled()) {
746            DPRINTF(Rename, "Serialize after instruction encountered.\n");
747
748            renamedSerializing++;
749
750            inst->setSerializeHandled();
751
752            serializeAfter(insts_to_rename, tid);
753        }
754
755        renameSrcRegs(inst, inst->threadNumber);
756
757        renameDestRegs(inst, inst->threadNumber);
758
759        if (inst->isAtomic() || inst->isStore()) {
760            storesInProgress[tid]++;
761        } else if (inst->isLoad()) {
762            loadsInProgress[tid]++;
763        }
764
765        ++renamed_insts;
766        // Notify potential listeners that source and destination registers for
767        // this instruction have been renamed.
768        ppRename->notify(inst);
769
770        // Put instruction in rename queue.
771        toIEW->insts[toIEWIndex] = inst;
772        ++(toIEW->size);
773
774        // Increment which instruction we're on.
775        ++toIEWIndex;
776
777        // Decrement how many instructions are available.
778        --insts_available;
779    }
780
781    instsInProgress[tid] += renamed_insts;
782    renameRenamedInsts += renamed_insts;
783
784    // If we wrote to the time buffer, record this.
785    if (toIEWIndex) {
786        wroteToTimeBuffer = true;
787    }
788
789    // Check if there's any instructions left that haven't yet been renamed.
790    // If so then block.
791    if (insts_available) {
792        blockThisCycle = true;
793    }
794
795    if (blockThisCycle) {
796        block(tid);
797        toDecode->renameUnblock[tid] = false;
798    }
799}
800
801template<class Impl>
802void
803DefaultRename<Impl>::skidInsert(ThreadID tid)
804{
805    DynInstPtr inst = NULL;
806
807    while (!insts[tid].empty()) {
808        inst = insts[tid].front();
809
810        insts[tid].pop_front();
811
812        assert(tid == inst->threadNumber);
813
814        DPRINTF(Rename, "[tid:%i] Inserting [sn:%llu] PC: %s into Rename "
815                "skidBuffer\n", tid, inst->seqNum, inst->pcState());
816
817        ++renameSkidInsts;
818
819        skidBuffer[tid].push_back(inst);
820    }
821
822    if (skidBuffer[tid].size() > skidBufferMax)
823    {
824        typename InstQueue::iterator it;
825        warn("Skidbuffer contents:\n");
826        for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
827        {
828            warn("[tid:%i] %s [sn:%llu].\n", tid,
829                    (*it)->staticInst->disassemble(inst->instAddr()),
830                    (*it)->seqNum);
831        }
832        panic("Skidbuffer Exceeded Max Size");
833    }
834}
835
836template <class Impl>
837void
838DefaultRename<Impl>::sortInsts()
839{
840    int insts_from_decode = fromDecode->size;
841    for (int i = 0; i < insts_from_decode; ++i) {
842        const DynInstPtr &inst = fromDecode->insts[i];
843        insts[inst->threadNumber].push_back(inst);
844#if TRACING_ON
845        if (DTRACE(O3PipeView)) {
846            inst->renameTick = curTick() - inst->fetchTick;
847        }
848#endif
849    }
850}
851
852template<class Impl>
853bool
854DefaultRename<Impl>::skidsEmpty()
855{
856    list<ThreadID>::iterator threads = activeThreads->begin();
857    list<ThreadID>::iterator end = activeThreads->end();
858
859    while (threads != end) {
860        ThreadID tid = *threads++;
861
862        if (!skidBuffer[tid].empty())
863            return false;
864    }
865
866    return true;
867}
868
869template<class Impl>
870void
871DefaultRename<Impl>::updateStatus()
872{
873    bool any_unblocking = false;
874
875    list<ThreadID>::iterator threads = activeThreads->begin();
876    list<ThreadID>::iterator end = activeThreads->end();
877
878    while (threads != end) {
879        ThreadID tid = *threads++;
880
881        if (renameStatus[tid] == Unblocking) {
882            any_unblocking = true;
883            break;
884        }
885    }
886
887    // Rename will have activity if it's unblocking.
888    if (any_unblocking) {
889        if (_status == Inactive) {
890            _status = Active;
891
892            DPRINTF(Activity, "Activating stage.\n");
893
894            cpu->activateStage(O3CPU::RenameIdx);
895        }
896    } else {
897        // If it's not unblocking, then rename will not have any internal
898        // activity.  Switch it to inactive.
899        if (_status == Active) {
900            _status = Inactive;
901            DPRINTF(Activity, "Deactivating stage.\n");
902
903            cpu->deactivateStage(O3CPU::RenameIdx);
904        }
905    }
906}
907
908template <class Impl>
909bool
910DefaultRename<Impl>::block(ThreadID tid)
911{
912    DPRINTF(Rename, "[tid:%i] Blocking.\n", tid);
913
914    // Add the current inputs onto the skid buffer, so they can be
915    // reprocessed when this stage unblocks.
916    skidInsert(tid);
917
918    // Only signal backwards to block if the previous stages do not think
919    // rename is already blocked.
920    if (renameStatus[tid] != Blocked) {
921        // If resumeUnblocking is set, we unblocked during the squash,
922        // but now we're have unblocking status. We need to tell earlier
923        // stages to block.
924        if (resumeUnblocking || renameStatus[tid] != Unblocking) {
925            toDecode->renameBlock[tid] = true;
926            toDecode->renameUnblock[tid] = false;
927            wroteToTimeBuffer = true;
928        }
929
930        // Rename can not go from SerializeStall to Blocked, otherwise
931        // it would not know to complete the serialize stall.
932        if (renameStatus[tid] != SerializeStall) {
933            // Set status to Blocked.
934            renameStatus[tid] = Blocked;
935            return true;
936        }
937    }
938
939    return false;
940}
941
942template <class Impl>
943bool
944DefaultRename<Impl>::unblock(ThreadID tid)
945{
946    DPRINTF(Rename, "[tid:%i] Trying to unblock.\n", tid);
947
948    // Rename is done unblocking if the skid buffer is empty.
949    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
950
951        DPRINTF(Rename, "[tid:%i] Done unblocking.\n", tid);
952
953        toDecode->renameUnblock[tid] = true;
954        wroteToTimeBuffer = true;
955
956        renameStatus[tid] = Running;
957        return true;
958    }
959
960    return false;
961}
962
963template <class Impl>
964void
965DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
966{
967    typename std::list<RenameHistory>::iterator hb_it =
968        historyBuffer[tid].begin();
969
970    // After a syscall squashes everything, the history buffer may be empty
971    // but the ROB may still be squashing instructions.
972    // Go through the most recent instructions, undoing the mappings
973    // they did and freeing up the registers.
974    while (!historyBuffer[tid].empty() &&
975           hb_it->instSeqNum > squashed_seq_num) {
976        assert(hb_it != historyBuffer[tid].end());
977
978        DPRINTF(Rename, "[tid:%i] Removing history entry with sequence "
979                "number %i.\n", tid, hb_it->instSeqNum);
980
981        // Undo the rename mapping only if it was really a change.
982        // Special regs that are not really renamed (like misc regs
983        // and the zero reg) can be recognized because the new mapping
984        // is the same as the old one.  While it would be merely a
985        // waste of time to update the rename table, we definitely
986        // don't want to put these on the free list.
987        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
988            // Tell the rename map to set the architected register to the
989            // previous physical register that it was renamed to.
990            renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
991
992            // Put the renamed physical register back on the free list.
993            freeList->addReg(hb_it->newPhysReg);
994        }
995
996        // Notify potential listeners that the register mapping needs to be
997        // removed because the instruction it was mapped to got squashed. Note
998        // that this is done before hb_it is incremented.
999        ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum,
1000                                                hb_it->newPhysReg));
1001
1002        historyBuffer[tid].erase(hb_it++);
1003
1004        ++renameUndoneMaps;
1005    }
1006
1007    // Check if we need to change vector renaming mode after squashing
1008    cpu->switchRenameMode(tid, freeList);
1009}
1010
1011template<class Impl>
1012void
1013DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
1014{
1015    DPRINTF(Rename, "[tid:%i] Removing a committed instruction from the "
1016            "history buffer %u (size=%i), until [sn:%llu].\n",
1017            tid, tid, historyBuffer[tid].size(), inst_seq_num);
1018
1019    typename std::list<RenameHistory>::iterator hb_it =
1020        historyBuffer[tid].end();
1021
1022    --hb_it;
1023
1024    if (historyBuffer[tid].empty()) {
1025        DPRINTF(Rename, "[tid:%i] History buffer is empty.\n", tid);
1026        return;
1027    } else if (hb_it->instSeqNum > inst_seq_num) {
1028        DPRINTF(Rename, "[tid:%i] [sn:%llu] "
1029                "Old sequence number encountered. "
1030                "Ensure that a syscall happened recently.\n",
1031                tid,inst_seq_num);
1032        return;
1033    }
1034
1035    // Commit all the renames up until (and including) the committed sequence
1036    // number. Some or even all of the committed instructions may not have
1037    // rename histories if they did not have destination registers that were
1038    // renamed.
1039    while (!historyBuffer[tid].empty() &&
1040           hb_it != historyBuffer[tid].end() &&
1041           hb_it->instSeqNum <= inst_seq_num) {
1042
1043        DPRINTF(Rename, "[tid:%i] Freeing up older rename of reg %i (%s), "
1044                "[sn:%llu].\n",
1045                tid, hb_it->prevPhysReg->index(),
1046                hb_it->prevPhysReg->className(),
1047                hb_it->instSeqNum);
1048
1049        // Don't free special phys regs like misc and zero regs, which
1050        // can be recognized because the new mapping is the same as
1051        // the old one.
1052        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
1053            freeList->addReg(hb_it->prevPhysReg);
1054        }
1055
1056        ++renameCommittedMaps;
1057
1058        historyBuffer[tid].erase(hb_it--);
1059    }
1060}
1061
1062template <class Impl>
1063inline void
1064DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid)
1065{
1066    ThreadContext *tc = inst->tcBase();
1067    RenameMap *map = renameMap[tid];
1068    unsigned num_src_regs = inst->numSrcRegs();
1069
1070    // Get the architectual register numbers from the source and
1071    // operands, and redirect them to the right physical register.
1072    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1073        const RegId& src_reg = inst->srcRegIdx(src_idx);
1074        PhysRegIdPtr renamed_reg;
1075
1076        renamed_reg = map->lookup(tc->flattenRegId(src_reg));
1077        switch (src_reg.classValue()) {
1078          case IntRegClass:
1079            intRenameLookups++;
1080            break;
1081          case FloatRegClass:
1082            fpRenameLookups++;
1083            break;
1084          case VecRegClass:
1085          case VecElemClass:
1086            vecRenameLookups++;
1087            break;
1088          case VecPredRegClass:
1089            vecPredRenameLookups++;
1090            break;
1091          case CCRegClass:
1092          case MiscRegClass:
1093            break;
1094
1095          default:
1096            panic("Invalid register class: %d.", src_reg.classValue());
1097        }
1098
1099        DPRINTF(Rename,
1100                "[tid:%i] "
1101                "Looking up %s arch reg %i, got phys reg %i (%s)\n",
1102                tid, src_reg.className(),
1103                src_reg.index(), renamed_reg->index(),
1104                renamed_reg->className());
1105
1106        inst->renameSrcReg(src_idx, renamed_reg);
1107
1108        // See if the register is ready or not.
1109        if (scoreboard->getReg(renamed_reg)) {
1110            DPRINTF(Rename,
1111                    "[tid:%i] "
1112                    "Register %d (flat: %d) (%s) is ready.\n",
1113                    tid, renamed_reg->index(), renamed_reg->flatIndex(),
1114                    renamed_reg->className());
1115
1116            inst->markSrcRegReady(src_idx);
1117        } else {
1118            DPRINTF(Rename,
1119                    "[tid:%i] "
1120                    "Register %d (flat: %d) (%s) is not ready.\n",
1121                    tid, renamed_reg->index(), renamed_reg->flatIndex(),
1122                    renamed_reg->className());
1123        }
1124
1125        ++renameRenameLookups;
1126    }
1127}
1128
1129template <class Impl>
1130inline void
1131DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid)
1132{
1133    ThreadContext *tc = inst->tcBase();
1134    RenameMap *map = renameMap[tid];
1135    unsigned num_dest_regs = inst->numDestRegs();
1136
1137    // Rename the destination registers.
1138    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1139        const RegId& dest_reg = inst->destRegIdx(dest_idx);
1140        typename RenameMap::RenameInfo rename_result;
1141
1142        RegId flat_dest_regid = tc->flattenRegId(dest_reg);
1143
1144        rename_result = map->rename(flat_dest_regid);
1145
1146        inst->flattenDestReg(dest_idx, flat_dest_regid);
1147
1148        // Mark Scoreboard entry as not ready
1149        scoreboard->unsetReg(rename_result.first);
1150
1151        DPRINTF(Rename,
1152                "[tid:%i] "
1153                "Renaming arch reg %i (%s) to physical reg %i (%i).\n",
1154                tid, dest_reg.index(), dest_reg.className(),
1155                rename_result.first->index(),
1156                rename_result.first->flatIndex());
1157
1158        // Record the rename information so that a history can be kept.
1159        RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1160                               rename_result.first,
1161                               rename_result.second);
1162
1163        historyBuffer[tid].push_front(hb_entry);
1164
1165        DPRINTF(Rename, "[tid:%i] [sn:%llu] "
1166                "Adding instruction to history buffer (size=%i).\n",
1167                tid,(*historyBuffer[tid].begin()).instSeqNum,
1168                historyBuffer[tid].size());
1169
1170        // Tell the instruction to rename the appropriate destination
1171        // register (dest_idx) to the new physical register
1172        // (rename_result.first), and record the previous physical
1173        // register that the same logical register was renamed to
1174        // (rename_result.second).
1175        inst->renameDestReg(dest_idx,
1176                            rename_result.first,
1177                            rename_result.second);
1178
1179        ++renameRenamedOperands;
1180    }
1181}
1182
1183template <class Impl>
1184inline int
1185DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1186{
1187    int num_free = freeEntries[tid].robEntries -
1188                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1189
1190    //DPRINTF(Rename,"[tid:%i] %i rob free\n",tid,num_free);
1191
1192    return num_free;
1193}
1194
1195template <class Impl>
1196inline int
1197DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1198{
1199    int num_free = freeEntries[tid].iqEntries -
1200                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1201
1202    //DPRINTF(Rename,"[tid:%i] %i iq free\n",tid,num_free);
1203
1204    return num_free;
1205}
1206
1207template <class Impl>
1208inline int
1209DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1210{
1211        int num_free = freeEntries[tid].lqEntries -
1212                                  (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1213        DPRINTF(Rename,
1214                "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1215                "loads dispatchedToLQ: %d\n",
1216                freeEntries[tid].lqEntries, loadsInProgress[tid],
1217                fromIEW->iewInfo[tid].dispatchedToLQ);
1218        return num_free;
1219}
1220
1221template <class Impl>
1222inline int
1223DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1224{
1225        int num_free = freeEntries[tid].sqEntries -
1226                                  (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1227        DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1228                "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1229                storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1230        return num_free;
1231}
1232
1233template <class Impl>
1234unsigned
1235DefaultRename<Impl>::validInsts()
1236{
1237    unsigned inst_count = 0;
1238
1239    for (int i=0; i<fromDecode->size; i++) {
1240        if (!fromDecode->insts[i]->isSquashed())
1241            inst_count++;
1242    }
1243
1244    return inst_count;
1245}
1246
1247template <class Impl>
1248void
1249DefaultRename<Impl>::readStallSignals(ThreadID tid)
1250{
1251    if (fromIEW->iewBlock[tid]) {
1252        stalls[tid].iew = true;
1253    }
1254
1255    if (fromIEW->iewUnblock[tid]) {
1256        assert(stalls[tid].iew);
1257        stalls[tid].iew = false;
1258    }
1259}
1260
1261template <class Impl>
1262bool
1263DefaultRename<Impl>::checkStall(ThreadID tid)
1264{
1265    bool ret_val = false;
1266
1267    if (stalls[tid].iew) {
1268        DPRINTF(Rename,"[tid:%i] Stall from IEW stage detected.\n", tid);
1269        ret_val = true;
1270    } else if (calcFreeROBEntries(tid) <= 0) {
1271        DPRINTF(Rename,"[tid:%i] Stall: ROB has 0 free entries.\n", tid);
1272        ret_val = true;
1273    } else if (calcFreeIQEntries(tid) <= 0) {
1274        DPRINTF(Rename,"[tid:%i] Stall: IQ has 0 free entries.\n", tid);
1275        ret_val = true;
1276    } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) {
1277        DPRINTF(Rename,"[tid:%i] Stall: LSQ has 0 free entries.\n", tid);
1278        ret_val = true;
1279    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1280        DPRINTF(Rename,"[tid:%i] Stall: RenameMap has 0 free entries.\n", tid);
1281        ret_val = true;
1282    } else if (renameStatus[tid] == SerializeStall &&
1283               (!emptyROB[tid] || instsInProgress[tid])) {
1284        DPRINTF(Rename,"[tid:%i] Stall: Serialize stall and ROB is not "
1285                "empty.\n",
1286                tid);
1287        ret_val = true;
1288    }
1289
1290    return ret_val;
1291}
1292
1293template <class Impl>
1294void
1295DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1296{
1297    if (fromIEW->iewInfo[tid].usedIQ)
1298        freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1299
1300    if (fromIEW->iewInfo[tid].usedLSQ) {
1301        freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries;
1302        freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries;
1303    }
1304
1305    if (fromCommit->commitInfo[tid].usedROB) {
1306        freeEntries[tid].robEntries =
1307            fromCommit->commitInfo[tid].freeROBEntries;
1308        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1309    }
1310
1311    DPRINTF(Rename, "[tid:%i] Free IQ: %i, Free ROB: %i, "
1312                    "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n",
1313            tid,
1314            freeEntries[tid].iqEntries,
1315            freeEntries[tid].robEntries,
1316            freeEntries[tid].lqEntries,
1317            freeEntries[tid].sqEntries,
1318            renameMap[tid]->numFreeEntries(),
1319            renameMap[tid]->numFreeIntEntries(),
1320            renameMap[tid]->numFreeFloatEntries(),
1321            renameMap[tid]->numFreeVecEntries(),
1322            renameMap[tid]->numFreePredEntries(),
1323            renameMap[tid]->numFreeCCEntries());
1324
1325    DPRINTF(Rename, "[tid:%i] %i instructions not yet in ROB\n",
1326            tid, instsInProgress[tid]);
1327}
1328
1329template <class Impl>
1330bool
1331DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1332{
1333    // Check if there's a squash signal, squash if there is
1334    // Check stall signals, block if necessary.
1335    // If status was blocked
1336    //     check if stall conditions have passed
1337    //         if so then go to unblocking
1338    // If status was Squashing
1339    //     check if squashing is not high.  Switch to running this cycle.
1340    // If status was serialize stall
1341    //     check if ROB is empty and no insts are in flight to the ROB
1342
1343    readFreeEntries(tid);
1344    readStallSignals(tid);
1345
1346    if (fromCommit->commitInfo[tid].squash) {
1347        DPRINTF(Rename, "[tid:%i] Squashing instructions due to squash from "
1348                "commit.\n", tid);
1349
1350        squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1351
1352        return true;
1353    }
1354
1355    if (checkStall(tid)) {
1356        return block(tid);
1357    }
1358
1359    if (renameStatus[tid] == Blocked) {
1360        DPRINTF(Rename, "[tid:%i] Done blocking, switching to unblocking.\n",
1361                tid);
1362
1363        renameStatus[tid] = Unblocking;
1364
1365        unblock(tid);
1366
1367        return true;
1368    }
1369
1370    if (renameStatus[tid] == Squashing) {
1371        // Switch status to running if rename isn't being told to block or
1372        // squash this cycle.
1373        if (resumeSerialize) {
1374            DPRINTF(Rename,
1375                    "[tid:%i] Done squashing, switching to serialize.\n", tid);
1376
1377            renameStatus[tid] = SerializeStall;
1378            return true;
1379        } else if (resumeUnblocking) {
1380            DPRINTF(Rename,
1381                    "[tid:%i] Done squashing, switching to unblocking.\n",
1382                    tid);
1383            renameStatus[tid] = Unblocking;
1384            return true;
1385        } else {
1386            DPRINTF(Rename, "[tid:%i] Done squashing, switching to running.\n",
1387                    tid);
1388            renameStatus[tid] = Running;
1389            return false;
1390        }
1391    }
1392
1393    if (renameStatus[tid] == SerializeStall) {
1394        // Stall ends once the ROB is free.
1395        DPRINTF(Rename, "[tid:%i] Done with serialize stall, switching to "
1396                "unblocking.\n", tid);
1397
1398        DynInstPtr serial_inst = serializeInst[tid];
1399
1400        renameStatus[tid] = Unblocking;
1401
1402        unblock(tid);
1403
1404        DPRINTF(Rename, "[tid:%i] Processing instruction [%lli] with "
1405                "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1406
1407        // Put instruction into queue here.
1408        serial_inst->clearSerializeBefore();
1409
1410        if (!skidBuffer[tid].empty()) {
1411            skidBuffer[tid].push_front(serial_inst);
1412        } else {
1413            insts[tid].push_front(serial_inst);
1414        }
1415
1416        DPRINTF(Rename, "[tid:%i] Instruction must be processed by rename."
1417                " Adding to front of list.\n", tid);
1418
1419        serializeInst[tid] = NULL;
1420
1421        return true;
1422    }
1423
1424    // If we've reached this point, we have not gotten any signals that
1425    // cause rename to change its status.  Rename remains the same as before.
1426    return false;
1427}
1428
1429template<class Impl>
1430void
1431DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1432{
1433    if (inst_list.empty()) {
1434        // Mark a bit to say that I must serialize on the next instruction.
1435        serializeOnNextInst[tid] = true;
1436        return;
1437    }
1438
1439    // Set the next instruction as serializing.
1440    inst_list.front()->setSerializeBefore();
1441}
1442
1443template <class Impl>
1444inline void
1445DefaultRename<Impl>::incrFullStat(const FullSource &source)
1446{
1447    switch (source) {
1448      case ROB:
1449        ++renameROBFullEvents;
1450        break;
1451      case IQ:
1452        ++renameIQFullEvents;
1453        break;
1454      case LQ:
1455        ++renameLQFullEvents;
1456        break;
1457      case SQ:
1458        ++renameSQFullEvents;
1459        break;
1460      default:
1461        panic("Rename full stall stat should be incremented for a reason!");
1462        break;
1463    }
1464}
1465
1466template <class Impl>
1467void
1468DefaultRename<Impl>::dumpHistory()
1469{
1470    typename std::list<RenameHistory>::iterator buf_it;
1471
1472    for (ThreadID tid = 0; tid < numThreads; tid++) {
1473
1474        buf_it = historyBuffer[tid].begin();
1475
1476        while (buf_it != historyBuffer[tid].end()) {
1477            cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
1478                    " %i[%s] Old phys reg: %i[%s]\n",
1479                    (*buf_it).instSeqNum,
1480                    (*buf_it).archReg.className(),
1481                    (*buf_it).archReg.index(),
1482                    (*buf_it).newPhysReg->index(),
1483                    (*buf_it).newPhysReg->className(),
1484                    (*buf_it).prevPhysReg->index(),
1485                    (*buf_it).prevPhysReg->className());
1486
1487            buf_it++;
1488        }
1489    }
1490}
1491
1492#endif//__CPU_O3_RENAME_IMPL_HH__
1493