rename_impl.hh revision 13641:648f3106ebdf
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2010-2012, 2014-2016 ARM Limited 310259SAndrew.Bardsley@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 410259SAndrew.Bardsley@arm.com * All rights reserved. 510259SAndrew.Bardsley@arm.com * 610259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 710259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 810259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 910259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 1010259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1110259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1210259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1310259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1410259SAndrew.Bardsley@arm.com * 1510259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1610259SAndrew.Bardsley@arm.com * All rights reserved. 1710259SAndrew.Bardsley@arm.com * 1810259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1910259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 2010259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2110259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2210259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2310259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2410259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2510259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2610259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2710259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2810259SAndrew.Bardsley@arm.com * 2910259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3010259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3210259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3310259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3410259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3510259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3610259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3710259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3810259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3910259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4010259SAndrew.Bardsley@arm.com * 4110259SAndrew.Bardsley@arm.com * Authors: Kevin Lim 4210259SAndrew.Bardsley@arm.com * Korey Sewell 4310259SAndrew.Bardsley@arm.com */ 4410259SAndrew.Bardsley@arm.com 4510259SAndrew.Bardsley@arm.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 4610259SAndrew.Bardsley@arm.com#define __CPU_O3_RENAME_IMPL_HH__ 4710259SAndrew.Bardsley@arm.com 4810259SAndrew.Bardsley@arm.com#include <list> 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com#include "arch/isa_traits.hh" 5110259SAndrew.Bardsley@arm.com#include "arch/registers.hh" 5210259SAndrew.Bardsley@arm.com#include "config/the_isa.hh" 5312334Sgabeblack@google.com#include "cpu/o3/rename.hh" 5412334Sgabeblack@google.com#include "cpu/reg_class.hh" 5510259SAndrew.Bardsley@arm.com#include "debug/Activity.hh" 5610259SAndrew.Bardsley@arm.com#include "debug/Rename.hh" 5710259SAndrew.Bardsley@arm.com#include "debug/O3PipeView.hh" 5810259SAndrew.Bardsley@arm.com#include "params/DerivO3CPU.hh" 5910259SAndrew.Bardsley@arm.com 6010259SAndrew.Bardsley@arm.comusing namespace std; 6110259SAndrew.Bardsley@arm.com 6210259SAndrew.Bardsley@arm.comtemplate <class Impl> 6310259SAndrew.Bardsley@arm.comDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 6410259SAndrew.Bardsley@arm.com : cpu(_cpu), 6510259SAndrew.Bardsley@arm.com iewToRenameDelay(params->iewToRenameDelay), 6610259SAndrew.Bardsley@arm.com decodeToRenameDelay(params->decodeToRenameDelay), 6710259SAndrew.Bardsley@arm.com commitToRenameDelay(params->commitToRenameDelay), 6810259SAndrew.Bardsley@arm.com renameWidth(params->renameWidth), 6910259SAndrew.Bardsley@arm.com commitWidth(params->commitWidth), 7010259SAndrew.Bardsley@arm.com numThreads(params->numThreads) 7110259SAndrew.Bardsley@arm.com{ 7210259SAndrew.Bardsley@arm.com if (renameWidth > Impl::MaxWidth) 7310259SAndrew.Bardsley@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410259SAndrew.Bardsley@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510259SAndrew.Bardsley@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610259SAndrew.Bardsley@arm.com 7710259SAndrew.Bardsley@arm.com // @todo: Make into a parameter. 7810259SAndrew.Bardsley@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 7910259SAndrew.Bardsley@arm.com for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 8010259SAndrew.Bardsley@arm.com renameStatus[tid] = Idle; 8110259SAndrew.Bardsley@arm.com renameMap[tid] = nullptr; 8210259SAndrew.Bardsley@arm.com instsInProgress[tid] = 0; 8310259SAndrew.Bardsley@arm.com loadsInProgress[tid] = 0; 8410259SAndrew.Bardsley@arm.com storesInProgress[tid] = 0; 8510259SAndrew.Bardsley@arm.com freeEntries[tid] = {0, 0, 0, 0}; 8610259SAndrew.Bardsley@arm.com emptyROB[tid] = true; 8710259SAndrew.Bardsley@arm.com stalls[tid] = {false, false}; 8810259SAndrew.Bardsley@arm.com serializeInst[tid] = nullptr; 8910259SAndrew.Bardsley@arm.com serializeOnNextInst[tid] = false; 9010259SAndrew.Bardsley@arm.com } 9110259SAndrew.Bardsley@arm.com} 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.comtemplate <class Impl> 9410259SAndrew.Bardsley@arm.comstd::string 9510259SAndrew.Bardsley@arm.comDefaultRename<Impl>::name() const 9610259SAndrew.Bardsley@arm.com{ 9710259SAndrew.Bardsley@arm.com return cpu->name() + ".rename"; 9810259SAndrew.Bardsley@arm.com} 9910259SAndrew.Bardsley@arm.com 10010259SAndrew.Bardsley@arm.comtemplate <class Impl> 10110259SAndrew.Bardsley@arm.comvoid 10210259SAndrew.Bardsley@arm.comDefaultRename<Impl>::regStats() 10310259SAndrew.Bardsley@arm.com{ 10410259SAndrew.Bardsley@arm.com renameSquashCycles 10510259SAndrew.Bardsley@arm.com .name(name() + ".SquashCycles") 10610259SAndrew.Bardsley@arm.com .desc("Number of cycles rename is squashing") 10710259SAndrew.Bardsley@arm.com .prereq(renameSquashCycles); 10810259SAndrew.Bardsley@arm.com renameIdleCycles 10910259SAndrew.Bardsley@arm.com .name(name() + ".IdleCycles") 11010259SAndrew.Bardsley@arm.com .desc("Number of cycles rename is idle") 11110259SAndrew.Bardsley@arm.com .prereq(renameIdleCycles); 11210259SAndrew.Bardsley@arm.com renameBlockCycles 11310259SAndrew.Bardsley@arm.com .name(name() + ".BlockCycles") 11410259SAndrew.Bardsley@arm.com .desc("Number of cycles rename is blocking") 11510259SAndrew.Bardsley@arm.com .prereq(renameBlockCycles); 11610259SAndrew.Bardsley@arm.com renameSerializeStallCycles 11710259SAndrew.Bardsley@arm.com .name(name() + ".serializeStallCycles") 11810259SAndrew.Bardsley@arm.com .desc("count of cycles rename stalled for serializing inst") 11910259SAndrew.Bardsley@arm.com .flags(Stats::total); 12010259SAndrew.Bardsley@arm.com renameRunCycles 12113449Sgabeblack@google.com .name(name() + ".RunCycles") 12213449Sgabeblack@google.com .desc("Number of cycles rename is running") 12313449Sgabeblack@google.com .prereq(renameIdleCycles); 12413449Sgabeblack@google.com renameUnblockCycles 12513449Sgabeblack@google.com .name(name() + ".UnblockCycles") 12610259SAndrew.Bardsley@arm.com .desc("Number of cycles rename is unblocking") 12710259SAndrew.Bardsley@arm.com .prereq(renameUnblockCycles); 12810259SAndrew.Bardsley@arm.com renameRenamedInsts 12910259SAndrew.Bardsley@arm.com .name(name() + ".RenamedInsts") 13010259SAndrew.Bardsley@arm.com .desc("Number of instructions processed by rename") 13110259SAndrew.Bardsley@arm.com .prereq(renameRenamedInsts); 13210259SAndrew.Bardsley@arm.com renameSquashedInsts 13310259SAndrew.Bardsley@arm.com .name(name() + ".SquashedInsts") 13410259SAndrew.Bardsley@arm.com .desc("Number of squashed instructions processed by rename") 13510259SAndrew.Bardsley@arm.com .prereq(renameSquashedInsts); 13610259SAndrew.Bardsley@arm.com renameROBFullEvents 13710259SAndrew.Bardsley@arm.com .name(name() + ".ROBFullEvents") 13810259SAndrew.Bardsley@arm.com .desc("Number of times rename has blocked due to ROB full") 13910259SAndrew.Bardsley@arm.com .prereq(renameROBFullEvents); 14010259SAndrew.Bardsley@arm.com renameIQFullEvents 14110259SAndrew.Bardsley@arm.com .name(name() + ".IQFullEvents") 14210259SAndrew.Bardsley@arm.com .desc("Number of times rename has blocked due to IQ full") 14310259SAndrew.Bardsley@arm.com .prereq(renameIQFullEvents); 14410259SAndrew.Bardsley@arm.com renameLQFullEvents 14510259SAndrew.Bardsley@arm.com .name(name() + ".LQFullEvents") 14610259SAndrew.Bardsley@arm.com .desc("Number of times rename has blocked due to LQ full") 14710259SAndrew.Bardsley@arm.com .prereq(renameLQFullEvents); 14810259SAndrew.Bardsley@arm.com renameSQFullEvents 14910259SAndrew.Bardsley@arm.com .name(name() + ".SQFullEvents") 15010259SAndrew.Bardsley@arm.com .desc("Number of times rename has blocked due to SQ full") 15110259SAndrew.Bardsley@arm.com .prereq(renameSQFullEvents); 15210259SAndrew.Bardsley@arm.com renameFullRegistersEvents 15310259SAndrew.Bardsley@arm.com .name(name() + ".FullRegisterEvents") 15410259SAndrew.Bardsley@arm.com .desc("Number of times there has been no free registers") 15510259SAndrew.Bardsley@arm.com .prereq(renameFullRegistersEvents); 15610259SAndrew.Bardsley@arm.com renameRenamedOperands 15710259SAndrew.Bardsley@arm.com .name(name() + ".RenamedOperands") 15810259SAndrew.Bardsley@arm.com .desc("Number of destination operands rename has renamed") 15910259SAndrew.Bardsley@arm.com .prereq(renameRenamedOperands); 16010259SAndrew.Bardsley@arm.com renameRenameLookups 16110259SAndrew.Bardsley@arm.com .name(name() + ".RenameLookups") 16210259SAndrew.Bardsley@arm.com .desc("Number of register rename lookups that rename has made") 16310259SAndrew.Bardsley@arm.com .prereq(renameRenameLookups); 16410259SAndrew.Bardsley@arm.com renameCommittedMaps 16510259SAndrew.Bardsley@arm.com .name(name() + ".CommittedMaps") 16610259SAndrew.Bardsley@arm.com .desc("Number of HB maps that are committed") 16710259SAndrew.Bardsley@arm.com .prereq(renameCommittedMaps); 16810259SAndrew.Bardsley@arm.com renameUndoneMaps 16910259SAndrew.Bardsley@arm.com .name(name() + ".UndoneMaps") 17010259SAndrew.Bardsley@arm.com .desc("Number of HB maps that are undone due to squashing") 17110259SAndrew.Bardsley@arm.com .prereq(renameUndoneMaps); 17210259SAndrew.Bardsley@arm.com renamedSerializing 17310259SAndrew.Bardsley@arm.com .name(name() + ".serializingInsts") 17410259SAndrew.Bardsley@arm.com .desc("count of serializing insts renamed") 17510259SAndrew.Bardsley@arm.com .flags(Stats::total) 17610259SAndrew.Bardsley@arm.com ; 17710259SAndrew.Bardsley@arm.com renamedTempSerializing 17810259SAndrew.Bardsley@arm.com .name(name() + ".tempSerializingInsts") 17910259SAndrew.Bardsley@arm.com .desc("count of temporary serializing insts renamed") 18010259SAndrew.Bardsley@arm.com .flags(Stats::total) 18110259SAndrew.Bardsley@arm.com ; 18210259SAndrew.Bardsley@arm.com renameSkidInsts 18310259SAndrew.Bardsley@arm.com .name(name() + ".skidInsts") 18410259SAndrew.Bardsley@arm.com .desc("count of insts added to the skid buffer") 18510259SAndrew.Bardsley@arm.com .flags(Stats::total) 18610259SAndrew.Bardsley@arm.com ; 18710259SAndrew.Bardsley@arm.com intRenameLookups 18810259SAndrew.Bardsley@arm.com .name(name() + ".int_rename_lookups") 18910259SAndrew.Bardsley@arm.com .desc("Number of integer rename lookups") 19010259SAndrew.Bardsley@arm.com .prereq(intRenameLookups); 19110259SAndrew.Bardsley@arm.com fpRenameLookups 19210259SAndrew.Bardsley@arm.com .name(name() + ".fp_rename_lookups") 19310259SAndrew.Bardsley@arm.com .desc("Number of floating rename lookups") 19410259SAndrew.Bardsley@arm.com .prereq(fpRenameLookups); 19510259SAndrew.Bardsley@arm.com vecRenameLookups 19610259SAndrew.Bardsley@arm.com .name(name() + ".vec_rename_lookups") 19710259SAndrew.Bardsley@arm.com .desc("Number of vector rename lookups") 19810259SAndrew.Bardsley@arm.com .prereq(vecRenameLookups); 19910259SAndrew.Bardsley@arm.com vecPredRenameLookups 20010259SAndrew.Bardsley@arm.com .name(name() + ".vec_pred_rename_lookups") 20110259SAndrew.Bardsley@arm.com .desc("Number of vector predicate rename lookups") 20210259SAndrew.Bardsley@arm.com .prereq(vecPredRenameLookups); 20310259SAndrew.Bardsley@arm.com} 20410259SAndrew.Bardsley@arm.com 20510259SAndrew.Bardsley@arm.comtemplate <class Impl> 20610259SAndrew.Bardsley@arm.comvoid 20710259SAndrew.Bardsley@arm.comDefaultRename<Impl>::regProbePoints() 20810259SAndrew.Bardsley@arm.com{ 20910259SAndrew.Bardsley@arm.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 21010259SAndrew.Bardsley@arm.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 21110259SAndrew.Bardsley@arm.com "SquashInRename"); 21210259SAndrew.Bardsley@arm.com} 21310259SAndrew.Bardsley@arm.com 21410259SAndrew.Bardsley@arm.comtemplate <class Impl> 21510259SAndrew.Bardsley@arm.comvoid 21610259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 21710259SAndrew.Bardsley@arm.com{ 21810259SAndrew.Bardsley@arm.com timeBuffer = tb_ptr; 21910259SAndrew.Bardsley@arm.com 22010259SAndrew.Bardsley@arm.com // Setup wire to read information from time buffer, from IEW stage. 22110259SAndrew.Bardsley@arm.com fromIEW = timeBuffer->getWire(-iewToRenameDelay); 22210259SAndrew.Bardsley@arm.com 22310259SAndrew.Bardsley@arm.com // Setup wire to read infromation from time buffer, from commit stage. 22410259SAndrew.Bardsley@arm.com fromCommit = timeBuffer->getWire(-commitToRenameDelay); 22510259SAndrew.Bardsley@arm.com 22610259SAndrew.Bardsley@arm.com // Setup wire to write information to previous stages. 22710259SAndrew.Bardsley@arm.com toDecode = timeBuffer->getWire(0); 22810259SAndrew.Bardsley@arm.com} 22910259SAndrew.Bardsley@arm.com 23010259SAndrew.Bardsley@arm.comtemplate <class Impl> 23110259SAndrew.Bardsley@arm.comvoid 23210259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 23310259SAndrew.Bardsley@arm.com{ 23410259SAndrew.Bardsley@arm.com renameQueue = rq_ptr; 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com // Setup wire to write information to future stages. 23710259SAndrew.Bardsley@arm.com toIEW = renameQueue->getWire(0); 23810259SAndrew.Bardsley@arm.com} 23910259SAndrew.Bardsley@arm.com 24010259SAndrew.Bardsley@arm.comtemplate <class Impl> 24110259SAndrew.Bardsley@arm.comvoid 24210259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 24310259SAndrew.Bardsley@arm.com{ 24410259SAndrew.Bardsley@arm.com decodeQueue = dq_ptr; 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.com // Setup wire to get information from decode. 24710259SAndrew.Bardsley@arm.com fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 24810259SAndrew.Bardsley@arm.com} 24910259SAndrew.Bardsley@arm.com 25010259SAndrew.Bardsley@arm.comtemplate <class Impl> 25110259SAndrew.Bardsley@arm.comvoid 25210259SAndrew.Bardsley@arm.comDefaultRename<Impl>::startupStage() 25310259SAndrew.Bardsley@arm.com{ 25410259SAndrew.Bardsley@arm.com resetStage(); 25510259SAndrew.Bardsley@arm.com} 25610259SAndrew.Bardsley@arm.com 25710259SAndrew.Bardsley@arm.comtemplate <class Impl> 25810259SAndrew.Bardsley@arm.comvoid 25910259SAndrew.Bardsley@arm.comDefaultRename<Impl>::clearStates(ThreadID tid) 26010259SAndrew.Bardsley@arm.com{ 26110259SAndrew.Bardsley@arm.com renameStatus[tid] = Idle; 26210259SAndrew.Bardsley@arm.com 26310259SAndrew.Bardsley@arm.com freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 26410259SAndrew.Bardsley@arm.com freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 26510259SAndrew.Bardsley@arm.com freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 26610259SAndrew.Bardsley@arm.com freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 26710259SAndrew.Bardsley@arm.com emptyROB[tid] = true; 26810259SAndrew.Bardsley@arm.com 26910259SAndrew.Bardsley@arm.com stalls[tid].iew = false; 27010259SAndrew.Bardsley@arm.com serializeInst[tid] = NULL; 27110259SAndrew.Bardsley@arm.com 27210259SAndrew.Bardsley@arm.com instsInProgress[tid] = 0; 27310259SAndrew.Bardsley@arm.com loadsInProgress[tid] = 0; 27410259SAndrew.Bardsley@arm.com storesInProgress[tid] = 0; 27510259SAndrew.Bardsley@arm.com 27610259SAndrew.Bardsley@arm.com serializeOnNextInst[tid] = false; 27710259SAndrew.Bardsley@arm.com} 27810259SAndrew.Bardsley@arm.com 27910259SAndrew.Bardsley@arm.comtemplate <class Impl> 28010259SAndrew.Bardsley@arm.comvoid 28110259SAndrew.Bardsley@arm.comDefaultRename<Impl>::resetStage() 28210259SAndrew.Bardsley@arm.com{ 28310259SAndrew.Bardsley@arm.com _status = Inactive; 28410259SAndrew.Bardsley@arm.com 28510259SAndrew.Bardsley@arm.com resumeSerialize = false; 28610259SAndrew.Bardsley@arm.com resumeUnblocking = false; 28710259SAndrew.Bardsley@arm.com 28810259SAndrew.Bardsley@arm.com // Grab the number of free entries directly from the stages. 28910259SAndrew.Bardsley@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 29010259SAndrew.Bardsley@arm.com renameStatus[tid] = Idle; 29110259SAndrew.Bardsley@arm.com 29210259SAndrew.Bardsley@arm.com freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 29310259SAndrew.Bardsley@arm.com freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 29410259SAndrew.Bardsley@arm.com freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 29510259SAndrew.Bardsley@arm.com freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 29610259SAndrew.Bardsley@arm.com emptyROB[tid] = true; 29710259SAndrew.Bardsley@arm.com 29810259SAndrew.Bardsley@arm.com stalls[tid].iew = false; 29910259SAndrew.Bardsley@arm.com serializeInst[tid] = NULL; 30010259SAndrew.Bardsley@arm.com 30110259SAndrew.Bardsley@arm.com instsInProgress[tid] = 0; 30210259SAndrew.Bardsley@arm.com loadsInProgress[tid] = 0; 30310259SAndrew.Bardsley@arm.com storesInProgress[tid] = 0; 30410259SAndrew.Bardsley@arm.com 30510259SAndrew.Bardsley@arm.com serializeOnNextInst[tid] = false; 30610259SAndrew.Bardsley@arm.com } 30710259SAndrew.Bardsley@arm.com} 30810259SAndrew.Bardsley@arm.com 30910259SAndrew.Bardsley@arm.comtemplate<class Impl> 31010259SAndrew.Bardsley@arm.comvoid 31110259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 31210259SAndrew.Bardsley@arm.com{ 31310259SAndrew.Bardsley@arm.com activeThreads = at_ptr; 31410259SAndrew.Bardsley@arm.com} 31510259SAndrew.Bardsley@arm.com 31610259SAndrew.Bardsley@arm.com 31710259SAndrew.Bardsley@arm.comtemplate <class Impl> 31810259SAndrew.Bardsley@arm.comvoid 31910259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 32010259SAndrew.Bardsley@arm.com{ 32110259SAndrew.Bardsley@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) 32210259SAndrew.Bardsley@arm.com renameMap[tid] = &rm_ptr[tid]; 32310259SAndrew.Bardsley@arm.com} 32410259SAndrew.Bardsley@arm.com 32510259SAndrew.Bardsley@arm.comtemplate <class Impl> 32610259SAndrew.Bardsley@arm.comvoid 32710259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 32810259SAndrew.Bardsley@arm.com{ 32910259SAndrew.Bardsley@arm.com freeList = fl_ptr; 33010259SAndrew.Bardsley@arm.com} 33110259SAndrew.Bardsley@arm.com 33210259SAndrew.Bardsley@arm.comtemplate<class Impl> 33310259SAndrew.Bardsley@arm.comvoid 33410259SAndrew.Bardsley@arm.comDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 33510259SAndrew.Bardsley@arm.com{ 33610259SAndrew.Bardsley@arm.com scoreboard = _scoreboard; 33710259SAndrew.Bardsley@arm.com} 33810259SAndrew.Bardsley@arm.com 33910259SAndrew.Bardsley@arm.comtemplate <class Impl> 34010259SAndrew.Bardsley@arm.combool 34110259SAndrew.Bardsley@arm.comDefaultRename<Impl>::isDrained() const 34210259SAndrew.Bardsley@arm.com{ 34310259SAndrew.Bardsley@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 34410259SAndrew.Bardsley@arm.com if (instsInProgress[tid] != 0 || 34510259SAndrew.Bardsley@arm.com !historyBuffer[tid].empty() || 34610259SAndrew.Bardsley@arm.com !skidBuffer[tid].empty() || 34710259SAndrew.Bardsley@arm.com !insts[tid].empty() || 34810259SAndrew.Bardsley@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 34910259SAndrew.Bardsley@arm.com return false; 35010259SAndrew.Bardsley@arm.com } 35110259SAndrew.Bardsley@arm.com return true; 35210259SAndrew.Bardsley@arm.com} 35310259SAndrew.Bardsley@arm.com 35410259SAndrew.Bardsley@arm.comtemplate <class Impl> 35510259SAndrew.Bardsley@arm.comvoid 35610259SAndrew.Bardsley@arm.comDefaultRename<Impl>::takeOverFrom() 35710259SAndrew.Bardsley@arm.com{ 35810259SAndrew.Bardsley@arm.com resetStage(); 35910259SAndrew.Bardsley@arm.com} 36010259SAndrew.Bardsley@arm.com 36110259SAndrew.Bardsley@arm.comtemplate <class Impl> 36210259SAndrew.Bardsley@arm.comvoid 36310259SAndrew.Bardsley@arm.comDefaultRename<Impl>::drainSanityCheck() const 36410259SAndrew.Bardsley@arm.com{ 36510259SAndrew.Bardsley@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 36610259SAndrew.Bardsley@arm.com assert(historyBuffer[tid].empty()); 36710259SAndrew.Bardsley@arm.com assert(insts[tid].empty()); 36810259SAndrew.Bardsley@arm.com assert(skidBuffer[tid].empty()); 36910259SAndrew.Bardsley@arm.com assert(instsInProgress[tid] == 0); 37010259SAndrew.Bardsley@arm.com } 37110259SAndrew.Bardsley@arm.com} 37210259SAndrew.Bardsley@arm.com 37310259SAndrew.Bardsley@arm.comtemplate <class Impl> 37410259SAndrew.Bardsley@arm.comvoid 37510259SAndrew.Bardsley@arm.comDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 37610259SAndrew.Bardsley@arm.com{ 37710259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 37810259SAndrew.Bardsley@arm.com 37910259SAndrew.Bardsley@arm.com // Clear the stall signal if rename was blocked or unblocking before. 38010259SAndrew.Bardsley@arm.com // If it still needs to block, the blocking should happen the next 38110259SAndrew.Bardsley@arm.com // cycle and there should be space to hold everything due to the squash. 38210259SAndrew.Bardsley@arm.com if (renameStatus[tid] == Blocked || 38310259SAndrew.Bardsley@arm.com renameStatus[tid] == Unblocking) { 38410259SAndrew.Bardsley@arm.com toDecode->renameUnblock[tid] = 1; 38510259SAndrew.Bardsley@arm.com 38610259SAndrew.Bardsley@arm.com resumeSerialize = false; 38710259SAndrew.Bardsley@arm.com serializeInst[tid] = NULL; 38810259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == SerializeStall) { 38910259SAndrew.Bardsley@arm.com if (serializeInst[tid]->seqNum <= squash_seq_num) { 39010259SAndrew.Bardsley@arm.com DPRINTF(Rename, "Rename will resume serializing after squash\n"); 39110259SAndrew.Bardsley@arm.com resumeSerialize = true; 39210259SAndrew.Bardsley@arm.com assert(serializeInst[tid]); 39310259SAndrew.Bardsley@arm.com } else { 39410259SAndrew.Bardsley@arm.com resumeSerialize = false; 39510259SAndrew.Bardsley@arm.com toDecode->renameUnblock[tid] = 1; 39610259SAndrew.Bardsley@arm.com 39710259SAndrew.Bardsley@arm.com serializeInst[tid] = NULL; 39810259SAndrew.Bardsley@arm.com } 39910259SAndrew.Bardsley@arm.com } 40010259SAndrew.Bardsley@arm.com 40110259SAndrew.Bardsley@arm.com // Set the status to Squashing. 40210259SAndrew.Bardsley@arm.com renameStatus[tid] = Squashing; 40310259SAndrew.Bardsley@arm.com 40410259SAndrew.Bardsley@arm.com // Squash any instructions from decode. 40510259SAndrew.Bardsley@arm.com for (int i=0; i<fromDecode->size; i++) { 40610259SAndrew.Bardsley@arm.com if (fromDecode->insts[i]->threadNumber == tid && 40710259SAndrew.Bardsley@arm.com fromDecode->insts[i]->seqNum > squash_seq_num) { 40810259SAndrew.Bardsley@arm.com fromDecode->insts[i]->setSquashed(); 40910259SAndrew.Bardsley@arm.com wroteToTimeBuffer = true; 41010259SAndrew.Bardsley@arm.com } 41110259SAndrew.Bardsley@arm.com 41210259SAndrew.Bardsley@arm.com } 41310259SAndrew.Bardsley@arm.com 41410259SAndrew.Bardsley@arm.com // Clear the instruction list and skid buffer in case they have any 41510259SAndrew.Bardsley@arm.com // insts in them. 41610259SAndrew.Bardsley@arm.com insts[tid].clear(); 41710259SAndrew.Bardsley@arm.com 41810259SAndrew.Bardsley@arm.com // Clear the skid buffer in case it has any data in it. 41910259SAndrew.Bardsley@arm.com skidBuffer[tid].clear(); 42010259SAndrew.Bardsley@arm.com 42110259SAndrew.Bardsley@arm.com doSquash(squash_seq_num, tid); 42210259SAndrew.Bardsley@arm.com} 42310259SAndrew.Bardsley@arm.com 42410259SAndrew.Bardsley@arm.comtemplate <class Impl> 42510259SAndrew.Bardsley@arm.comvoid 42610259SAndrew.Bardsley@arm.comDefaultRename<Impl>::tick() 42710259SAndrew.Bardsley@arm.com{ 42810259SAndrew.Bardsley@arm.com wroteToTimeBuffer = false; 42910259SAndrew.Bardsley@arm.com 43010259SAndrew.Bardsley@arm.com blockThisCycle = false; 43110259SAndrew.Bardsley@arm.com 43210259SAndrew.Bardsley@arm.com bool status_change = false; 43310259SAndrew.Bardsley@arm.com 43410259SAndrew.Bardsley@arm.com toIEWIndex = 0; 43510259SAndrew.Bardsley@arm.com 43610259SAndrew.Bardsley@arm.com sortInsts(); 43710259SAndrew.Bardsley@arm.com 43810259SAndrew.Bardsley@arm.com list<ThreadID>::iterator threads = activeThreads->begin(); 43910259SAndrew.Bardsley@arm.com list<ThreadID>::iterator end = activeThreads->end(); 44010259SAndrew.Bardsley@arm.com 44110259SAndrew.Bardsley@arm.com // Check stall and squash signals. 44210259SAndrew.Bardsley@arm.com while (threads != end) { 44310259SAndrew.Bardsley@arm.com ThreadID tid = *threads++; 44410259SAndrew.Bardsley@arm.com 44510259SAndrew.Bardsley@arm.com DPRINTF(Rename, "Processing [tid:%i]\n", tid); 44610259SAndrew.Bardsley@arm.com 44710259SAndrew.Bardsley@arm.com status_change = checkSignalsAndUpdate(tid) || status_change; 44810259SAndrew.Bardsley@arm.com 44910259SAndrew.Bardsley@arm.com rename(status_change, tid); 45010259SAndrew.Bardsley@arm.com } 45110259SAndrew.Bardsley@arm.com 45210259SAndrew.Bardsley@arm.com if (status_change) { 45310259SAndrew.Bardsley@arm.com updateStatus(); 45410259SAndrew.Bardsley@arm.com } 45510259SAndrew.Bardsley@arm.com 45610259SAndrew.Bardsley@arm.com if (wroteToTimeBuffer) { 45710259SAndrew.Bardsley@arm.com DPRINTF(Activity, "Activity this cycle.\n"); 45810259SAndrew.Bardsley@arm.com cpu->activityThisCycle(); 45910259SAndrew.Bardsley@arm.com } 46010259SAndrew.Bardsley@arm.com 46110259SAndrew.Bardsley@arm.com threads = activeThreads->begin(); 46210259SAndrew.Bardsley@arm.com 46310259SAndrew.Bardsley@arm.com while (threads != end) { 46410259SAndrew.Bardsley@arm.com ThreadID tid = *threads++; 46510259SAndrew.Bardsley@arm.com 46610259SAndrew.Bardsley@arm.com // If we committed this cycle then doneSeqNum will be > 0 46710259SAndrew.Bardsley@arm.com if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 46810259SAndrew.Bardsley@arm.com !fromCommit->commitInfo[tid].squash && 46910259SAndrew.Bardsley@arm.com renameStatus[tid] != Squashing) { 47010259SAndrew.Bardsley@arm.com 47110259SAndrew.Bardsley@arm.com removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 47210259SAndrew.Bardsley@arm.com tid); 47310259SAndrew.Bardsley@arm.com } 47410259SAndrew.Bardsley@arm.com } 47510259SAndrew.Bardsley@arm.com 47610259SAndrew.Bardsley@arm.com // @todo: make into updateProgress function 47710259SAndrew.Bardsley@arm.com for (ThreadID tid = 0; tid < numThreads; tid++) { 47810259SAndrew.Bardsley@arm.com instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 47910259SAndrew.Bardsley@arm.com loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 48010259SAndrew.Bardsley@arm.com storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 48110259SAndrew.Bardsley@arm.com assert(loadsInProgress[tid] >= 0); 48210259SAndrew.Bardsley@arm.com assert(storesInProgress[tid] >= 0); 48310259SAndrew.Bardsley@arm.com assert(instsInProgress[tid] >=0); 48410259SAndrew.Bardsley@arm.com } 48510259SAndrew.Bardsley@arm.com 48610259SAndrew.Bardsley@arm.com} 48710259SAndrew.Bardsley@arm.com 48810259SAndrew.Bardsley@arm.comtemplate<class Impl> 48910259SAndrew.Bardsley@arm.comvoid 49010259SAndrew.Bardsley@arm.comDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 49110259SAndrew.Bardsley@arm.com{ 49210259SAndrew.Bardsley@arm.com // If status is Running or idle, 49310259SAndrew.Bardsley@arm.com // call renameInsts() 49410259SAndrew.Bardsley@arm.com // If status is Unblocking, 49510259SAndrew.Bardsley@arm.com // buffer any instructions coming from decode 49610259SAndrew.Bardsley@arm.com // continue trying to empty skid buffer 49710259SAndrew.Bardsley@arm.com // check if stall conditions have passed 49810259SAndrew.Bardsley@arm.com 49910259SAndrew.Bardsley@arm.com if (renameStatus[tid] == Blocked) { 50010259SAndrew.Bardsley@arm.com ++renameBlockCycles; 50110259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == Squashing) { 50210259SAndrew.Bardsley@arm.com ++renameSquashCycles; 50310259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == SerializeStall) { 50410259SAndrew.Bardsley@arm.com ++renameSerializeStallCycles; 50510259SAndrew.Bardsley@arm.com // If we are currently in SerializeStall and resumeSerialize 50610259SAndrew.Bardsley@arm.com // was set, then that means that we are resuming serializing 50710259SAndrew.Bardsley@arm.com // this cycle. Tell the previous stages to block. 50810259SAndrew.Bardsley@arm.com if (resumeSerialize) { 50910259SAndrew.Bardsley@arm.com resumeSerialize = false; 51010259SAndrew.Bardsley@arm.com block(tid); 51110259SAndrew.Bardsley@arm.com toDecode->renameUnblock[tid] = false; 51210259SAndrew.Bardsley@arm.com } 51310259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == Unblocking) { 51410259SAndrew.Bardsley@arm.com if (resumeUnblocking) { 51510259SAndrew.Bardsley@arm.com block(tid); 51610259SAndrew.Bardsley@arm.com resumeUnblocking = false; 51710259SAndrew.Bardsley@arm.com toDecode->renameUnblock[tid] = false; 51810259SAndrew.Bardsley@arm.com } 51910259SAndrew.Bardsley@arm.com } 52010259SAndrew.Bardsley@arm.com 52110259SAndrew.Bardsley@arm.com if (renameStatus[tid] == Running || 52210259SAndrew.Bardsley@arm.com renameStatus[tid] == Idle) { 52310259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 52410259SAndrew.Bardsley@arm.com "stage.\n", tid); 52510259SAndrew.Bardsley@arm.com 52610259SAndrew.Bardsley@arm.com renameInsts(tid); 52710259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == Unblocking) { 52810259SAndrew.Bardsley@arm.com renameInsts(tid); 52910259SAndrew.Bardsley@arm.com 53010259SAndrew.Bardsley@arm.com if (validInsts()) { 53110259SAndrew.Bardsley@arm.com // Add the current inputs to the skid buffer so they can be 53210259SAndrew.Bardsley@arm.com // reprocessed when this stage unblocks. 53310259SAndrew.Bardsley@arm.com skidInsert(tid); 53410259SAndrew.Bardsley@arm.com } 53510259SAndrew.Bardsley@arm.com 53610259SAndrew.Bardsley@arm.com // If we switched over to blocking, then there's a potential for 53710259SAndrew.Bardsley@arm.com // an overall status change. 53810259SAndrew.Bardsley@arm.com status_change = unblock(tid) || status_change || blockThisCycle; 53910259SAndrew.Bardsley@arm.com } 54010259SAndrew.Bardsley@arm.com} 54110259SAndrew.Bardsley@arm.com 54210259SAndrew.Bardsley@arm.comtemplate <class Impl> 54310259SAndrew.Bardsley@arm.comvoid 54410259SAndrew.Bardsley@arm.comDefaultRename<Impl>::renameInsts(ThreadID tid) 54510259SAndrew.Bardsley@arm.com{ 54610259SAndrew.Bardsley@arm.com // Instructions can be either in the skid buffer or the queue of 54710259SAndrew.Bardsley@arm.com // instructions coming from decode, depending on the status. 54810259SAndrew.Bardsley@arm.com int insts_available = renameStatus[tid] == Unblocking ? 54910259SAndrew.Bardsley@arm.com skidBuffer[tid].size() : insts[tid].size(); 55010259SAndrew.Bardsley@arm.com 55110259SAndrew.Bardsley@arm.com // Check the decode queue to see if instructions are available. 55210259SAndrew.Bardsley@arm.com // If there are no available instructions to rename, then do nothing. 55310259SAndrew.Bardsley@arm.com if (insts_available == 0) { 55410259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 55510259SAndrew.Bardsley@arm.com tid); 55610259SAndrew.Bardsley@arm.com // Should I change status to idle? 55710259SAndrew.Bardsley@arm.com ++renameIdleCycles; 55810259SAndrew.Bardsley@arm.com return; 55910259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == Unblocking) { 56010259SAndrew.Bardsley@arm.com ++renameUnblockCycles; 56110259SAndrew.Bardsley@arm.com } else if (renameStatus[tid] == Running) { 56210259SAndrew.Bardsley@arm.com ++renameRunCycles; 56310259SAndrew.Bardsley@arm.com } 56410259SAndrew.Bardsley@arm.com 56510259SAndrew.Bardsley@arm.com // Will have to do a different calculation for the number of free 56610259SAndrew.Bardsley@arm.com // entries. 56710259SAndrew.Bardsley@arm.com int free_rob_entries = calcFreeROBEntries(tid); 56810259SAndrew.Bardsley@arm.com int free_iq_entries = calcFreeIQEntries(tid); 56910259SAndrew.Bardsley@arm.com int min_free_entries = free_rob_entries; 57010259SAndrew.Bardsley@arm.com 57110259SAndrew.Bardsley@arm.com FullSource source = ROB; 57210259SAndrew.Bardsley@arm.com 57310259SAndrew.Bardsley@arm.com if (free_iq_entries < min_free_entries) { 57410259SAndrew.Bardsley@arm.com min_free_entries = free_iq_entries; 57510259SAndrew.Bardsley@arm.com source = IQ; 57610259SAndrew.Bardsley@arm.com } 57710259SAndrew.Bardsley@arm.com 57810259SAndrew.Bardsley@arm.com // Check if there's any space left. 57910259SAndrew.Bardsley@arm.com if (min_free_entries <= 0) { 58010259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 58110259SAndrew.Bardsley@arm.com "entries.\n" 58210259SAndrew.Bardsley@arm.com "ROB has %i free entries.\n" 58310259SAndrew.Bardsley@arm.com "IQ has %i free entries.\n", 58410259SAndrew.Bardsley@arm.com tid, 58510259SAndrew.Bardsley@arm.com free_rob_entries, 58610259SAndrew.Bardsley@arm.com free_iq_entries); 58710259SAndrew.Bardsley@arm.com 58810259SAndrew.Bardsley@arm.com blockThisCycle = true; 58910259SAndrew.Bardsley@arm.com 59010259SAndrew.Bardsley@arm.com block(tid); 59110259SAndrew.Bardsley@arm.com 59210259SAndrew.Bardsley@arm.com incrFullStat(source); 59310259SAndrew.Bardsley@arm.com 59410259SAndrew.Bardsley@arm.com return; 59510259SAndrew.Bardsley@arm.com } else if (min_free_entries < insts_available) { 59610259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 59710259SAndrew.Bardsley@arm.com "%i insts available, but only %i insts can be " 59810259SAndrew.Bardsley@arm.com "renamed due to ROB/IQ/LSQ limits.\n", 59910259SAndrew.Bardsley@arm.com tid, insts_available, min_free_entries); 60010259SAndrew.Bardsley@arm.com 60110259SAndrew.Bardsley@arm.com insts_available = min_free_entries; 60210259SAndrew.Bardsley@arm.com 60310259SAndrew.Bardsley@arm.com blockThisCycle = true; 60410259SAndrew.Bardsley@arm.com 60510259SAndrew.Bardsley@arm.com incrFullStat(source); 60610259SAndrew.Bardsley@arm.com } 60710259SAndrew.Bardsley@arm.com 60810259SAndrew.Bardsley@arm.com InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 60910259SAndrew.Bardsley@arm.com skidBuffer[tid] : insts[tid]; 61010259SAndrew.Bardsley@arm.com 61110259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: %i available instructions to " 61210259SAndrew.Bardsley@arm.com "send iew.\n", tid, insts_available); 61310259SAndrew.Bardsley@arm.com 61410259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 61510259SAndrew.Bardsley@arm.com "dispatched to IQ last cycle.\n", 61610259SAndrew.Bardsley@arm.com tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 61710259SAndrew.Bardsley@arm.com 61810259SAndrew.Bardsley@arm.com // Handle serializing the next instruction if necessary. 61910259SAndrew.Bardsley@arm.com if (serializeOnNextInst[tid]) { 62010259SAndrew.Bardsley@arm.com if (emptyROB[tid] && instsInProgress[tid] == 0) { 62110259SAndrew.Bardsley@arm.com // ROB already empty; no need to serialize. 62210259SAndrew.Bardsley@arm.com serializeOnNextInst[tid] = false; 62310259SAndrew.Bardsley@arm.com } else if (!insts_to_rename.empty()) { 62410259SAndrew.Bardsley@arm.com insts_to_rename.front()->setSerializeBefore(); 62510259SAndrew.Bardsley@arm.com } 62610259SAndrew.Bardsley@arm.com } 62710259SAndrew.Bardsley@arm.com 62810259SAndrew.Bardsley@arm.com int renamed_insts = 0; 62910259SAndrew.Bardsley@arm.com 63010259SAndrew.Bardsley@arm.com while (insts_available > 0 && toIEWIndex < renameWidth) { 63110259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 63210259SAndrew.Bardsley@arm.com 63310259SAndrew.Bardsley@arm.com assert(!insts_to_rename.empty()); 63410259SAndrew.Bardsley@arm.com 63510259SAndrew.Bardsley@arm.com DynInstPtr inst = insts_to_rename.front(); 63610259SAndrew.Bardsley@arm.com 63710259SAndrew.Bardsley@arm.com //For all kind of instructions, check ROB and IQ first 63810259SAndrew.Bardsley@arm.com //For load instruction, check LQ size and take into account the inflight loads 63910259SAndrew.Bardsley@arm.com //For store instruction, check SQ size and take into account the inflight stores 64010259SAndrew.Bardsley@arm.com 64110259SAndrew.Bardsley@arm.com if (inst->isLoad()) { 64210259SAndrew.Bardsley@arm.com if (calcFreeLQEntries(tid) <= 0) { 64310259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 64410259SAndrew.Bardsley@arm.com source = LQ; 64510259SAndrew.Bardsley@arm.com incrFullStat(source); 64610259SAndrew.Bardsley@arm.com break; 64710259SAndrew.Bardsley@arm.com } 64810259SAndrew.Bardsley@arm.com } 64910259SAndrew.Bardsley@arm.com 65010259SAndrew.Bardsley@arm.com if (inst->isStore()) { 65110259SAndrew.Bardsley@arm.com if (calcFreeSQEntries(tid) <= 0) { 65210259SAndrew.Bardsley@arm.com DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 65310259SAndrew.Bardsley@arm.com source = SQ; 65410259SAndrew.Bardsley@arm.com incrFullStat(source); 65510259SAndrew.Bardsley@arm.com break; 65610259SAndrew.Bardsley@arm.com } 65710259SAndrew.Bardsley@arm.com } 65810259SAndrew.Bardsley@arm.com 659 insts_to_rename.pop_front(); 660 661 if (renameStatus[tid] == Unblocking) { 662 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 663 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 664 } 665 666 if (inst->isSquashed()) { 667 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 668 "squashed, skipping.\n", tid, inst->seqNum, 669 inst->pcState()); 670 671 ++renameSquashedInsts; 672 673 // Decrement how many instructions are available. 674 --insts_available; 675 676 continue; 677 } 678 679 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 680 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 681 682 // Check here to make sure there are enough destination registers 683 // to rename to. Otherwise block. 684 if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 685 inst->numFPDestRegs(), 686 inst->numVecDestRegs(), 687 inst->numVecElemDestRegs(), 688 inst->numVecPredDestRegs(), 689 inst->numCCDestRegs())) { 690 DPRINTF(Rename, "Blocking due to lack of free " 691 "physical registers to rename to.\n"); 692 blockThisCycle = true; 693 insts_to_rename.push_front(inst); 694 ++renameFullRegistersEvents; 695 696 break; 697 } 698 699 // Handle serializeAfter/serializeBefore instructions. 700 // serializeAfter marks the next instruction as serializeBefore. 701 // serializeBefore makes the instruction wait in rename until the ROB 702 // is empty. 703 704 // In this model, IPR accesses are serialize before 705 // instructions, and store conditionals are serialize after 706 // instructions. This is mainly due to lack of support for 707 // out-of-order operations of either of those classes of 708 // instructions. 709 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 710 !inst->isSerializeHandled()) { 711 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 712 713 if (!inst->isTempSerializeBefore()) { 714 renamedSerializing++; 715 inst->setSerializeHandled(); 716 } else { 717 renamedTempSerializing++; 718 } 719 720 // Change status over to SerializeStall so that other stages know 721 // what this is blocked on. 722 renameStatus[tid] = SerializeStall; 723 724 serializeInst[tid] = inst; 725 726 blockThisCycle = true; 727 728 break; 729 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 730 !inst->isSerializeHandled()) { 731 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 732 733 renamedSerializing++; 734 735 inst->setSerializeHandled(); 736 737 serializeAfter(insts_to_rename, tid); 738 } 739 740 renameSrcRegs(inst, inst->threadNumber); 741 742 renameDestRegs(inst, inst->threadNumber); 743 744 if (inst->isLoad()) { 745 loadsInProgress[tid]++; 746 } 747 if (inst->isStore()) { 748 storesInProgress[tid]++; 749 } 750 ++renamed_insts; 751 // Notify potential listeners that source and destination registers for 752 // this instruction have been renamed. 753 ppRename->notify(inst); 754 755 // Put instruction in rename queue. 756 toIEW->insts[toIEWIndex] = inst; 757 ++(toIEW->size); 758 759 // Increment which instruction we're on. 760 ++toIEWIndex; 761 762 // Decrement how many instructions are available. 763 --insts_available; 764 } 765 766 instsInProgress[tid] += renamed_insts; 767 renameRenamedInsts += renamed_insts; 768 769 // If we wrote to the time buffer, record this. 770 if (toIEWIndex) { 771 wroteToTimeBuffer = true; 772 } 773 774 // Check if there's any instructions left that haven't yet been renamed. 775 // If so then block. 776 if (insts_available) { 777 blockThisCycle = true; 778 } 779 780 if (blockThisCycle) { 781 block(tid); 782 toDecode->renameUnblock[tid] = false; 783 } 784} 785 786template<class Impl> 787void 788DefaultRename<Impl>::skidInsert(ThreadID tid) 789{ 790 DynInstPtr inst = NULL; 791 792 while (!insts[tid].empty()) { 793 inst = insts[tid].front(); 794 795 insts[tid].pop_front(); 796 797 assert(tid == inst->threadNumber); 798 799 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 800 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 801 802 ++renameSkidInsts; 803 804 skidBuffer[tid].push_back(inst); 805 } 806 807 if (skidBuffer[tid].size() > skidBufferMax) 808 { 809 typename InstQueue::iterator it; 810 warn("Skidbuffer contents:\n"); 811 for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 812 { 813 warn("[tid:%u]: %s [sn:%i].\n", tid, 814 (*it)->staticInst->disassemble(inst->instAddr()), 815 (*it)->seqNum); 816 } 817 panic("Skidbuffer Exceeded Max Size"); 818 } 819} 820 821template <class Impl> 822void 823DefaultRename<Impl>::sortInsts() 824{ 825 int insts_from_decode = fromDecode->size; 826 for (int i = 0; i < insts_from_decode; ++i) { 827 const DynInstPtr &inst = fromDecode->insts[i]; 828 insts[inst->threadNumber].push_back(inst); 829#if TRACING_ON 830 if (DTRACE(O3PipeView)) { 831 inst->renameTick = curTick() - inst->fetchTick; 832 } 833#endif 834 } 835} 836 837template<class Impl> 838bool 839DefaultRename<Impl>::skidsEmpty() 840{ 841 list<ThreadID>::iterator threads = activeThreads->begin(); 842 list<ThreadID>::iterator end = activeThreads->end(); 843 844 while (threads != end) { 845 ThreadID tid = *threads++; 846 847 if (!skidBuffer[tid].empty()) 848 return false; 849 } 850 851 return true; 852} 853 854template<class Impl> 855void 856DefaultRename<Impl>::updateStatus() 857{ 858 bool any_unblocking = false; 859 860 list<ThreadID>::iterator threads = activeThreads->begin(); 861 list<ThreadID>::iterator end = activeThreads->end(); 862 863 while (threads != end) { 864 ThreadID tid = *threads++; 865 866 if (renameStatus[tid] == Unblocking) { 867 any_unblocking = true; 868 break; 869 } 870 } 871 872 // Rename will have activity if it's unblocking. 873 if (any_unblocking) { 874 if (_status == Inactive) { 875 _status = Active; 876 877 DPRINTF(Activity, "Activating stage.\n"); 878 879 cpu->activateStage(O3CPU::RenameIdx); 880 } 881 } else { 882 // If it's not unblocking, then rename will not have any internal 883 // activity. Switch it to inactive. 884 if (_status == Active) { 885 _status = Inactive; 886 DPRINTF(Activity, "Deactivating stage.\n"); 887 888 cpu->deactivateStage(O3CPU::RenameIdx); 889 } 890 } 891} 892 893template <class Impl> 894bool 895DefaultRename<Impl>::block(ThreadID tid) 896{ 897 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 898 899 // Add the current inputs onto the skid buffer, so they can be 900 // reprocessed when this stage unblocks. 901 skidInsert(tid); 902 903 // Only signal backwards to block if the previous stages do not think 904 // rename is already blocked. 905 if (renameStatus[tid] != Blocked) { 906 // If resumeUnblocking is set, we unblocked during the squash, 907 // but now we're have unblocking status. We need to tell earlier 908 // stages to block. 909 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 910 toDecode->renameBlock[tid] = true; 911 toDecode->renameUnblock[tid] = false; 912 wroteToTimeBuffer = true; 913 } 914 915 // Rename can not go from SerializeStall to Blocked, otherwise 916 // it would not know to complete the serialize stall. 917 if (renameStatus[tid] != SerializeStall) { 918 // Set status to Blocked. 919 renameStatus[tid] = Blocked; 920 return true; 921 } 922 } 923 924 return false; 925} 926 927template <class Impl> 928bool 929DefaultRename<Impl>::unblock(ThreadID tid) 930{ 931 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 932 933 // Rename is done unblocking if the skid buffer is empty. 934 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 935 936 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 937 938 toDecode->renameUnblock[tid] = true; 939 wroteToTimeBuffer = true; 940 941 renameStatus[tid] = Running; 942 return true; 943 } 944 945 return false; 946} 947 948template <class Impl> 949void 950DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 951{ 952 typename std::list<RenameHistory>::iterator hb_it = 953 historyBuffer[tid].begin(); 954 955 // After a syscall squashes everything, the history buffer may be empty 956 // but the ROB may still be squashing instructions. 957 // Go through the most recent instructions, undoing the mappings 958 // they did and freeing up the registers. 959 while (!historyBuffer[tid].empty() && 960 hb_it->instSeqNum > squashed_seq_num) { 961 assert(hb_it != historyBuffer[tid].end()); 962 963 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 964 "number %i.\n", tid, hb_it->instSeqNum); 965 966 // Undo the rename mapping only if it was really a change. 967 // Special regs that are not really renamed (like misc regs 968 // and the zero reg) can be recognized because the new mapping 969 // is the same as the old one. While it would be merely a 970 // waste of time to update the rename table, we definitely 971 // don't want to put these on the free list. 972 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 973 // Tell the rename map to set the architected register to the 974 // previous physical register that it was renamed to. 975 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 976 977 // Put the renamed physical register back on the free list. 978 freeList->addReg(hb_it->newPhysReg); 979 } 980 981 // Notify potential listeners that the register mapping needs to be 982 // removed because the instruction it was mapped to got squashed. Note 983 // that this is done before hb_it is incremented. 984 ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 985 hb_it->newPhysReg)); 986 987 historyBuffer[tid].erase(hb_it++); 988 989 ++renameUndoneMaps; 990 } 991 992 // Check if we need to change vector renaming mode after squashing 993 cpu->switchRenameMode(tid, freeList); 994} 995 996template<class Impl> 997void 998DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 999{ 1000 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 1001 "history buffer %u (size=%i), until [sn:%lli].\n", 1002 tid, tid, historyBuffer[tid].size(), inst_seq_num); 1003 1004 typename std::list<RenameHistory>::iterator hb_it = 1005 historyBuffer[tid].end(); 1006 1007 --hb_it; 1008 1009 if (historyBuffer[tid].empty()) { 1010 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 1011 return; 1012 } else if (hb_it->instSeqNum > inst_seq_num) { 1013 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 1014 "that a syscall happened recently.\n", tid); 1015 return; 1016 } 1017 1018 // Commit all the renames up until (and including) the committed sequence 1019 // number. Some or even all of the committed instructions may not have 1020 // rename histories if they did not have destination registers that were 1021 // renamed. 1022 while (!historyBuffer[tid].empty() && 1023 hb_it != historyBuffer[tid].end() && 1024 hb_it->instSeqNum <= inst_seq_num) { 1025 1026 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 1027 "[sn:%lli].\n", 1028 tid, hb_it->prevPhysReg->index(), 1029 hb_it->prevPhysReg->className(), 1030 hb_it->instSeqNum); 1031 1032 // Don't free special phys regs like misc and zero regs, which 1033 // can be recognized because the new mapping is the same as 1034 // the old one. 1035 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 1036 freeList->addReg(hb_it->prevPhysReg); 1037 } 1038 1039 ++renameCommittedMaps; 1040 1041 historyBuffer[tid].erase(hb_it--); 1042 } 1043} 1044 1045template <class Impl> 1046inline void 1047DefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 1048{ 1049 ThreadContext *tc = inst->tcBase(); 1050 RenameMap *map = renameMap[tid]; 1051 unsigned num_src_regs = inst->numSrcRegs(); 1052 1053 // Get the architectual register numbers from the source and 1054 // operands, and redirect them to the right physical register. 1055 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 1056 const RegId& src_reg = inst->srcRegIdx(src_idx); 1057 PhysRegIdPtr renamed_reg; 1058 1059 renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 1060 switch (src_reg.classValue()) { 1061 case IntRegClass: 1062 intRenameLookups++; 1063 break; 1064 case FloatRegClass: 1065 fpRenameLookups++; 1066 break; 1067 case VecRegClass: 1068 case VecElemClass: 1069 vecRenameLookups++; 1070 break; 1071 case VecPredRegClass: 1072 vecPredRenameLookups++; 1073 break; 1074 case CCRegClass: 1075 case MiscRegClass: 1076 break; 1077 1078 default: 1079 panic("Invalid register class: %d.", src_reg.classValue()); 1080 } 1081 1082 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 1083 ", got phys reg %i (%s)\n", tid, 1084 src_reg.className(), src_reg.index(), 1085 renamed_reg->index(), 1086 renamed_reg->className()); 1087 1088 inst->renameSrcReg(src_idx, renamed_reg); 1089 1090 // See if the register is ready or not. 1091 if (scoreboard->getReg(renamed_reg)) { 1092 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1093 " is ready.\n", tid, renamed_reg->index(), 1094 renamed_reg->flatIndex(), 1095 renamed_reg->className()); 1096 1097 inst->markSrcRegReady(src_idx); 1098 } else { 1099 DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 1100 " is not ready.\n", tid, renamed_reg->index(), 1101 renamed_reg->flatIndex(), 1102 renamed_reg->className()); 1103 } 1104 1105 ++renameRenameLookups; 1106 } 1107} 1108 1109template <class Impl> 1110inline void 1111DefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 1112{ 1113 ThreadContext *tc = inst->tcBase(); 1114 RenameMap *map = renameMap[tid]; 1115 unsigned num_dest_regs = inst->numDestRegs(); 1116 1117 // Rename the destination registers. 1118 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1119 const RegId& dest_reg = inst->destRegIdx(dest_idx); 1120 typename RenameMap::RenameInfo rename_result; 1121 1122 RegId flat_dest_regid = tc->flattenRegId(dest_reg); 1123 1124 rename_result = map->rename(flat_dest_regid); 1125 1126 inst->flattenDestReg(dest_idx, flat_dest_regid); 1127 1128 // Mark Scoreboard entry as not ready 1129 scoreboard->unsetReg(rename_result.first); 1130 1131 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 1132 "reg %i (%i).\n", tid, dest_reg.index(), 1133 dest_reg.className(), 1134 rename_result.first->index(), 1135 rename_result.first->flatIndex()); 1136 1137 // Record the rename information so that a history can be kept. 1138 RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 1139 rename_result.first, 1140 rename_result.second); 1141 1142 historyBuffer[tid].push_front(hb_entry); 1143 1144 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1145 "(size=%i), [sn:%lli].\n",tid, 1146 historyBuffer[tid].size(), 1147 (*historyBuffer[tid].begin()).instSeqNum); 1148 1149 // Tell the instruction to rename the appropriate destination 1150 // register (dest_idx) to the new physical register 1151 // (rename_result.first), and record the previous physical 1152 // register that the same logical register was renamed to 1153 // (rename_result.second). 1154 inst->renameDestReg(dest_idx, 1155 rename_result.first, 1156 rename_result.second); 1157 1158 ++renameRenamedOperands; 1159 } 1160} 1161 1162template <class Impl> 1163inline int 1164DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1165{ 1166 int num_free = freeEntries[tid].robEntries - 1167 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1168 1169 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1170 1171 return num_free; 1172} 1173 1174template <class Impl> 1175inline int 1176DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1177{ 1178 int num_free = freeEntries[tid].iqEntries - 1179 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1180 1181 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1182 1183 return num_free; 1184} 1185 1186template <class Impl> 1187inline int 1188DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1189{ 1190 int num_free = freeEntries[tid].lqEntries - 1191 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1192 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1193 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1194 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1195 return num_free; 1196} 1197 1198template <class Impl> 1199inline int 1200DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1201{ 1202 int num_free = freeEntries[tid].sqEntries - 1203 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1204 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1205 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1206 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1207 return num_free; 1208} 1209 1210template <class Impl> 1211unsigned 1212DefaultRename<Impl>::validInsts() 1213{ 1214 unsigned inst_count = 0; 1215 1216 for (int i=0; i<fromDecode->size; i++) { 1217 if (!fromDecode->insts[i]->isSquashed()) 1218 inst_count++; 1219 } 1220 1221 return inst_count; 1222} 1223 1224template <class Impl> 1225void 1226DefaultRename<Impl>::readStallSignals(ThreadID tid) 1227{ 1228 if (fromIEW->iewBlock[tid]) { 1229 stalls[tid].iew = true; 1230 } 1231 1232 if (fromIEW->iewUnblock[tid]) { 1233 assert(stalls[tid].iew); 1234 stalls[tid].iew = false; 1235 } 1236} 1237 1238template <class Impl> 1239bool 1240DefaultRename<Impl>::checkStall(ThreadID tid) 1241{ 1242 bool ret_val = false; 1243 1244 if (stalls[tid].iew) { 1245 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1246 ret_val = true; 1247 } else if (calcFreeROBEntries(tid) <= 0) { 1248 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1249 ret_val = true; 1250 } else if (calcFreeIQEntries(tid) <= 0) { 1251 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1252 ret_val = true; 1253 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1254 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1255 ret_val = true; 1256 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1257 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1258 ret_val = true; 1259 } else if (renameStatus[tid] == SerializeStall && 1260 (!emptyROB[tid] || instsInProgress[tid])) { 1261 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1262 "empty.\n", 1263 tid); 1264 ret_val = true; 1265 } 1266 1267 return ret_val; 1268} 1269 1270template <class Impl> 1271void 1272DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1273{ 1274 if (fromIEW->iewInfo[tid].usedIQ) 1275 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1276 1277 if (fromIEW->iewInfo[tid].usedLSQ) { 1278 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1279 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1280 } 1281 1282 if (fromCommit->commitInfo[tid].usedROB) { 1283 freeEntries[tid].robEntries = 1284 fromCommit->commitInfo[tid].freeROBEntries; 1285 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1286 } 1287 1288 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1289 "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n", 1290 tid, 1291 freeEntries[tid].iqEntries, 1292 freeEntries[tid].robEntries, 1293 freeEntries[tid].lqEntries, 1294 freeEntries[tid].sqEntries, 1295 renameMap[tid]->numFreeEntries(), 1296 renameMap[tid]->numFreeIntEntries(), 1297 renameMap[tid]->numFreeFloatEntries(), 1298 renameMap[tid]->numFreeVecEntries(), 1299 renameMap[tid]->numFreePredEntries(), 1300 renameMap[tid]->numFreeCCEntries()); 1301 1302 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1303 tid, instsInProgress[tid]); 1304} 1305 1306template <class Impl> 1307bool 1308DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1309{ 1310 // Check if there's a squash signal, squash if there is 1311 // Check stall signals, block if necessary. 1312 // If status was blocked 1313 // check if stall conditions have passed 1314 // if so then go to unblocking 1315 // If status was Squashing 1316 // check if squashing is not high. Switch to running this cycle. 1317 // If status was serialize stall 1318 // check if ROB is empty and no insts are in flight to the ROB 1319 1320 readFreeEntries(tid); 1321 readStallSignals(tid); 1322 1323 if (fromCommit->commitInfo[tid].squash) { 1324 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1325 "commit.\n", tid); 1326 1327 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1328 1329 return true; 1330 } 1331 1332 if (checkStall(tid)) { 1333 return block(tid); 1334 } 1335 1336 if (renameStatus[tid] == Blocked) { 1337 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1338 tid); 1339 1340 renameStatus[tid] = Unblocking; 1341 1342 unblock(tid); 1343 1344 return true; 1345 } 1346 1347 if (renameStatus[tid] == Squashing) { 1348 // Switch status to running if rename isn't being told to block or 1349 // squash this cycle. 1350 if (resumeSerialize) { 1351 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1352 tid); 1353 1354 renameStatus[tid] = SerializeStall; 1355 return true; 1356 } else if (resumeUnblocking) { 1357 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1358 tid); 1359 renameStatus[tid] = Unblocking; 1360 return true; 1361 } else { 1362 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1363 tid); 1364 1365 renameStatus[tid] = Running; 1366 return false; 1367 } 1368 } 1369 1370 if (renameStatus[tid] == SerializeStall) { 1371 // Stall ends once the ROB is free. 1372 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1373 "unblocking.\n", tid); 1374 1375 DynInstPtr serial_inst = serializeInst[tid]; 1376 1377 renameStatus[tid] = Unblocking; 1378 1379 unblock(tid); 1380 1381 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1382 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1383 1384 // Put instruction into queue here. 1385 serial_inst->clearSerializeBefore(); 1386 1387 if (!skidBuffer[tid].empty()) { 1388 skidBuffer[tid].push_front(serial_inst); 1389 } else { 1390 insts[tid].push_front(serial_inst); 1391 } 1392 1393 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1394 " Adding to front of list.\n", tid); 1395 1396 serializeInst[tid] = NULL; 1397 1398 return true; 1399 } 1400 1401 // If we've reached this point, we have not gotten any signals that 1402 // cause rename to change its status. Rename remains the same as before. 1403 return false; 1404} 1405 1406template<class Impl> 1407void 1408DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1409{ 1410 if (inst_list.empty()) { 1411 // Mark a bit to say that I must serialize on the next instruction. 1412 serializeOnNextInst[tid] = true; 1413 return; 1414 } 1415 1416 // Set the next instruction as serializing. 1417 inst_list.front()->setSerializeBefore(); 1418} 1419 1420template <class Impl> 1421inline void 1422DefaultRename<Impl>::incrFullStat(const FullSource &source) 1423{ 1424 switch (source) { 1425 case ROB: 1426 ++renameROBFullEvents; 1427 break; 1428 case IQ: 1429 ++renameIQFullEvents; 1430 break; 1431 case LQ: 1432 ++renameLQFullEvents; 1433 break; 1434 case SQ: 1435 ++renameSQFullEvents; 1436 break; 1437 default: 1438 panic("Rename full stall stat should be incremented for a reason!"); 1439 break; 1440 } 1441} 1442 1443template <class Impl> 1444void 1445DefaultRename<Impl>::dumpHistory() 1446{ 1447 typename std::list<RenameHistory>::iterator buf_it; 1448 1449 for (ThreadID tid = 0; tid < numThreads; tid++) { 1450 1451 buf_it = historyBuffer[tid].begin(); 1452 1453 while (buf_it != historyBuffer[tid].end()) { 1454 cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 1455 " %i[%s] Old phys reg: %i[%s]\n", 1456 (*buf_it).instSeqNum, 1457 (*buf_it).archReg.className(), 1458 (*buf_it).archReg.index(), 1459 (*buf_it).newPhysReg->index(), 1460 (*buf_it).newPhysReg->className(), 1461 (*buf_it).prevPhysReg->index(), 1462 (*buf_it).prevPhysReg->className()); 1463 1464 buf_it++; 1465 } 1466 } 1467} 1468 1469#endif//__CPU_O3_RENAME_IMPL_HH__ 1470