rename_impl.hh revision 12109 
1/*
2 * Copyright (c) 2010-2012, 2014-2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_RENAME_IMPL_HH__
46#define __CPU_O3_RENAME_IMPL_HH__
47
48#include <list>
49
50#include "arch/isa_traits.hh"
51#include "arch/registers.hh"
52#include "config/the_isa.hh"
53#include "cpu/o3/rename.hh"
54#include "cpu/reg_class.hh"
55#include "debug/Activity.hh"
56#include "debug/Rename.hh"
57#include "debug/O3PipeView.hh"
58#include "params/DerivO3CPU.hh"
59
60using namespace std;
61
62template <class Impl>
63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
64    : cpu(_cpu),
65      iewToRenameDelay(params->iewToRenameDelay),
66      decodeToRenameDelay(params->decodeToRenameDelay),
67      commitToRenameDelay(params->commitToRenameDelay),
68      renameWidth(params->renameWidth),
69      commitWidth(params->commitWidth),
70      numThreads(params->numThreads)
71{
72    if (renameWidth > Impl::MaxWidth)
73        fatal("renameWidth (%d) is larger than compiled limit (%d),\n"
74             "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
75             renameWidth, static_cast<int>(Impl::MaxWidth));
76
77    // @todo: Make into a parameter.
78    skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth;
79}
80
81template <class Impl>
82std::string
83DefaultRename<Impl>::name() const
84{
85    return cpu->name() + ".rename";
86}
87
88template <class Impl>
89void
90DefaultRename<Impl>::regStats()
91{
92    renameSquashCycles
93        .name(name() + ".SquashCycles")
94        .desc("Number of cycles rename is squashing")
95        .prereq(renameSquashCycles);
96    renameIdleCycles
97        .name(name() + ".IdleCycles")
98        .desc("Number of cycles rename is idle")
99        .prereq(renameIdleCycles);
100    renameBlockCycles
101        .name(name() + ".BlockCycles")
102        .desc("Number of cycles rename is blocking")
103        .prereq(renameBlockCycles);
104    renameSerializeStallCycles
105        .name(name() + ".serializeStallCycles")
106        .desc("count of cycles rename stalled for serializing inst")
107        .flags(Stats::total);
108    renameRunCycles
109        .name(name() + ".RunCycles")
110        .desc("Number of cycles rename is running")
111        .prereq(renameIdleCycles);
112    renameUnblockCycles
113        .name(name() + ".UnblockCycles")
114        .desc("Number of cycles rename is unblocking")
115        .prereq(renameUnblockCycles);
116    renameRenamedInsts
117        .name(name() + ".RenamedInsts")
118        .desc("Number of instructions processed by rename")
119        .prereq(renameRenamedInsts);
120    renameSquashedInsts
121        .name(name() + ".SquashedInsts")
122        .desc("Number of squashed instructions processed by rename")
123        .prereq(renameSquashedInsts);
124    renameROBFullEvents
125        .name(name() + ".ROBFullEvents")
126        .desc("Number of times rename has blocked due to ROB full")
127        .prereq(renameROBFullEvents);
128    renameIQFullEvents
129        .name(name() + ".IQFullEvents")
130        .desc("Number of times rename has blocked due to IQ full")
131        .prereq(renameIQFullEvents);
132    renameLQFullEvents
133        .name(name() + ".LQFullEvents")
134        .desc("Number of times rename has blocked due to LQ full")
135        .prereq(renameLQFullEvents);
136    renameSQFullEvents
137        .name(name() + ".SQFullEvents")
138        .desc("Number of times rename has blocked due to SQ full")
139        .prereq(renameSQFullEvents);
140    renameFullRegistersEvents
141        .name(name() + ".FullRegisterEvents")
142        .desc("Number of times there has been no free registers")
143        .prereq(renameFullRegistersEvents);
144    renameRenamedOperands
145        .name(name() + ".RenamedOperands")
146        .desc("Number of destination operands rename has renamed")
147        .prereq(renameRenamedOperands);
148    renameRenameLookups
149        .name(name() + ".RenameLookups")
150        .desc("Number of register rename lookups that rename has made")
151        .prereq(renameRenameLookups);
152    renameCommittedMaps
153        .name(name() + ".CommittedMaps")
154        .desc("Number of HB maps that are committed")
155        .prereq(renameCommittedMaps);
156    renameUndoneMaps
157        .name(name() + ".UndoneMaps")
158        .desc("Number of HB maps that are undone due to squashing")
159        .prereq(renameUndoneMaps);
160    renamedSerializing
161        .name(name() + ".serializingInsts")
162        .desc("count of serializing insts renamed")
163        .flags(Stats::total)
164        ;
165    renamedTempSerializing
166        .name(name() + ".tempSerializingInsts")
167        .desc("count of temporary serializing insts renamed")
168        .flags(Stats::total)
169        ;
170    renameSkidInsts
171        .name(name() + ".skidInsts")
172        .desc("count of insts added to the skid buffer")
173        .flags(Stats::total)
174        ;
175    intRenameLookups
176        .name(name() + ".int_rename_lookups")
177        .desc("Number of integer rename lookups")
178        .prereq(intRenameLookups);
179    fpRenameLookups
180        .name(name() + ".fp_rename_lookups")
181        .desc("Number of floating rename lookups")
182        .prereq(fpRenameLookups);
183    vecRenameLookups
184        .name(name() + ".vec_rename_lookups")
185        .desc("Number of vector rename lookups")
186        .prereq(vecRenameLookups);
187}
188
189template <class Impl>
190void
191DefaultRename<Impl>::regProbePoints()
192{
193    ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename");
194    ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(),
195                                                        "SquashInRename");
196}
197
198template <class Impl>
199void
200DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
201{
202    timeBuffer = tb_ptr;
203
204    // Setup wire to read information from time buffer, from IEW stage.
205    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
206
207    // Setup wire to read infromation from time buffer, from commit stage.
208    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
209
210    // Setup wire to write information to previous stages.
211    toDecode = timeBuffer->getWire(0);
212}
213
214template <class Impl>
215void
216DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
217{
218    renameQueue = rq_ptr;
219
220    // Setup wire to write information to future stages.
221    toIEW = renameQueue->getWire(0);
222}
223
224template <class Impl>
225void
226DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
227{
228    decodeQueue = dq_ptr;
229
230    // Setup wire to get information from decode.
231    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
232}
233
234template <class Impl>
235void
236DefaultRename<Impl>::startupStage()
237{
238    resetStage();
239}
240
241template <class Impl>
242void
243DefaultRename<Impl>::resetStage()
244{
245    _status = Inactive;
246
247    resumeSerialize = false;
248    resumeUnblocking = false;
249
250    // Grab the number of free entries directly from the stages.
251    for (ThreadID tid = 0; tid < numThreads; tid++) {
252        renameStatus[tid] = Idle;
253
254        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
255        freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid);
256        freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid);
257        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
258        emptyROB[tid] = true;
259
260        stalls[tid].iew = false;
261        serializeInst[tid] = NULL;
262
263        instsInProgress[tid] = 0;
264        loadsInProgress[tid] = 0;
265        storesInProgress[tid] = 0;
266
267        serializeOnNextInst[tid] = false;
268    }
269}
270
271template<class Impl>
272void
273DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
274{
275    activeThreads = at_ptr;
276}
277
278
279template <class Impl>
280void
281DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
282{
283    for (ThreadID tid = 0; tid < numThreads; tid++)
284        renameMap[tid] = &rm_ptr[tid];
285}
286
287template <class Impl>
288void
289DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
290{
291    freeList = fl_ptr;
292}
293
294template<class Impl>
295void
296DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
297{
298    scoreboard = _scoreboard;
299}
300
301template <class Impl>
302bool
303DefaultRename<Impl>::isDrained() const
304{
305    for (ThreadID tid = 0; tid < numThreads; tid++) {
306        if (instsInProgress[tid] != 0 ||
307            !historyBuffer[tid].empty() ||
308            !skidBuffer[tid].empty() ||
309            !insts[tid].empty() ||
310            (renameStatus[tid] != Idle && renameStatus[tid] != Running))
311            return false;
312    }
313    return true;
314}
315
316template <class Impl>
317void
318DefaultRename<Impl>::takeOverFrom()
319{
320    resetStage();
321}
322
323template <class Impl>
324void
325DefaultRename<Impl>::drainSanityCheck() const
326{
327    for (ThreadID tid = 0; tid < numThreads; tid++) {
328        assert(historyBuffer[tid].empty());
329        assert(insts[tid].empty());
330        assert(skidBuffer[tid].empty());
331        assert(instsInProgress[tid] == 0);
332    }
333}
334
335template <class Impl>
336void
337DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
338{
339    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
340
341    // Clear the stall signal if rename was blocked or unblocking before.
342    // If it still needs to block, the blocking should happen the next
343    // cycle and there should be space to hold everything due to the squash.
344    if (renameStatus[tid] == Blocked ||
345        renameStatus[tid] == Unblocking) {
346        toDecode->renameUnblock[tid] = 1;
347
348        resumeSerialize = false;
349        serializeInst[tid] = NULL;
350    } else if (renameStatus[tid] == SerializeStall) {
351        if (serializeInst[tid]->seqNum <= squash_seq_num) {
352            DPRINTF(Rename, "Rename will resume serializing after squash\n");
353            resumeSerialize = true;
354            assert(serializeInst[tid]);
355        } else {
356            resumeSerialize = false;
357            toDecode->renameUnblock[tid] = 1;
358
359            serializeInst[tid] = NULL;
360        }
361    }
362
363    // Set the status to Squashing.
364    renameStatus[tid] = Squashing;
365
366    // Squash any instructions from decode.
367    for (int i=0; i<fromDecode->size; i++) {
368        if (fromDecode->insts[i]->threadNumber == tid &&
369            fromDecode->insts[i]->seqNum > squash_seq_num) {
370            fromDecode->insts[i]->setSquashed();
371            wroteToTimeBuffer = true;
372        }
373
374    }
375
376    // Clear the instruction list and skid buffer in case they have any
377    // insts in them.
378    insts[tid].clear();
379
380    // Clear the skid buffer in case it has any data in it.
381    skidBuffer[tid].clear();
382
383    doSquash(squash_seq_num, tid);
384}
385
386template <class Impl>
387void
388DefaultRename<Impl>::tick()
389{
390    wroteToTimeBuffer = false;
391
392    blockThisCycle = false;
393
394    bool status_change = false;
395
396    toIEWIndex = 0;
397
398    sortInsts();
399
400    list<ThreadID>::iterator threads = activeThreads->begin();
401    list<ThreadID>::iterator end = activeThreads->end();
402
403    // Check stall and squash signals.
404    while (threads != end) {
405        ThreadID tid = *threads++;
406
407        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
408
409        status_change = checkSignalsAndUpdate(tid) || status_change;
410
411        rename(status_change, tid);
412    }
413
414    if (status_change) {
415        updateStatus();
416    }
417
418    if (wroteToTimeBuffer) {
419        DPRINTF(Activity, "Activity this cycle.\n");
420        cpu->activityThisCycle();
421    }
422
423    threads = activeThreads->begin();
424
425    while (threads != end) {
426        ThreadID tid = *threads++;
427
428        // If we committed this cycle then doneSeqNum will be > 0
429        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
430            !fromCommit->commitInfo[tid].squash &&
431            renameStatus[tid] != Squashing) {
432
433            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
434                                  tid);
435        }
436    }
437
438    // @todo: make into updateProgress function
439    for (ThreadID tid = 0; tid < numThreads; tid++) {
440        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
441        loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ;
442        storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ;
443        assert(loadsInProgress[tid] >= 0);
444        assert(storesInProgress[tid] >= 0);
445        assert(instsInProgress[tid] >=0);
446    }
447
448}
449
450template<class Impl>
451void
452DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
453{
454    // If status is Running or idle,
455    //     call renameInsts()
456    // If status is Unblocking,
457    //     buffer any instructions coming from decode
458    //     continue trying to empty skid buffer
459    //     check if stall conditions have passed
460
461    if (renameStatus[tid] == Blocked) {
462        ++renameBlockCycles;
463    } else if (renameStatus[tid] == Squashing) {
464        ++renameSquashCycles;
465    } else if (renameStatus[tid] == SerializeStall) {
466        ++renameSerializeStallCycles;
467        // If we are currently in SerializeStall and resumeSerialize
468        // was set, then that means that we are resuming serializing
469        // this cycle.  Tell the previous stages to block.
470        if (resumeSerialize) {
471            resumeSerialize = false;
472            block(tid);
473            toDecode->renameUnblock[tid] = false;
474        }
475    } else if (renameStatus[tid] == Unblocking) {
476        if (resumeUnblocking) {
477            block(tid);
478            resumeUnblocking = false;
479            toDecode->renameUnblock[tid] = false;
480        }
481    }
482
483    if (renameStatus[tid] == Running ||
484        renameStatus[tid] == Idle) {
485        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
486                "stage.\n", tid);
487
488        renameInsts(tid);
489    } else if (renameStatus[tid] == Unblocking) {
490        renameInsts(tid);
491
492        if (validInsts()) {
493            // Add the current inputs to the skid buffer so they can be
494            // reprocessed when this stage unblocks.
495            skidInsert(tid);
496        }
497
498        // If we switched over to blocking, then there's a potential for
499        // an overall status change.
500        status_change = unblock(tid) || status_change || blockThisCycle;
501    }
502}
503
504template <class Impl>
505void
506DefaultRename<Impl>::renameInsts(ThreadID tid)
507{
508    // Instructions can be either in the skid buffer or the queue of
509    // instructions coming from decode, depending on the status.
510    int insts_available = renameStatus[tid] == Unblocking ?
511        skidBuffer[tid].size() : insts[tid].size();
512
513    // Check the decode queue to see if instructions are available.
514    // If there are no available instructions to rename, then do nothing.
515    if (insts_available == 0) {
516        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
517                tid);
518        // Should I change status to idle?
519        ++renameIdleCycles;
520        return;
521    } else if (renameStatus[tid] == Unblocking) {
522        ++renameUnblockCycles;
523    } else if (renameStatus[tid] == Running) {
524        ++renameRunCycles;
525    }
526
527    DynInstPtr inst;
528
529    // Will have to do a different calculation for the number of free
530    // entries.
531    int free_rob_entries = calcFreeROBEntries(tid);
532    int free_iq_entries  = calcFreeIQEntries(tid);
533    int min_free_entries = free_rob_entries;
534
535    FullSource source = ROB;
536
537    if (free_iq_entries < min_free_entries) {
538        min_free_entries = free_iq_entries;
539        source = IQ;
540    }
541
542    // Check if there's any space left.
543    if (min_free_entries <= 0) {
544        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ "
545                "entries.\n"
546                "ROB has %i free entries.\n"
547                "IQ has %i free entries.\n",
548                tid,
549                free_rob_entries,
550                free_iq_entries);
551
552        blockThisCycle = true;
553
554        block(tid);
555
556        incrFullStat(source);
557
558        return;
559    } else if (min_free_entries < insts_available) {
560        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
561                "%i insts available, but only %i insts can be "
562                "renamed due to ROB/IQ/LSQ limits.\n",
563                tid, insts_available, min_free_entries);
564
565        insts_available = min_free_entries;
566
567        blockThisCycle = true;
568
569        incrFullStat(source);
570    }
571
572    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
573        skidBuffer[tid] : insts[tid];
574
575    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
576            "send iew.\n", tid, insts_available);
577
578    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
579            "dispatched to IQ last cycle.\n",
580            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
581
582    // Handle serializing the next instruction if necessary.
583    if (serializeOnNextInst[tid]) {
584        if (emptyROB[tid] && instsInProgress[tid] == 0) {
585            // ROB already empty; no need to serialize.
586            serializeOnNextInst[tid] = false;
587        } else if (!insts_to_rename.empty()) {
588            insts_to_rename.front()->setSerializeBefore();
589        }
590    }
591
592    int renamed_insts = 0;
593
594    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
595        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
596
597        assert(!insts_to_rename.empty());
598
599        inst = insts_to_rename.front();
600
601        //For all kind of instructions, check ROB and IQ first
602        //For load instruction, check LQ size and take into account the inflight loads
603        //For store instruction, check SQ size and take into account the inflight stores
604
605        if (inst->isLoad()) {
606            if (calcFreeLQEntries(tid) <= 0) {
607                DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n");
608                source = LQ;
609                incrFullStat(source);
610                break;
611            }
612        }
613
614        if (inst->isStore()) {
615            if (calcFreeSQEntries(tid) <= 0) {
616                DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n");
617                source = SQ;
618                incrFullStat(source);
619                break;
620            }
621        }
622
623        insts_to_rename.pop_front();
624
625        if (renameStatus[tid] == Unblocking) {
626            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename "
627                    "skidBuffer\n", tid, inst->seqNum, inst->pcState());
628        }
629
630        if (inst->isSquashed()) {
631            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is "
632                    "squashed, skipping.\n", tid, inst->seqNum,
633                    inst->pcState());
634
635            ++renameSquashedInsts;
636
637            // Decrement how many instructions are available.
638            --insts_available;
639
640            continue;
641        }
642
643        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
644                "PC %s.\n", tid, inst->seqNum, inst->pcState());
645
646        // Check here to make sure there are enough destination registers
647        // to rename to.  Otherwise block.
648        if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
649                                       inst->numFPDestRegs(),
650                                       inst->numVecDestRegs(),
651                                       inst->numVecElemDestRegs(),
652                                       inst->numCCDestRegs())) {
653            DPRINTF(Rename, "Blocking due to lack of free "
654                    "physical registers to rename to.\n");
655            blockThisCycle = true;
656            insts_to_rename.push_front(inst);
657            ++renameFullRegistersEvents;
658
659            break;
660        }
661
662        // Handle serializeAfter/serializeBefore instructions.
663        // serializeAfter marks the next instruction as serializeBefore.
664        // serializeBefore makes the instruction wait in rename until the ROB
665        // is empty.
666
667        // In this model, IPR accesses are serialize before
668        // instructions, and store conditionals are serialize after
669        // instructions.  This is mainly due to lack of support for
670        // out-of-order operations of either of those classes of
671        // instructions.
672        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
673            !inst->isSerializeHandled()) {
674            DPRINTF(Rename, "Serialize before instruction encountered.\n");
675
676            if (!inst->isTempSerializeBefore()) {
677                renamedSerializing++;
678                inst->setSerializeHandled();
679            } else {
680                renamedTempSerializing++;
681            }
682
683            // Change status over to SerializeStall so that other stages know
684            // what this is blocked on.
685            renameStatus[tid] = SerializeStall;
686
687            serializeInst[tid] = inst;
688
689            blockThisCycle = true;
690
691            break;
692        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
693                   !inst->isSerializeHandled()) {
694            DPRINTF(Rename, "Serialize after instruction encountered.\n");
695
696            renamedSerializing++;
697
698            inst->setSerializeHandled();
699
700            serializeAfter(insts_to_rename, tid);
701        }
702
703        renameSrcRegs(inst, inst->threadNumber);
704
705        renameDestRegs(inst, inst->threadNumber);
706
707        if (inst->isLoad()) {
708                loadsInProgress[tid]++;
709        }
710        if (inst->isStore()) {
711                storesInProgress[tid]++;
712        }
713        ++renamed_insts;
714        // Notify potential listeners that source and destination registers for
715        // this instruction have been renamed.
716        ppRename->notify(inst);
717
718        // Put instruction in rename queue.
719        toIEW->insts[toIEWIndex] = inst;
720        ++(toIEW->size);
721
722        // Increment which instruction we're on.
723        ++toIEWIndex;
724
725        // Decrement how many instructions are available.
726        --insts_available;
727    }
728
729    instsInProgress[tid] += renamed_insts;
730    renameRenamedInsts += renamed_insts;
731
732    // If we wrote to the time buffer, record this.
733    if (toIEWIndex) {
734        wroteToTimeBuffer = true;
735    }
736
737    // Check if there's any instructions left that haven't yet been renamed.
738    // If so then block.
739    if (insts_available) {
740        blockThisCycle = true;
741    }
742
743    if (blockThisCycle) {
744        block(tid);
745        toDecode->renameUnblock[tid] = false;
746    }
747}
748
749template<class Impl>
750void
751DefaultRename<Impl>::skidInsert(ThreadID tid)
752{
753    DynInstPtr inst = NULL;
754
755    while (!insts[tid].empty()) {
756        inst = insts[tid].front();
757
758        insts[tid].pop_front();
759
760        assert(tid == inst->threadNumber);
761
762        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename "
763                "skidBuffer\n", tid, inst->seqNum, inst->pcState());
764
765        ++renameSkidInsts;
766
767        skidBuffer[tid].push_back(inst);
768    }
769
770    if (skidBuffer[tid].size() > skidBufferMax)
771    {
772        typename InstQueue::iterator it;
773        warn("Skidbuffer contents:\n");
774        for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++)
775        {
776            warn("[tid:%u]: %s [sn:%i].\n", tid,
777                    (*it)->staticInst->disassemble(inst->instAddr()),
778                    (*it)->seqNum);
779        }
780        panic("Skidbuffer Exceeded Max Size");
781    }
782}
783
784template <class Impl>
785void
786DefaultRename<Impl>::sortInsts()
787{
788    int insts_from_decode = fromDecode->size;
789    for (int i = 0; i < insts_from_decode; ++i) {
790        DynInstPtr inst = fromDecode->insts[i];
791        insts[inst->threadNumber].push_back(inst);
792#if TRACING_ON
793        if (DTRACE(O3PipeView)) {
794            inst->renameTick = curTick() - inst->fetchTick;
795        }
796#endif
797    }
798}
799
800template<class Impl>
801bool
802DefaultRename<Impl>::skidsEmpty()
803{
804    list<ThreadID>::iterator threads = activeThreads->begin();
805    list<ThreadID>::iterator end = activeThreads->end();
806
807    while (threads != end) {
808        ThreadID tid = *threads++;
809
810        if (!skidBuffer[tid].empty())
811            return false;
812    }
813
814    return true;
815}
816
817template<class Impl>
818void
819DefaultRename<Impl>::updateStatus()
820{
821    bool any_unblocking = false;
822
823    list<ThreadID>::iterator threads = activeThreads->begin();
824    list<ThreadID>::iterator end = activeThreads->end();
825
826    while (threads != end) {
827        ThreadID tid = *threads++;
828
829        if (renameStatus[tid] == Unblocking) {
830            any_unblocking = true;
831            break;
832        }
833    }
834
835    // Rename will have activity if it's unblocking.
836    if (any_unblocking) {
837        if (_status == Inactive) {
838            _status = Active;
839
840            DPRINTF(Activity, "Activating stage.\n");
841
842            cpu->activateStage(O3CPU::RenameIdx);
843        }
844    } else {
845        // If it's not unblocking, then rename will not have any internal
846        // activity.  Switch it to inactive.
847        if (_status == Active) {
848            _status = Inactive;
849            DPRINTF(Activity, "Deactivating stage.\n");
850
851            cpu->deactivateStage(O3CPU::RenameIdx);
852        }
853    }
854}
855
856template <class Impl>
857bool
858DefaultRename<Impl>::block(ThreadID tid)
859{
860    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
861
862    // Add the current inputs onto the skid buffer, so they can be
863    // reprocessed when this stage unblocks.
864    skidInsert(tid);
865
866    // Only signal backwards to block if the previous stages do not think
867    // rename is already blocked.
868    if (renameStatus[tid] != Blocked) {
869        // If resumeUnblocking is set, we unblocked during the squash,
870        // but now we're have unblocking status. We need to tell earlier
871        // stages to block.
872        if (resumeUnblocking || renameStatus[tid] != Unblocking) {
873            toDecode->renameBlock[tid] = true;
874            toDecode->renameUnblock[tid] = false;
875            wroteToTimeBuffer = true;
876        }
877
878        // Rename can not go from SerializeStall to Blocked, otherwise
879        // it would not know to complete the serialize stall.
880        if (renameStatus[tid] != SerializeStall) {
881            // Set status to Blocked.
882            renameStatus[tid] = Blocked;
883            return true;
884        }
885    }
886
887    return false;
888}
889
890template <class Impl>
891bool
892DefaultRename<Impl>::unblock(ThreadID tid)
893{
894    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
895
896    // Rename is done unblocking if the skid buffer is empty.
897    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
898
899        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
900
901        toDecode->renameUnblock[tid] = true;
902        wroteToTimeBuffer = true;
903
904        renameStatus[tid] = Running;
905        return true;
906    }
907
908    return false;
909}
910
911template <class Impl>
912void
913DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
914{
915    typename std::list<RenameHistory>::iterator hb_it =
916        historyBuffer[tid].begin();
917
918    // After a syscall squashes everything, the history buffer may be empty
919    // but the ROB may still be squashing instructions.
920    if (historyBuffer[tid].empty()) {
921        return;
922    }
923
924    // Go through the most recent instructions, undoing the mappings
925    // they did and freeing up the registers.
926    while (!historyBuffer[tid].empty() &&
927           hb_it->instSeqNum > squashed_seq_num) {
928        assert(hb_it != historyBuffer[tid].end());
929
930        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
931                "number %i.\n", tid, hb_it->instSeqNum);
932
933        // Undo the rename mapping only if it was really a change.
934        // Special regs that are not really renamed (like misc regs
935        // and the zero reg) can be recognized because the new mapping
936        // is the same as the old one.  While it would be merely a
937        // waste of time to update the rename table, we definitely
938        // don't want to put these on the free list.
939        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
940            // Tell the rename map to set the architected register to the
941            // previous physical register that it was renamed to.
942            renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
943
944            // Put the renamed physical register back on the free list.
945            freeList->addReg(hb_it->newPhysReg);
946        }
947
948        // Notify potential listeners that the register mapping needs to be
949        // removed because the instruction it was mapped to got squashed. Note
950        // that this is done before hb_it is incremented.
951        ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum,
952                                                hb_it->newPhysReg));
953
954        historyBuffer[tid].erase(hb_it++);
955
956        ++renameUndoneMaps;
957    }
958}
959
960template<class Impl>
961void
962DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
963{
964    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
965            "history buffer %u (size=%i), until [sn:%lli].\n",
966            tid, tid, historyBuffer[tid].size(), inst_seq_num);
967
968    typename std::list<RenameHistory>::iterator hb_it =
969        historyBuffer[tid].end();
970
971    --hb_it;
972
973    if (historyBuffer[tid].empty()) {
974        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
975        return;
976    } else if (hb_it->instSeqNum > inst_seq_num) {
977        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
978                "that a syscall happened recently.\n", tid);
979        return;
980    }
981
982    // Commit all the renames up until (and including) the committed sequence
983    // number. Some or even all of the committed instructions may not have
984    // rename histories if they did not have destination registers that were
985    // renamed.
986    while (!historyBuffer[tid].empty() &&
987           hb_it != historyBuffer[tid].end() &&
988           hb_it->instSeqNum <= inst_seq_num) {
989
990        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), "
991                "[sn:%lli].\n",
992                tid, hb_it->prevPhysReg->index(),
993                hb_it->prevPhysReg->className(),
994                hb_it->instSeqNum);
995
996        // Don't free special phys regs like misc and zero regs, which
997        // can be recognized because the new mapping is the same as
998        // the old one.
999        if (hb_it->newPhysReg != hb_it->prevPhysReg) {
1000            freeList->addReg(hb_it->prevPhysReg);
1001        }
1002
1003        ++renameCommittedMaps;
1004
1005        historyBuffer[tid].erase(hb_it--);
1006    }
1007}
1008
1009template <class Impl>
1010inline void
1011DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
1012{
1013    ThreadContext *tc = inst->tcBase();
1014    RenameMap *map = renameMap[tid];
1015    unsigned num_src_regs = inst->numSrcRegs();
1016
1017    // Get the architectual register numbers from the source and
1018    // operands, and redirect them to the right physical register.
1019    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
1020        const RegId& src_reg = inst->srcRegIdx(src_idx);
1021        PhysRegIdPtr renamed_reg;
1022
1023        renamed_reg = map->lookup(tc->flattenRegId(src_reg));
1024        switch (src_reg.classValue()) {
1025          case IntRegClass:
1026            intRenameLookups++;
1027            break;
1028          case FloatRegClass:
1029            fpRenameLookups++;
1030            break;
1031          case CCRegClass:
1032          case MiscRegClass:
1033            break;
1034
1035          default:
1036            panic("Invalid register class: %d.", src_reg.classValue());
1037        }
1038
1039        DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i"
1040                ", got phys reg %i (%s)\n", tid,
1041                src_reg.className(), src_reg.index(),
1042                renamed_reg->index(),
1043                renamed_reg->className());
1044
1045        inst->renameSrcReg(src_idx, renamed_reg);
1046
1047        // See if the register is ready or not.
1048        if (scoreboard->getReg(renamed_reg)) {
1049            DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1050                    " is ready.\n", tid, renamed_reg->index(),
1051                    renamed_reg->flatIndex(),
1052                    renamed_reg->className());
1053
1054            inst->markSrcRegReady(src_idx);
1055        } else {
1056            DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)"
1057                    " is not ready.\n", tid, renamed_reg->index(),
1058                    renamed_reg->flatIndex(),
1059                    renamed_reg->className());
1060        }
1061
1062        ++renameRenameLookups;
1063    }
1064}
1065
1066template <class Impl>
1067inline void
1068DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
1069{
1070    ThreadContext *tc = inst->tcBase();
1071    RenameMap *map = renameMap[tid];
1072    unsigned num_dest_regs = inst->numDestRegs();
1073
1074    // Rename the destination registers.
1075    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
1076        const RegId& dest_reg = inst->destRegIdx(dest_idx);
1077        typename RenameMap::RenameInfo rename_result;
1078
1079        RegId flat_dest_regid = tc->flattenRegId(dest_reg);
1080
1081        rename_result = map->rename(flat_dest_regid);
1082
1083        inst->flattenDestReg(dest_idx, flat_dest_regid);
1084
1085        // Mark Scoreboard entry as not ready
1086        scoreboard->unsetReg(rename_result.first);
1087
1088        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical "
1089                "reg %i (%i).\n", tid, dest_reg.index(),
1090                dest_reg.className(),
1091                rename_result.first->index(),
1092                rename_result.first->flatIndex());
1093
1094        // Record the rename information so that a history can be kept.
1095        RenameHistory hb_entry(inst->seqNum, flat_dest_regid,
1096                               rename_result.first,
1097                               rename_result.second);
1098
1099        historyBuffer[tid].push_front(hb_entry);
1100
1101        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer "
1102                "(size=%i), [sn:%lli].\n",tid,
1103                historyBuffer[tid].size(),
1104                (*historyBuffer[tid].begin()).instSeqNum);
1105
1106        // Tell the instruction to rename the appropriate destination
1107        // register (dest_idx) to the new physical register
1108        // (rename_result.first), and record the previous physical
1109        // register that the same logical register was renamed to
1110        // (rename_result.second).
1111        inst->renameDestReg(dest_idx,
1112                            rename_result.first,
1113                            rename_result.second);
1114
1115        ++renameRenamedOperands;
1116    }
1117}
1118
1119template <class Impl>
1120inline int
1121DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
1122{
1123    int num_free = freeEntries[tid].robEntries -
1124                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1125
1126    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1127
1128    return num_free;
1129}
1130
1131template <class Impl>
1132inline int
1133DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
1134{
1135    int num_free = freeEntries[tid].iqEntries -
1136                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1137
1138    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1139
1140    return num_free;
1141}
1142
1143template <class Impl>
1144inline int
1145DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid)
1146{
1147        int num_free = freeEntries[tid].lqEntries -
1148                                  (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ);
1149        DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, "
1150                "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries,
1151                loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ);
1152        return num_free;
1153}
1154
1155template <class Impl>
1156inline int
1157DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid)
1158{
1159        int num_free = freeEntries[tid].sqEntries -
1160                                  (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ);
1161        DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, "
1162                "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries,
1163                storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ);
1164        return num_free;
1165}
1166
1167template <class Impl>
1168unsigned
1169DefaultRename<Impl>::validInsts()
1170{
1171    unsigned inst_count = 0;
1172
1173    for (int i=0; i<fromDecode->size; i++) {
1174        if (!fromDecode->insts[i]->isSquashed())
1175            inst_count++;
1176    }
1177
1178    return inst_count;
1179}
1180
1181template <class Impl>
1182void
1183DefaultRename<Impl>::readStallSignals(ThreadID tid)
1184{
1185    if (fromIEW->iewBlock[tid]) {
1186        stalls[tid].iew = true;
1187    }
1188
1189    if (fromIEW->iewUnblock[tid]) {
1190        assert(stalls[tid].iew);
1191        stalls[tid].iew = false;
1192    }
1193}
1194
1195template <class Impl>
1196bool
1197DefaultRename<Impl>::checkStall(ThreadID tid)
1198{
1199    bool ret_val = false;
1200
1201    if (stalls[tid].iew) {
1202        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1203        ret_val = true;
1204    } else if (calcFreeROBEntries(tid) <= 0) {
1205        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1206        ret_val = true;
1207    } else if (calcFreeIQEntries(tid) <= 0) {
1208        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1209        ret_val = true;
1210    } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) {
1211        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1212        ret_val = true;
1213    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1214        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1215        ret_val = true;
1216    } else if (renameStatus[tid] == SerializeStall &&
1217               (!emptyROB[tid] || instsInProgress[tid])) {
1218        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1219                "empty.\n",
1220                tid);
1221        ret_val = true;
1222    }
1223
1224    return ret_val;
1225}
1226
1227template <class Impl>
1228void
1229DefaultRename<Impl>::readFreeEntries(ThreadID tid)
1230{
1231    if (fromIEW->iewInfo[tid].usedIQ)
1232        freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
1233
1234    if (fromIEW->iewInfo[tid].usedLSQ) {
1235        freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries;
1236        freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries;
1237    }
1238
1239    if (fromCommit->commitInfo[tid].usedROB) {
1240        freeEntries[tid].robEntries =
1241            fromCommit->commitInfo[tid].freeROBEntries;
1242        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1243    }
1244
1245    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, "
1246                    "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n",
1247            tid,
1248            freeEntries[tid].iqEntries,
1249            freeEntries[tid].robEntries,
1250            freeEntries[tid].lqEntries,
1251            freeEntries[tid].sqEntries,
1252            renameMap[tid]->numFreeEntries(),
1253            renameMap[tid]->numFreeIntEntries(),
1254            renameMap[tid]->numFreeFloatEntries(),
1255            renameMap[tid]->numFreeVecEntries(),
1256            renameMap[tid]->numFreeCCEntries());
1257
1258    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1259            tid, instsInProgress[tid]);
1260}
1261
1262template <class Impl>
1263bool
1264DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
1265{
1266    // Check if there's a squash signal, squash if there is
1267    // Check stall signals, block if necessary.
1268    // If status was blocked
1269    //     check if stall conditions have passed
1270    //         if so then go to unblocking
1271    // If status was Squashing
1272    //     check if squashing is not high.  Switch to running this cycle.
1273    // If status was serialize stall
1274    //     check if ROB is empty and no insts are in flight to the ROB
1275
1276    readFreeEntries(tid);
1277    readStallSignals(tid);
1278
1279    if (fromCommit->commitInfo[tid].squash) {
1280        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1281                "commit.\n", tid);
1282
1283        squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
1284
1285        return true;
1286    }
1287
1288    if (checkStall(tid)) {
1289        return block(tid);
1290    }
1291
1292    if (renameStatus[tid] == Blocked) {
1293        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1294                tid);
1295
1296        renameStatus[tid] = Unblocking;
1297
1298        unblock(tid);
1299
1300        return true;
1301    }
1302
1303    if (renameStatus[tid] == Squashing) {
1304        // Switch status to running if rename isn't being told to block or
1305        // squash this cycle.
1306        if (resumeSerialize) {
1307            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n",
1308                    tid);
1309
1310            renameStatus[tid] = SerializeStall;
1311            return true;
1312        } else if (resumeUnblocking) {
1313            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n",
1314                    tid);
1315            renameStatus[tid] = Unblocking;
1316            return true;
1317        } else {
1318            DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1319                    tid);
1320
1321            renameStatus[tid] = Running;
1322            return false;
1323        }
1324    }
1325
1326    if (renameStatus[tid] == SerializeStall) {
1327        // Stall ends once the ROB is free.
1328        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1329                "unblocking.\n", tid);
1330
1331        DynInstPtr serial_inst = serializeInst[tid];
1332
1333        renameStatus[tid] = Unblocking;
1334
1335        unblock(tid);
1336
1337        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1338                "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState());
1339
1340        // Put instruction into queue here.
1341        serial_inst->clearSerializeBefore();
1342
1343        if (!skidBuffer[tid].empty()) {
1344            skidBuffer[tid].push_front(serial_inst);
1345        } else {
1346            insts[tid].push_front(serial_inst);
1347        }
1348
1349        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1350                " Adding to front of list.\n", tid);
1351
1352        serializeInst[tid] = NULL;
1353
1354        return true;
1355    }
1356
1357    // If we've reached this point, we have not gotten any signals that
1358    // cause rename to change its status.  Rename remains the same as before.
1359    return false;
1360}
1361
1362template<class Impl>
1363void
1364DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
1365{
1366    if (inst_list.empty()) {
1367        // Mark a bit to say that I must serialize on the next instruction.
1368        serializeOnNextInst[tid] = true;
1369        return;
1370    }
1371
1372    // Set the next instruction as serializing.
1373    inst_list.front()->setSerializeBefore();
1374}
1375
1376template <class Impl>
1377inline void
1378DefaultRename<Impl>::incrFullStat(const FullSource &source)
1379{
1380    switch (source) {
1381      case ROB:
1382        ++renameROBFullEvents;
1383        break;
1384      case IQ:
1385        ++renameIQFullEvents;
1386        break;
1387      case LQ:
1388        ++renameLQFullEvents;
1389        break;
1390      case SQ:
1391        ++renameSQFullEvents;
1392        break;
1393      default:
1394        panic("Rename full stall stat should be incremented for a reason!");
1395        break;
1396    }
1397}
1398
1399template <class Impl>
1400void
1401DefaultRename<Impl>::dumpHistory()
1402{
1403    typename std::list<RenameHistory>::iterator buf_it;
1404
1405    for (ThreadID tid = 0; tid < numThreads; tid++) {
1406
1407        buf_it = historyBuffer[tid].begin();
1408
1409        while (buf_it != historyBuffer[tid].end()) {
1410            cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:"
1411                    " %i[%s] Old phys reg: %i[%s]\n",
1412                    (*buf_it).instSeqNum,
1413                    (*buf_it).archReg.className(),
1414                    (*buf_it).archReg.index(),
1415                    (*buf_it).newPhysReg->index(),
1416                    (*buf_it).newPhysReg->className(),
1417                    (*buf_it).prevPhysReg->index(),
1418                    (*buf_it).prevPhysReg->className());
1419
1420            buf_it++;
1421        }
1422    }
1423}
1424
1425#endif//__CPU_O3_RENAME_IMPL_HH__
1426