rename_impl.hh revision 10328
1/* 2 * Copyright (c) 2010-2012, 2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2004-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 * Korey Sewell 43 */ 44 45#ifndef __CPU_O3_RENAME_IMPL_HH__ 46#define __CPU_O3_RENAME_IMPL_HH__ 47 48#include <list> 49 50#include "arch/isa_traits.hh" 51#include "arch/registers.hh" 52#include "config/the_isa.hh" 53#include "cpu/o3/rename.hh" 54#include "cpu/reg_class.hh" 55#include "debug/Activity.hh" 56#include "debug/Rename.hh" 57#include "debug/O3PipeView.hh" 58#include "params/DerivO3CPU.hh" 59 60using namespace std; 61 62template <class Impl> 63DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 64 : cpu(_cpu), 65 iewToRenameDelay(params->iewToRenameDelay), 66 decodeToRenameDelay(params->decodeToRenameDelay), 67 commitToRenameDelay(params->commitToRenameDelay), 68 renameWidth(params->renameWidth), 69 commitWidth(params->commitWidth), 70 numThreads(params->numThreads), 71 maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 72 + params->numPhysCCRegs) 73{ 74 if (renameWidth > Impl::MaxWidth) 75 fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 76 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 77 renameWidth, static_cast<int>(Impl::MaxWidth)); 78 79 // @todo: Make into a parameter. 80 skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 81} 82 83template <class Impl> 84std::string 85DefaultRename<Impl>::name() const 86{ 87 return cpu->name() + ".rename"; 88} 89 90template <class Impl> 91void 92DefaultRename<Impl>::regStats() 93{ 94 renameSquashCycles 95 .name(name() + ".SquashCycles") 96 .desc("Number of cycles rename is squashing") 97 .prereq(renameSquashCycles); 98 renameIdleCycles 99 .name(name() + ".IdleCycles") 100 .desc("Number of cycles rename is idle") 101 .prereq(renameIdleCycles); 102 renameBlockCycles 103 .name(name() + ".BlockCycles") 104 .desc("Number of cycles rename is blocking") 105 .prereq(renameBlockCycles); 106 renameSerializeStallCycles 107 .name(name() + ".serializeStallCycles") 108 .desc("count of cycles rename stalled for serializing inst") 109 .flags(Stats::total); 110 renameRunCycles 111 .name(name() + ".RunCycles") 112 .desc("Number of cycles rename is running") 113 .prereq(renameIdleCycles); 114 renameUnblockCycles 115 .name(name() + ".UnblockCycles") 116 .desc("Number of cycles rename is unblocking") 117 .prereq(renameUnblockCycles); 118 renameRenamedInsts 119 .name(name() + ".RenamedInsts") 120 .desc("Number of instructions processed by rename") 121 .prereq(renameRenamedInsts); 122 renameSquashedInsts 123 .name(name() + ".SquashedInsts") 124 .desc("Number of squashed instructions processed by rename") 125 .prereq(renameSquashedInsts); 126 renameROBFullEvents 127 .name(name() + ".ROBFullEvents") 128 .desc("Number of times rename has blocked due to ROB full") 129 .prereq(renameROBFullEvents); 130 renameIQFullEvents 131 .name(name() + ".IQFullEvents") 132 .desc("Number of times rename has blocked due to IQ full") 133 .prereq(renameIQFullEvents); 134 renameLQFullEvents 135 .name(name() + ".LQFullEvents") 136 .desc("Number of times rename has blocked due to LQ full") 137 .prereq(renameLQFullEvents); 138 renameSQFullEvents 139 .name(name() + ".SQFullEvents") 140 .desc("Number of times rename has blocked due to SQ full") 141 .prereq(renameSQFullEvents); 142 renameFullRegistersEvents 143 .name(name() + ".FullRegisterEvents") 144 .desc("Number of times there has been no free registers") 145 .prereq(renameFullRegistersEvents); 146 renameRenamedOperands 147 .name(name() + ".RenamedOperands") 148 .desc("Number of destination operands rename has renamed") 149 .prereq(renameRenamedOperands); 150 renameRenameLookups 151 .name(name() + ".RenameLookups") 152 .desc("Number of register rename lookups that rename has made") 153 .prereq(renameRenameLookups); 154 renameCommittedMaps 155 .name(name() + ".CommittedMaps") 156 .desc("Number of HB maps that are committed") 157 .prereq(renameCommittedMaps); 158 renameUndoneMaps 159 .name(name() + ".UndoneMaps") 160 .desc("Number of HB maps that are undone due to squashing") 161 .prereq(renameUndoneMaps); 162 renamedSerializing 163 .name(name() + ".serializingInsts") 164 .desc("count of serializing insts renamed") 165 .flags(Stats::total) 166 ; 167 renamedTempSerializing 168 .name(name() + ".tempSerializingInsts") 169 .desc("count of temporary serializing insts renamed") 170 .flags(Stats::total) 171 ; 172 renameSkidInsts 173 .name(name() + ".skidInsts") 174 .desc("count of insts added to the skid buffer") 175 .flags(Stats::total) 176 ; 177 intRenameLookups 178 .name(name() + ".int_rename_lookups") 179 .desc("Number of integer rename lookups") 180 .prereq(intRenameLookups); 181 fpRenameLookups 182 .name(name() + ".fp_rename_lookups") 183 .desc("Number of floating rename lookups") 184 .prereq(fpRenameLookups); 185} 186 187template <class Impl> 188void 189DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 190{ 191 timeBuffer = tb_ptr; 192 193 // Setup wire to read information from time buffer, from IEW stage. 194 fromIEW = timeBuffer->getWire(-iewToRenameDelay); 195 196 // Setup wire to read infromation from time buffer, from commit stage. 197 fromCommit = timeBuffer->getWire(-commitToRenameDelay); 198 199 // Setup wire to write information to previous stages. 200 toDecode = timeBuffer->getWire(0); 201} 202 203template <class Impl> 204void 205DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 206{ 207 renameQueue = rq_ptr; 208 209 // Setup wire to write information to future stages. 210 toIEW = renameQueue->getWire(0); 211} 212 213template <class Impl> 214void 215DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 216{ 217 decodeQueue = dq_ptr; 218 219 // Setup wire to get information from decode. 220 fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 221} 222 223template <class Impl> 224void 225DefaultRename<Impl>::startupStage() 226{ 227 resetStage(); 228} 229 230template <class Impl> 231void 232DefaultRename<Impl>::resetStage() 233{ 234 _status = Inactive; 235 236 resumeSerialize = false; 237 resumeUnblocking = false; 238 239 // Grab the number of free entries directly from the stages. 240 for (ThreadID tid = 0; tid < numThreads; tid++) { 241 renameStatus[tid] = Idle; 242 243 freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 244 freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 245 freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 246 freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 247 emptyROB[tid] = true; 248 249 stalls[tid].iew = false; 250 serializeInst[tid] = NULL; 251 252 instsInProgress[tid] = 0; 253 loadsInProgress[tid] = 0; 254 storesInProgress[tid] = 0; 255 256 serializeOnNextInst[tid] = false; 257 } 258} 259 260template<class Impl> 261void 262DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 263{ 264 activeThreads = at_ptr; 265} 266 267 268template <class Impl> 269void 270DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 271{ 272 for (ThreadID tid = 0; tid < numThreads; tid++) 273 renameMap[tid] = &rm_ptr[tid]; 274} 275 276template <class Impl> 277void 278DefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 279{ 280 freeList = fl_ptr; 281} 282 283template<class Impl> 284void 285DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 286{ 287 scoreboard = _scoreboard; 288} 289 290template <class Impl> 291bool 292DefaultRename<Impl>::isDrained() const 293{ 294 for (ThreadID tid = 0; tid < numThreads; tid++) { 295 if (instsInProgress[tid] != 0 || 296 !historyBuffer[tid].empty() || 297 !skidBuffer[tid].empty() || 298 !insts[tid].empty()) 299 return false; 300 } 301 return true; 302} 303 304template <class Impl> 305void 306DefaultRename<Impl>::takeOverFrom() 307{ 308 resetStage(); 309} 310 311template <class Impl> 312void 313DefaultRename<Impl>::drainSanityCheck() const 314{ 315 for (ThreadID tid = 0; tid < numThreads; tid++) { 316 assert(historyBuffer[tid].empty()); 317 assert(insts[tid].empty()); 318 assert(skidBuffer[tid].empty()); 319 assert(instsInProgress[tid] == 0); 320 } 321} 322 323template <class Impl> 324void 325DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 326{ 327 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 328 329 // Clear the stall signal if rename was blocked or unblocking before. 330 // If it still needs to block, the blocking should happen the next 331 // cycle and there should be space to hold everything due to the squash. 332 if (renameStatus[tid] == Blocked || 333 renameStatus[tid] == Unblocking) { 334 toDecode->renameUnblock[tid] = 1; 335 336 resumeSerialize = false; 337 serializeInst[tid] = NULL; 338 } else if (renameStatus[tid] == SerializeStall) { 339 if (serializeInst[tid]->seqNum <= squash_seq_num) { 340 DPRINTF(Rename, "Rename will resume serializing after squash\n"); 341 resumeSerialize = true; 342 assert(serializeInst[tid]); 343 } else { 344 resumeSerialize = false; 345 toDecode->renameUnblock[tid] = 1; 346 347 serializeInst[tid] = NULL; 348 } 349 } 350 351 // Set the status to Squashing. 352 renameStatus[tid] = Squashing; 353 354 // Squash any instructions from decode. 355 for (int i=0; i<fromDecode->size; i++) { 356 if (fromDecode->insts[i]->threadNumber == tid && 357 fromDecode->insts[i]->seqNum > squash_seq_num) { 358 fromDecode->insts[i]->setSquashed(); 359 wroteToTimeBuffer = true; 360 } 361 362 } 363 364 // Clear the instruction list and skid buffer in case they have any 365 // insts in them. 366 insts[tid].clear(); 367 368 // Clear the skid buffer in case it has any data in it. 369 skidBuffer[tid].clear(); 370 371 doSquash(squash_seq_num, tid); 372} 373 374template <class Impl> 375void 376DefaultRename<Impl>::tick() 377{ 378 wroteToTimeBuffer = false; 379 380 blockThisCycle = false; 381 382 bool status_change = false; 383 384 toIEWIndex = 0; 385 386 sortInsts(); 387 388 list<ThreadID>::iterator threads = activeThreads->begin(); 389 list<ThreadID>::iterator end = activeThreads->end(); 390 391 // Check stall and squash signals. 392 while (threads != end) { 393 ThreadID tid = *threads++; 394 395 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 396 397 status_change = checkSignalsAndUpdate(tid) || status_change; 398 399 rename(status_change, tid); 400 } 401 402 if (status_change) { 403 updateStatus(); 404 } 405 406 if (wroteToTimeBuffer) { 407 DPRINTF(Activity, "Activity this cycle.\n"); 408 cpu->activityThisCycle(); 409 } 410 411 threads = activeThreads->begin(); 412 413 while (threads != end) { 414 ThreadID tid = *threads++; 415 416 // If we committed this cycle then doneSeqNum will be > 0 417 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 418 !fromCommit->commitInfo[tid].squash && 419 renameStatus[tid] != Squashing) { 420 421 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 422 tid); 423 } 424 } 425 426 // @todo: make into updateProgress function 427 for (ThreadID tid = 0; tid < numThreads; tid++) { 428 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 429 loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 430 storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 431 assert(loadsInProgress[tid] >= 0); 432 assert(storesInProgress[tid] >= 0); 433 assert(instsInProgress[tid] >=0); 434 } 435 436} 437 438template<class Impl> 439void 440DefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 441{ 442 // If status is Running or idle, 443 // call renameInsts() 444 // If status is Unblocking, 445 // buffer any instructions coming from decode 446 // continue trying to empty skid buffer 447 // check if stall conditions have passed 448 449 if (renameStatus[tid] == Blocked) { 450 ++renameBlockCycles; 451 } else if (renameStatus[tid] == Squashing) { 452 ++renameSquashCycles; 453 } else if (renameStatus[tid] == SerializeStall) { 454 ++renameSerializeStallCycles; 455 // If we are currently in SerializeStall and resumeSerialize 456 // was set, then that means that we are resuming serializing 457 // this cycle. Tell the previous stages to block. 458 if (resumeSerialize) { 459 resumeSerialize = false; 460 block(tid); 461 toDecode->renameUnblock[tid] = false; 462 } 463 } else if (renameStatus[tid] == Unblocking) { 464 if (resumeUnblocking) { 465 block(tid); 466 resumeUnblocking = false; 467 toDecode->renameUnblock[tid] = false; 468 } 469 } 470 471 if (renameStatus[tid] == Running || 472 renameStatus[tid] == Idle) { 473 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 474 "stage.\n", tid); 475 476 renameInsts(tid); 477 } else if (renameStatus[tid] == Unblocking) { 478 renameInsts(tid); 479 480 if (validInsts()) { 481 // Add the current inputs to the skid buffer so they can be 482 // reprocessed when this stage unblocks. 483 skidInsert(tid); 484 } 485 486 // If we switched over to blocking, then there's a potential for 487 // an overall status change. 488 status_change = unblock(tid) || status_change || blockThisCycle; 489 } 490} 491 492template <class Impl> 493void 494DefaultRename<Impl>::renameInsts(ThreadID tid) 495{ 496 // Instructions can be either in the skid buffer or the queue of 497 // instructions coming from decode, depending on the status. 498 int insts_available = renameStatus[tid] == Unblocking ? 499 skidBuffer[tid].size() : insts[tid].size(); 500 501 // Check the decode queue to see if instructions are available. 502 // If there are no available instructions to rename, then do nothing. 503 if (insts_available == 0) { 504 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 505 tid); 506 // Should I change status to idle? 507 ++renameIdleCycles; 508 return; 509 } else if (renameStatus[tid] == Unblocking) { 510 ++renameUnblockCycles; 511 } else if (renameStatus[tid] == Running) { 512 ++renameRunCycles; 513 } 514 515 DynInstPtr inst; 516 517 // Will have to do a different calculation for the number of free 518 // entries. 519 int free_rob_entries = calcFreeROBEntries(tid); 520 int free_iq_entries = calcFreeIQEntries(tid); 521 int min_free_entries = free_rob_entries; 522 523 FullSource source = ROB; 524 525 if (free_iq_entries < min_free_entries) { 526 min_free_entries = free_iq_entries; 527 source = IQ; 528 } 529 530 // Check if there's any space left. 531 if (min_free_entries <= 0) { 532 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 533 "entries.\n" 534 "ROB has %i free entries.\n" 535 "IQ has %i free entries.\n", 536 tid, 537 free_rob_entries, 538 free_iq_entries); 539 540 blockThisCycle = true; 541 542 block(tid); 543 544 incrFullStat(source); 545 546 return; 547 } else if (min_free_entries < insts_available) { 548 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 549 "%i insts available, but only %i insts can be " 550 "renamed due to ROB/IQ/LSQ limits.\n", 551 tid, insts_available, min_free_entries); 552 553 insts_available = min_free_entries; 554 555 blockThisCycle = true; 556 557 incrFullStat(source); 558 } 559 560 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 561 skidBuffer[tid] : insts[tid]; 562 563 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 564 "send iew.\n", tid, insts_available); 565 566 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 567 "dispatched to IQ last cycle.\n", 568 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 569 570 // Handle serializing the next instruction if necessary. 571 if (serializeOnNextInst[tid]) { 572 if (emptyROB[tid] && instsInProgress[tid] == 0) { 573 // ROB already empty; no need to serialize. 574 serializeOnNextInst[tid] = false; 575 } else if (!insts_to_rename.empty()) { 576 insts_to_rename.front()->setSerializeBefore(); 577 } 578 } 579 580 int renamed_insts = 0; 581 582 while (insts_available > 0 && toIEWIndex < renameWidth) { 583 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 584 585 assert(!insts_to_rename.empty()); 586 587 inst = insts_to_rename.front(); 588 589 //For all kind of instructions, check ROB and IQ first 590 //For load instruction, check LQ size and take into account the inflight loads 591 //For store instruction, check SQ size and take into account the inflight stores 592 593 if (inst->isLoad()) { 594 if(calcFreeLQEntries(tid) <= 0) { 595 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 596 source = LQ; 597 incrFullStat(source); 598 break; 599 } 600 } 601 602 if (inst->isStore()) { 603 if(calcFreeSQEntries(tid) <= 0) { 604 DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 605 source = SQ; 606 incrFullStat(source); 607 break; 608 } 609 } 610 611 insts_to_rename.pop_front(); 612 613 if (renameStatus[tid] == Unblocking) { 614 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 615 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 616 } 617 618 if (inst->isSquashed()) { 619 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 620 "squashed, skipping.\n", tid, inst->seqNum, 621 inst->pcState()); 622 623 ++renameSquashedInsts; 624 625 // Decrement how many instructions are available. 626 --insts_available; 627 628 continue; 629 } 630 631 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 632 "PC %s.\n", tid, inst->seqNum, inst->pcState()); 633 634 // Check here to make sure there are enough destination registers 635 // to rename to. Otherwise block. 636 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 637 DPRINTF(Rename, "Blocking due to lack of free " 638 "physical registers to rename to.\n"); 639 blockThisCycle = true; 640 insts_to_rename.push_front(inst); 641 ++renameFullRegistersEvents; 642 643 break; 644 } 645 646 // Handle serializeAfter/serializeBefore instructions. 647 // serializeAfter marks the next instruction as serializeBefore. 648 // serializeBefore makes the instruction wait in rename until the ROB 649 // is empty. 650 651 // In this model, IPR accesses are serialize before 652 // instructions, and store conditionals are serialize after 653 // instructions. This is mainly due to lack of support for 654 // out-of-order operations of either of those classes of 655 // instructions. 656 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 657 !inst->isSerializeHandled()) { 658 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 659 660 if (!inst->isTempSerializeBefore()) { 661 renamedSerializing++; 662 inst->setSerializeHandled(); 663 } else { 664 renamedTempSerializing++; 665 } 666 667 // Change status over to SerializeStall so that other stages know 668 // what this is blocked on. 669 renameStatus[tid] = SerializeStall; 670 671 serializeInst[tid] = inst; 672 673 blockThisCycle = true; 674 675 break; 676 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 677 !inst->isSerializeHandled()) { 678 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 679 680 renamedSerializing++; 681 682 inst->setSerializeHandled(); 683 684 serializeAfter(insts_to_rename, tid); 685 } 686 687 renameSrcRegs(inst, inst->threadNumber); 688 689 renameDestRegs(inst, inst->threadNumber); 690 691 if (inst->isLoad()) { 692 loadsInProgress[tid]++; 693 } 694 if (inst->isStore()) { 695 storesInProgress[tid]++; 696 } 697 ++renamed_insts; 698 699 700 // Put instruction in rename queue. 701 toIEW->insts[toIEWIndex] = inst; 702 ++(toIEW->size); 703 704 // Increment which instruction we're on. 705 ++toIEWIndex; 706 707 // Decrement how many instructions are available. 708 --insts_available; 709 } 710 711 instsInProgress[tid] += renamed_insts; 712 renameRenamedInsts += renamed_insts; 713 714 // If we wrote to the time buffer, record this. 715 if (toIEWIndex) { 716 wroteToTimeBuffer = true; 717 } 718 719 // Check if there's any instructions left that haven't yet been renamed. 720 // If so then block. 721 if (insts_available) { 722 blockThisCycle = true; 723 } 724 725 if (blockThisCycle) { 726 block(tid); 727 toDecode->renameUnblock[tid] = false; 728 } 729} 730 731template<class Impl> 732void 733DefaultRename<Impl>::skidInsert(ThreadID tid) 734{ 735 DynInstPtr inst = NULL; 736 737 while (!insts[tid].empty()) { 738 inst = insts[tid].front(); 739 740 insts[tid].pop_front(); 741 742 assert(tid == inst->threadNumber); 743 744 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 745 "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 746 747 ++renameSkidInsts; 748 749 skidBuffer[tid].push_back(inst); 750 } 751 752 if (skidBuffer[tid].size() > skidBufferMax) 753 { 754 typename InstQueue::iterator it; 755 warn("Skidbuffer contents:\n"); 756 for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 757 { 758 warn("[tid:%u]: %s [sn:%i].\n", tid, 759 (*it)->staticInst->disassemble(inst->instAddr()), 760 (*it)->seqNum); 761 } 762 panic("Skidbuffer Exceeded Max Size"); 763 } 764} 765 766template <class Impl> 767void 768DefaultRename<Impl>::sortInsts() 769{ 770 int insts_from_decode = fromDecode->size; 771 for (int i = 0; i < insts_from_decode; ++i) { 772 DynInstPtr inst = fromDecode->insts[i]; 773 insts[inst->threadNumber].push_back(inst); 774#if TRACING_ON 775 if (DTRACE(O3PipeView)) { 776 inst->renameTick = curTick() - inst->fetchTick; 777 } 778#endif 779 } 780} 781 782template<class Impl> 783bool 784DefaultRename<Impl>::skidsEmpty() 785{ 786 list<ThreadID>::iterator threads = activeThreads->begin(); 787 list<ThreadID>::iterator end = activeThreads->end(); 788 789 while (threads != end) { 790 ThreadID tid = *threads++; 791 792 if (!skidBuffer[tid].empty()) 793 return false; 794 } 795 796 return true; 797} 798 799template<class Impl> 800void 801DefaultRename<Impl>::updateStatus() 802{ 803 bool any_unblocking = false; 804 805 list<ThreadID>::iterator threads = activeThreads->begin(); 806 list<ThreadID>::iterator end = activeThreads->end(); 807 808 while (threads != end) { 809 ThreadID tid = *threads++; 810 811 if (renameStatus[tid] == Unblocking) { 812 any_unblocking = true; 813 break; 814 } 815 } 816 817 // Rename will have activity if it's unblocking. 818 if (any_unblocking) { 819 if (_status == Inactive) { 820 _status = Active; 821 822 DPRINTF(Activity, "Activating stage.\n"); 823 824 cpu->activateStage(O3CPU::RenameIdx); 825 } 826 } else { 827 // If it's not unblocking, then rename will not have any internal 828 // activity. Switch it to inactive. 829 if (_status == Active) { 830 _status = Inactive; 831 DPRINTF(Activity, "Deactivating stage.\n"); 832 833 cpu->deactivateStage(O3CPU::RenameIdx); 834 } 835 } 836} 837 838template <class Impl> 839bool 840DefaultRename<Impl>::block(ThreadID tid) 841{ 842 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 843 844 // Add the current inputs onto the skid buffer, so they can be 845 // reprocessed when this stage unblocks. 846 skidInsert(tid); 847 848 // Only signal backwards to block if the previous stages do not think 849 // rename is already blocked. 850 if (renameStatus[tid] != Blocked) { 851 // If resumeUnblocking is set, we unblocked during the squash, 852 // but now we're have unblocking status. We need to tell earlier 853 // stages to block. 854 if (resumeUnblocking || renameStatus[tid] != Unblocking) { 855 toDecode->renameBlock[tid] = true; 856 toDecode->renameUnblock[tid] = false; 857 wroteToTimeBuffer = true; 858 } 859 860 // Rename can not go from SerializeStall to Blocked, otherwise 861 // it would not know to complete the serialize stall. 862 if (renameStatus[tid] != SerializeStall) { 863 // Set status to Blocked. 864 renameStatus[tid] = Blocked; 865 return true; 866 } 867 } 868 869 return false; 870} 871 872template <class Impl> 873bool 874DefaultRename<Impl>::unblock(ThreadID tid) 875{ 876 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 877 878 // Rename is done unblocking if the skid buffer is empty. 879 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 880 881 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 882 883 toDecode->renameUnblock[tid] = true; 884 wroteToTimeBuffer = true; 885 886 renameStatus[tid] = Running; 887 return true; 888 } 889 890 return false; 891} 892 893template <class Impl> 894void 895DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 896{ 897 typename std::list<RenameHistory>::iterator hb_it = 898 historyBuffer[tid].begin(); 899 900 // After a syscall squashes everything, the history buffer may be empty 901 // but the ROB may still be squashing instructions. 902 if (historyBuffer[tid].empty()) { 903 return; 904 } 905 906 // Go through the most recent instructions, undoing the mappings 907 // they did and freeing up the registers. 908 while (!historyBuffer[tid].empty() && 909 hb_it->instSeqNum > squashed_seq_num) { 910 assert(hb_it != historyBuffer[tid].end()); 911 912 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 913 "number %i.\n", tid, hb_it->instSeqNum); 914 915 // Undo the rename mapping only if it was really a change. 916 // Special regs that are not really renamed (like misc regs 917 // and the zero reg) can be recognized because the new mapping 918 // is the same as the old one. While it would be merely a 919 // waste of time to update the rename table, we definitely 920 // don't want to put these on the free list. 921 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 922 // Tell the rename map to set the architected register to the 923 // previous physical register that it was renamed to. 924 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 925 926 // Put the renamed physical register back on the free list. 927 freeList->addReg(hb_it->newPhysReg); 928 } 929 930 historyBuffer[tid].erase(hb_it++); 931 932 ++renameUndoneMaps; 933 } 934} 935 936template<class Impl> 937void 938DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 939{ 940 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 941 "history buffer %u (size=%i), until [sn:%lli].\n", 942 tid, tid, historyBuffer[tid].size(), inst_seq_num); 943 944 typename std::list<RenameHistory>::iterator hb_it = 945 historyBuffer[tid].end(); 946 947 --hb_it; 948 949 if (historyBuffer[tid].empty()) { 950 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 951 return; 952 } else if (hb_it->instSeqNum > inst_seq_num) { 953 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 954 "that a syscall happened recently.\n", tid); 955 return; 956 } 957 958 // Commit all the renames up until (and including) the committed sequence 959 // number. Some or even all of the committed instructions may not have 960 // rename histories if they did not have destination registers that were 961 // renamed. 962 while (!historyBuffer[tid].empty() && 963 hb_it != historyBuffer[tid].end() && 964 hb_it->instSeqNum <= inst_seq_num) { 965 966 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 967 "[sn:%lli].\n", 968 tid, hb_it->prevPhysReg, hb_it->instSeqNum); 969 970 // Don't free special phys regs like misc and zero regs, which 971 // can be recognized because the new mapping is the same as 972 // the old one. 973 if (hb_it->newPhysReg != hb_it->prevPhysReg) { 974 freeList->addReg(hb_it->prevPhysReg); 975 } 976 977 ++renameCommittedMaps; 978 979 historyBuffer[tid].erase(hb_it--); 980 } 981} 982 983template <class Impl> 984inline void 985DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 986{ 987 ThreadContext *tc = inst->tcBase(); 988 RenameMap *map = renameMap[tid]; 989 unsigned num_src_regs = inst->numSrcRegs(); 990 991 // Get the architectual register numbers from the source and 992 // operands, and redirect them to the right physical register. 993 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 994 RegIndex src_reg = inst->srcRegIdx(src_idx); 995 RegIndex rel_src_reg; 996 RegIndex flat_rel_src_reg; 997 PhysRegIndex renamed_reg; 998 999 switch (regIdxToClass(src_reg, &rel_src_reg)) { 1000 case IntRegClass: 1001 flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 1002 renamed_reg = map->lookupInt(flat_rel_src_reg); 1003 intRenameLookups++; 1004 break; 1005 1006 case FloatRegClass: 1007 flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 1008 renamed_reg = map->lookupFloat(flat_rel_src_reg); 1009 fpRenameLookups++; 1010 break; 1011 1012 case CCRegClass: 1013 flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 1014 renamed_reg = map->lookupCC(flat_rel_src_reg); 1015 break; 1016 1017 case MiscRegClass: 1018 // misc regs don't get flattened 1019 flat_rel_src_reg = rel_src_reg; 1020 renamed_reg = map->lookupMisc(flat_rel_src_reg); 1021 break; 1022 1023 default: 1024 panic("Reg index is out of bound: %d.", src_reg); 1025 } 1026 1027 DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 1028 "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 1029 (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 1030 1031 inst->renameSrcReg(src_idx, renamed_reg); 1032 1033 // See if the register is ready or not. 1034 if (scoreboard->getReg(renamed_reg)) { 1035 DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 1036 tid, renamed_reg); 1037 1038 inst->markSrcRegReady(src_idx); 1039 } else { 1040 DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 1041 tid, renamed_reg); 1042 } 1043 1044 ++renameRenameLookups; 1045 } 1046} 1047 1048template <class Impl> 1049inline void 1050DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 1051{ 1052 ThreadContext *tc = inst->tcBase(); 1053 RenameMap *map = renameMap[tid]; 1054 unsigned num_dest_regs = inst->numDestRegs(); 1055 1056 // Rename the destination registers. 1057 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 1058 RegIndex dest_reg = inst->destRegIdx(dest_idx); 1059 RegIndex rel_dest_reg; 1060 RegIndex flat_rel_dest_reg; 1061 RegIndex flat_uni_dest_reg; 1062 typename RenameMap::RenameInfo rename_result; 1063 1064 switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 1065 case IntRegClass: 1066 flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 1067 rename_result = map->renameInt(flat_rel_dest_reg); 1068 flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 1069 break; 1070 1071 case FloatRegClass: 1072 flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 1073 rename_result = map->renameFloat(flat_rel_dest_reg); 1074 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 1075 break; 1076 1077 case CCRegClass: 1078 flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 1079 rename_result = map->renameCC(flat_rel_dest_reg); 1080 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 1081 break; 1082 1083 case MiscRegClass: 1084 // misc regs don't get flattened 1085 flat_rel_dest_reg = rel_dest_reg; 1086 rename_result = map->renameMisc(flat_rel_dest_reg); 1087 flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 1088 break; 1089 1090 default: 1091 panic("Reg index is out of bound: %d.", dest_reg); 1092 } 1093 1094 inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 1095 1096 // Mark Scoreboard entry as not ready 1097 scoreboard->unsetReg(rename_result.first); 1098 1099 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 1100 "reg %i.\n", tid, (int)flat_rel_dest_reg, 1101 (int)rename_result.first); 1102 1103 // Record the rename information so that a history can be kept. 1104 RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 1105 rename_result.first, 1106 rename_result.second); 1107 1108 historyBuffer[tid].push_front(hb_entry); 1109 1110 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 1111 "(size=%i), [sn:%lli].\n",tid, 1112 historyBuffer[tid].size(), 1113 (*historyBuffer[tid].begin()).instSeqNum); 1114 1115 // Tell the instruction to rename the appropriate destination 1116 // register (dest_idx) to the new physical register 1117 // (rename_result.first), and record the previous physical 1118 // register that the same logical register was renamed to 1119 // (rename_result.second). 1120 inst->renameDestReg(dest_idx, 1121 rename_result.first, 1122 rename_result.second); 1123 1124 ++renameRenamedOperands; 1125 } 1126} 1127 1128template <class Impl> 1129inline int 1130DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 1131{ 1132 int num_free = freeEntries[tid].robEntries - 1133 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1134 1135 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 1136 1137 return num_free; 1138} 1139 1140template <class Impl> 1141inline int 1142DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 1143{ 1144 int num_free = freeEntries[tid].iqEntries - 1145 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1146 1147 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1148 1149 return num_free; 1150} 1151 1152template <class Impl> 1153inline int 1154DefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 1155{ 1156 int num_free = freeEntries[tid].lqEntries - 1157 (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 1158 DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 1159 "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 1160 loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 1161 return num_free; 1162} 1163 1164template <class Impl> 1165inline int 1166DefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 1167{ 1168 int num_free = freeEntries[tid].sqEntries - 1169 (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 1170 DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 1171 "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 1172 storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 1173 return num_free; 1174} 1175 1176template <class Impl> 1177unsigned 1178DefaultRename<Impl>::validInsts() 1179{ 1180 unsigned inst_count = 0; 1181 1182 for (int i=0; i<fromDecode->size; i++) { 1183 if (!fromDecode->insts[i]->isSquashed()) 1184 inst_count++; 1185 } 1186 1187 return inst_count; 1188} 1189 1190template <class Impl> 1191void 1192DefaultRename<Impl>::readStallSignals(ThreadID tid) 1193{ 1194 if (fromIEW->iewBlock[tid]) { 1195 stalls[tid].iew = true; 1196 } 1197 1198 if (fromIEW->iewUnblock[tid]) { 1199 assert(stalls[tid].iew); 1200 stalls[tid].iew = false; 1201 } 1202} 1203 1204template <class Impl> 1205bool 1206DefaultRename<Impl>::checkStall(ThreadID tid) 1207{ 1208 bool ret_val = false; 1209 1210 if (stalls[tid].iew) { 1211 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1212 ret_val = true; 1213 } else if (calcFreeROBEntries(tid) <= 0) { 1214 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1215 ret_val = true; 1216 } else if (calcFreeIQEntries(tid) <= 0) { 1217 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1218 ret_val = true; 1219 } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 1220 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1221 ret_val = true; 1222 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1223 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1224 ret_val = true; 1225 } else if (renameStatus[tid] == SerializeStall && 1226 (!emptyROB[tid] || instsInProgress[tid])) { 1227 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1228 "empty.\n", 1229 tid); 1230 ret_val = true; 1231 } 1232 1233 return ret_val; 1234} 1235 1236template <class Impl> 1237void 1238DefaultRename<Impl>::readFreeEntries(ThreadID tid) 1239{ 1240 if (fromIEW->iewInfo[tid].usedIQ) 1241 freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 1242 1243 if (fromIEW->iewInfo[tid].usedLSQ) { 1244 freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 1245 freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 1246 } 1247 1248 if (fromCommit->commitInfo[tid].usedROB) { 1249 freeEntries[tid].robEntries = 1250 fromCommit->commitInfo[tid].freeROBEntries; 1251 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1252 } 1253 1254 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 1255 "Free LQ: %i, Free SQ: %i\n", 1256 tid, 1257 freeEntries[tid].iqEntries, 1258 freeEntries[tid].robEntries, 1259 freeEntries[tid].lqEntries, 1260 freeEntries[tid].sqEntries); 1261 1262 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1263 tid, instsInProgress[tid]); 1264} 1265 1266template <class Impl> 1267bool 1268DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 1269{ 1270 // Check if there's a squash signal, squash if there is 1271 // Check stall signals, block if necessary. 1272 // If status was blocked 1273 // check if stall conditions have passed 1274 // if so then go to unblocking 1275 // If status was Squashing 1276 // check if squashing is not high. Switch to running this cycle. 1277 // If status was serialize stall 1278 // check if ROB is empty and no insts are in flight to the ROB 1279 1280 readFreeEntries(tid); 1281 readStallSignals(tid); 1282 1283 if (fromCommit->commitInfo[tid].squash) { 1284 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1285 "commit.\n", tid); 1286 1287 squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 1288 1289 return true; 1290 } 1291 1292 if (checkStall(tid)) { 1293 return block(tid); 1294 } 1295 1296 if (renameStatus[tid] == Blocked) { 1297 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1298 tid); 1299 1300 renameStatus[tid] = Unblocking; 1301 1302 unblock(tid); 1303 1304 return true; 1305 } 1306 1307 if (renameStatus[tid] == Squashing) { 1308 // Switch status to running if rename isn't being told to block or 1309 // squash this cycle. 1310 if (resumeSerialize) { 1311 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1312 tid); 1313 1314 renameStatus[tid] = SerializeStall; 1315 return true; 1316 } else if (resumeUnblocking) { 1317 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1318 tid); 1319 renameStatus[tid] = Unblocking; 1320 return true; 1321 } else { 1322 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1323 tid); 1324 1325 renameStatus[tid] = Running; 1326 return false; 1327 } 1328 } 1329 1330 if (renameStatus[tid] == SerializeStall) { 1331 // Stall ends once the ROB is free. 1332 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1333 "unblocking.\n", tid); 1334 1335 DynInstPtr serial_inst = serializeInst[tid]; 1336 1337 renameStatus[tid] = Unblocking; 1338 1339 unblock(tid); 1340 1341 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1342 "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 1343 1344 // Put instruction into queue here. 1345 serial_inst->clearSerializeBefore(); 1346 1347 if (!skidBuffer[tid].empty()) { 1348 skidBuffer[tid].push_front(serial_inst); 1349 } else { 1350 insts[tid].push_front(serial_inst); 1351 } 1352 1353 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1354 " Adding to front of list.\n", tid); 1355 1356 serializeInst[tid] = NULL; 1357 1358 return true; 1359 } 1360 1361 // If we've reached this point, we have not gotten any signals that 1362 // cause rename to change its status. Rename remains the same as before. 1363 return false; 1364} 1365 1366template<class Impl> 1367void 1368DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 1369{ 1370 if (inst_list.empty()) { 1371 // Mark a bit to say that I must serialize on the next instruction. 1372 serializeOnNextInst[tid] = true; 1373 return; 1374 } 1375 1376 // Set the next instruction as serializing. 1377 inst_list.front()->setSerializeBefore(); 1378} 1379 1380template <class Impl> 1381inline void 1382DefaultRename<Impl>::incrFullStat(const FullSource &source) 1383{ 1384 switch (source) { 1385 case ROB: 1386 ++renameROBFullEvents; 1387 break; 1388 case IQ: 1389 ++renameIQFullEvents; 1390 break; 1391 case LQ: 1392 ++renameLQFullEvents; 1393 break; 1394 case SQ: 1395 ++renameSQFullEvents; 1396 break; 1397 default: 1398 panic("Rename full stall stat should be incremented for a reason!"); 1399 break; 1400 } 1401} 1402 1403template <class Impl> 1404void 1405DefaultRename<Impl>::dumpHistory() 1406{ 1407 typename std::list<RenameHistory>::iterator buf_it; 1408 1409 for (ThreadID tid = 0; tid < numThreads; tid++) { 1410 1411 buf_it = historyBuffer[tid].begin(); 1412 1413 while (buf_it != historyBuffer[tid].end()) { 1414 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1415 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1416 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1417 1418 buf_it++; 1419 } 1420 } 1421} 1422 1423#endif//__CPU_O3_RENAME_IMPL_HH__ 1424