rename_impl.hh revision 9920
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 451060SN/A#include <list> 461060SN/A 473773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 486329Sgblack@eecs.umich.edu#include "arch/registers.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/o3/rename.hh" 519913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 528232Snate@binkert.org#include "debug/Activity.hh" 538232Snate@binkert.org#include "debug/Rename.hh" 549527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 555529Snate@binkert.org#include "params/DerivO3CPU.hh" 561060SN/A 576221Snate@binkert.orgusing namespace std; 586221Snate@binkert.org 591061SN/Atemplate <class Impl> 605529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 614329Sktlim@umich.edu : cpu(_cpu), 624329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 632292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 642292SN/A commitToRenameDelay(params->commitToRenameDelay), 652292SN/A renameWidth(params->renameWidth), 662292SN/A commitWidth(params->commitWidth), 675529Snate@binkert.org numThreads(params->numThreads), 689920Syasuko.eckert@amd.com maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 699920Syasuko.eckert@amd.com + params->numPhysCCRegs) 701060SN/A{ 712292SN/A // @todo: Make into a parameter. 728907Slukefahr@umich.edu skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 732292SN/A} 742292SN/A 752292SN/Atemplate <class Impl> 762292SN/Astd::string 772292SN/ADefaultRename<Impl>::name() const 782292SN/A{ 792292SN/A return cpu->name() + ".rename"; 801060SN/A} 811060SN/A 821061SN/Atemplate <class Impl> 831060SN/Avoid 842292SN/ADefaultRename<Impl>::regStats() 851062SN/A{ 861062SN/A renameSquashCycles 878240Snate@binkert.org .name(name() + ".SquashCycles") 881062SN/A .desc("Number of cycles rename is squashing") 891062SN/A .prereq(renameSquashCycles); 901062SN/A renameIdleCycles 918240Snate@binkert.org .name(name() + ".IdleCycles") 921062SN/A .desc("Number of cycles rename is idle") 931062SN/A .prereq(renameIdleCycles); 941062SN/A renameBlockCycles 958240Snate@binkert.org .name(name() + ".BlockCycles") 961062SN/A .desc("Number of cycles rename is blocking") 971062SN/A .prereq(renameBlockCycles); 982301SN/A renameSerializeStallCycles 998240Snate@binkert.org .name(name() + ".serializeStallCycles") 1002301SN/A .desc("count of cycles rename stalled for serializing inst") 1012301SN/A .flags(Stats::total); 1022292SN/A renameRunCycles 1038240Snate@binkert.org .name(name() + ".RunCycles") 1042292SN/A .desc("Number of cycles rename is running") 1052292SN/A .prereq(renameIdleCycles); 1061062SN/A renameUnblockCycles 1078240Snate@binkert.org .name(name() + ".UnblockCycles") 1081062SN/A .desc("Number of cycles rename is unblocking") 1091062SN/A .prereq(renameUnblockCycles); 1101062SN/A renameRenamedInsts 1118240Snate@binkert.org .name(name() + ".RenamedInsts") 1121062SN/A .desc("Number of instructions processed by rename") 1131062SN/A .prereq(renameRenamedInsts); 1141062SN/A renameSquashedInsts 1158240Snate@binkert.org .name(name() + ".SquashedInsts") 1161062SN/A .desc("Number of squashed instructions processed by rename") 1171062SN/A .prereq(renameSquashedInsts); 1181062SN/A renameROBFullEvents 1198240Snate@binkert.org .name(name() + ".ROBFullEvents") 1202292SN/A .desc("Number of times rename has blocked due to ROB full") 1211062SN/A .prereq(renameROBFullEvents); 1221062SN/A renameIQFullEvents 1238240Snate@binkert.org .name(name() + ".IQFullEvents") 1242292SN/A .desc("Number of times rename has blocked due to IQ full") 1251062SN/A .prereq(renameIQFullEvents); 1262292SN/A renameLSQFullEvents 1278240Snate@binkert.org .name(name() + ".LSQFullEvents") 1282292SN/A .desc("Number of times rename has blocked due to LSQ full") 1292292SN/A .prereq(renameLSQFullEvents); 1301062SN/A renameFullRegistersEvents 1318240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1321062SN/A .desc("Number of times there has been no free registers") 1331062SN/A .prereq(renameFullRegistersEvents); 1341062SN/A renameRenamedOperands 1358240Snate@binkert.org .name(name() + ".RenamedOperands") 1361062SN/A .desc("Number of destination operands rename has renamed") 1371062SN/A .prereq(renameRenamedOperands); 1381062SN/A renameRenameLookups 1398240Snate@binkert.org .name(name() + ".RenameLookups") 1401062SN/A .desc("Number of register rename lookups that rename has made") 1411062SN/A .prereq(renameRenameLookups); 1421062SN/A renameCommittedMaps 1438240Snate@binkert.org .name(name() + ".CommittedMaps") 1441062SN/A .desc("Number of HB maps that are committed") 1451062SN/A .prereq(renameCommittedMaps); 1461062SN/A renameUndoneMaps 1478240Snate@binkert.org .name(name() + ".UndoneMaps") 1481062SN/A .desc("Number of HB maps that are undone due to squashing") 1491062SN/A .prereq(renameUndoneMaps); 1502301SN/A renamedSerializing 1518240Snate@binkert.org .name(name() + ".serializingInsts") 1522301SN/A .desc("count of serializing insts renamed") 1532301SN/A .flags(Stats::total) 1542301SN/A ; 1552301SN/A renamedTempSerializing 1568240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1572301SN/A .desc("count of temporary serializing insts renamed") 1582301SN/A .flags(Stats::total) 1592301SN/A ; 1602307SN/A renameSkidInsts 1618240Snate@binkert.org .name(name() + ".skidInsts") 1622307SN/A .desc("count of insts added to the skid buffer") 1632307SN/A .flags(Stats::total) 1642307SN/A ; 1657897Shestness@cs.utexas.edu intRenameLookups 1668240Snate@binkert.org .name(name() + ".int_rename_lookups") 1677897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1687897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1697897Shestness@cs.utexas.edu fpRenameLookups 1708240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1717897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1727897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1731062SN/A} 1741062SN/A 1751062SN/Atemplate <class Impl> 1761062SN/Avoid 1772292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1781060SN/A{ 1791060SN/A timeBuffer = tb_ptr; 1801060SN/A 1811060SN/A // Setup wire to read information from time buffer, from IEW stage. 1821060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1831060SN/A 1841060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1851060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1861060SN/A 1871060SN/A // Setup wire to write information to previous stages. 1881060SN/A toDecode = timeBuffer->getWire(0); 1891060SN/A} 1901060SN/A 1911061SN/Atemplate <class Impl> 1921060SN/Avoid 1932292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1941060SN/A{ 1951060SN/A renameQueue = rq_ptr; 1961060SN/A 1971060SN/A // Setup wire to write information to future stages. 1981060SN/A toIEW = renameQueue->getWire(0); 1991060SN/A} 2001060SN/A 2011061SN/Atemplate <class Impl> 2021060SN/Avoid 2032292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2041060SN/A{ 2051060SN/A decodeQueue = dq_ptr; 2061060SN/A 2071060SN/A // Setup wire to get information from decode. 2081060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2091060SN/A} 2101060SN/A 2111061SN/Atemplate <class Impl> 2121060SN/Avoid 2139427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2141060SN/A{ 2159444SAndreas.Sandberg@ARM.com resetStage(); 2169444SAndreas.Sandberg@ARM.com} 2179444SAndreas.Sandberg@ARM.com 2189444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2199444SAndreas.Sandberg@ARM.comvoid 2209444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2219444SAndreas.Sandberg@ARM.com{ 2229444SAndreas.Sandberg@ARM.com _status = Inactive; 2239444SAndreas.Sandberg@ARM.com 2249444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2259444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2269444SAndreas.Sandberg@ARM.com 2272329SN/A // Grab the number of free entries directly from the stages. 2286221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2299444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2309444SAndreas.Sandberg@ARM.com 2312292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2322292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2332292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2342292SN/A emptyROB[tid] = true; 2359444SAndreas.Sandberg@ARM.com 2369444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2379444SAndreas.Sandberg@ARM.com stalls[tid].commit = false; 2389444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2399444SAndreas.Sandberg@ARM.com 2409444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 2419444SAndreas.Sandberg@ARM.com 2429444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2432292SN/A } 2441060SN/A} 2451060SN/A 2462292SN/Atemplate<class Impl> 2472292SN/Avoid 2486221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2492292SN/A{ 2502292SN/A activeThreads = at_ptr; 2512292SN/A} 2522292SN/A 2532292SN/A 2541061SN/Atemplate <class Impl> 2551060SN/Avoid 2562292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2571060SN/A{ 2586221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2596221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2601060SN/A} 2611060SN/A 2621061SN/Atemplate <class Impl> 2631060SN/Avoid 2642292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2651060SN/A{ 2662292SN/A freeList = fl_ptr; 2672292SN/A} 2681060SN/A 2692292SN/Atemplate<class Impl> 2702292SN/Avoid 2712292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2722292SN/A{ 2732292SN/A scoreboard = _scoreboard; 2741060SN/A} 2751060SN/A 2761061SN/Atemplate <class Impl> 2772863Sktlim@umich.edubool 2789444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 2791060SN/A{ 2809444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2819444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 2829444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 2839444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 2849444SAndreas.Sandberg@ARM.com !insts[tid].empty()) 2859444SAndreas.Sandberg@ARM.com return false; 2869444SAndreas.Sandberg@ARM.com } 2872863Sktlim@umich.edu return true; 2882316SN/A} 2891060SN/A 2902316SN/Atemplate <class Impl> 2912316SN/Avoid 2922307SN/ADefaultRename<Impl>::takeOverFrom() 2931060SN/A{ 2949444SAndreas.Sandberg@ARM.com resetStage(); 2959444SAndreas.Sandberg@ARM.com} 2961060SN/A 2979444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2989444SAndreas.Sandberg@ARM.comvoid 2999444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3009444SAndreas.Sandberg@ARM.com{ 3016221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3029444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3039444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3049444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3059444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3062307SN/A } 3072307SN/A} 3082307SN/A 3092307SN/Atemplate <class Impl> 3102307SN/Avoid 3116221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3121858SN/A{ 3132292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3141858SN/A 3152292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3162292SN/A // If it still needs to block, the blocking should happen the next 3172292SN/A // cycle and there should be space to hold everything due to the squash. 3182292SN/A if (renameStatus[tid] == Blocked || 3193788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3202292SN/A toDecode->renameUnblock[tid] = 1; 3212698Sktlim@umich.edu 3223788Sgblack@eecs.umich.edu resumeSerialize = false; 3232301SN/A serializeInst[tid] = NULL; 3243788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3253788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3263788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3273788Sgblack@eecs.umich.edu resumeSerialize = true; 3283788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3293788Sgblack@eecs.umich.edu } else { 3303788Sgblack@eecs.umich.edu resumeSerialize = false; 3313788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3323788Sgblack@eecs.umich.edu 3333788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3343788Sgblack@eecs.umich.edu } 3352292SN/A } 3362292SN/A 3372292SN/A // Set the status to Squashing. 3382292SN/A renameStatus[tid] = Squashing; 3392292SN/A 3402329SN/A // Squash any instructions from decode. 3412292SN/A unsigned squashCount = 0; 3422292SN/A 3432292SN/A for (int i=0; i<fromDecode->size; i++) { 3442935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3452935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3462731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3472292SN/A wroteToTimeBuffer = true; 3482292SN/A squashCount++; 3492292SN/A } 3502935Sksewell@umich.edu 3512292SN/A } 3522292SN/A 3532935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3544632Sgblack@eecs.umich.edu // insts in them. 3553093Sksewell@umich.edu insts[tid].clear(); 3562292SN/A 3572292SN/A // Clear the skid buffer in case it has any data in it. 3583093Sksewell@umich.edu skidBuffer[tid].clear(); 3594632Sgblack@eecs.umich.edu 3602935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3612292SN/A} 3622292SN/A 3632292SN/Atemplate <class Impl> 3642292SN/Avoid 3652292SN/ADefaultRename<Impl>::tick() 3662292SN/A{ 3672292SN/A wroteToTimeBuffer = false; 3682292SN/A 3692292SN/A blockThisCycle = false; 3702292SN/A 3712292SN/A bool status_change = false; 3722292SN/A 3732292SN/A toIEWIndex = 0; 3742292SN/A 3752292SN/A sortInsts(); 3762292SN/A 3776221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3786221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3792292SN/A 3802292SN/A // Check stall and squash signals. 3813867Sbinkertn@umich.edu while (threads != end) { 3826221Snate@binkert.org ThreadID tid = *threads++; 3832292SN/A 3842292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3852292SN/A 3862292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3872292SN/A 3882292SN/A rename(status_change, tid); 3892292SN/A } 3902292SN/A 3912292SN/A if (status_change) { 3922292SN/A updateStatus(); 3932292SN/A } 3942292SN/A 3952292SN/A if (wroteToTimeBuffer) { 3962292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 3972292SN/A cpu->activityThisCycle(); 3982292SN/A } 3992292SN/A 4003867Sbinkertn@umich.edu threads = activeThreads->begin(); 4012292SN/A 4023867Sbinkertn@umich.edu while (threads != end) { 4036221Snate@binkert.org ThreadID tid = *threads++; 4042292SN/A 4052292SN/A // If we committed this cycle then doneSeqNum will be > 0 4062292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4072292SN/A !fromCommit->commitInfo[tid].squash && 4082292SN/A renameStatus[tid] != Squashing) { 4092292SN/A 4102292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4112292SN/A tid); 4122292SN/A } 4132292SN/A } 4142292SN/A 4152292SN/A // @todo: make into updateProgress function 4166221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4172292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4182292SN/A 4192292SN/A assert(instsInProgress[tid] >=0); 4202292SN/A } 4212292SN/A 4222292SN/A} 4232292SN/A 4242292SN/Atemplate<class Impl> 4252292SN/Avoid 4266221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4272292SN/A{ 4282292SN/A // If status is Running or idle, 4292292SN/A // call renameInsts() 4302292SN/A // If status is Unblocking, 4312292SN/A // buffer any instructions coming from decode 4322292SN/A // continue trying to empty skid buffer 4332292SN/A // check if stall conditions have passed 4342292SN/A 4352292SN/A if (renameStatus[tid] == Blocked) { 4362292SN/A ++renameBlockCycles; 4372292SN/A } else if (renameStatus[tid] == Squashing) { 4382292SN/A ++renameSquashCycles; 4392301SN/A } else if (renameStatus[tid] == SerializeStall) { 4402301SN/A ++renameSerializeStallCycles; 4413788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4423788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4433788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4443788Sgblack@eecs.umich.edu if (resumeSerialize) { 4453788Sgblack@eecs.umich.edu resumeSerialize = false; 4463788Sgblack@eecs.umich.edu block(tid); 4473788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4483788Sgblack@eecs.umich.edu } 4493798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4503798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4513798Sgblack@eecs.umich.edu block(tid); 4523798Sgblack@eecs.umich.edu resumeUnblocking = false; 4533798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4543798Sgblack@eecs.umich.edu } 4552292SN/A } 4562292SN/A 4572292SN/A if (renameStatus[tid] == Running || 4582292SN/A renameStatus[tid] == Idle) { 4592292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4602292SN/A "stage.\n", tid); 4612292SN/A 4622292SN/A renameInsts(tid); 4632292SN/A } else if (renameStatus[tid] == Unblocking) { 4642292SN/A renameInsts(tid); 4652292SN/A 4662292SN/A if (validInsts()) { 4672292SN/A // Add the current inputs to the skid buffer so they can be 4682292SN/A // reprocessed when this stage unblocks. 4692292SN/A skidInsert(tid); 4702292SN/A } 4712292SN/A 4722292SN/A // If we switched over to blocking, then there's a potential for 4732292SN/A // an overall status change. 4742292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4751858SN/A } 4761858SN/A} 4771858SN/A 4781858SN/Atemplate <class Impl> 4791858SN/Avoid 4806221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4811858SN/A{ 4822292SN/A // Instructions can be either in the skid buffer or the queue of 4832292SN/A // instructions coming from decode, depending on the status. 4842292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4852292SN/A skidBuffer[tid].size() : insts[tid].size(); 4861858SN/A 4872292SN/A // Check the decode queue to see if instructions are available. 4882292SN/A // If there are no available instructions to rename, then do nothing. 4892292SN/A if (insts_available == 0) { 4902292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4912292SN/A tid); 4922292SN/A // Should I change status to idle? 4932292SN/A ++renameIdleCycles; 4942292SN/A return; 4952292SN/A } else if (renameStatus[tid] == Unblocking) { 4962292SN/A ++renameUnblockCycles; 4972292SN/A } else if (renameStatus[tid] == Running) { 4982292SN/A ++renameRunCycles; 4992292SN/A } 5001858SN/A 5012292SN/A DynInstPtr inst; 5022292SN/A 5032292SN/A // Will have to do a different calculation for the number of free 5042292SN/A // entries. 5052292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5062292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5072292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5082292SN/A int min_free_entries = free_rob_entries; 5092292SN/A 5102292SN/A FullSource source = ROB; 5112292SN/A 5122292SN/A if (free_iq_entries < min_free_entries) { 5132292SN/A min_free_entries = free_iq_entries; 5142292SN/A source = IQ; 5152292SN/A } 5162292SN/A 5172292SN/A if (free_lsq_entries < min_free_entries) { 5182292SN/A min_free_entries = free_lsq_entries; 5192292SN/A source = LSQ; 5202292SN/A } 5212292SN/A 5222292SN/A // Check if there's any space left. 5232292SN/A if (min_free_entries <= 0) { 5242292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5252292SN/A "entries.\n" 5262292SN/A "ROB has %i free entries.\n" 5272292SN/A "IQ has %i free entries.\n" 5282292SN/A "LSQ has %i free entries.\n", 5292292SN/A tid, 5302292SN/A free_rob_entries, 5312292SN/A free_iq_entries, 5322292SN/A free_lsq_entries); 5332292SN/A 5342292SN/A blockThisCycle = true; 5352292SN/A 5362292SN/A block(tid); 5372292SN/A 5382292SN/A incrFullStat(source); 5392292SN/A 5402292SN/A return; 5412292SN/A } else if (min_free_entries < insts_available) { 5422292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5432292SN/A "%i insts available, but only %i insts can be " 5442292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5452292SN/A tid, insts_available, min_free_entries); 5462292SN/A 5472292SN/A insts_available = min_free_entries; 5482292SN/A 5492292SN/A blockThisCycle = true; 5502292SN/A 5512292SN/A incrFullStat(source); 5522292SN/A } 5532292SN/A 5542292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5552292SN/A skidBuffer[tid] : insts[tid]; 5562292SN/A 5572292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5582292SN/A "send iew.\n", tid, insts_available); 5592292SN/A 5602292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5612292SN/A "dispatched to IQ last cycle.\n", 5622292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5632292SN/A 5642292SN/A // Handle serializing the next instruction if necessary. 5652292SN/A if (serializeOnNextInst[tid]) { 5662292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5672292SN/A // ROB already empty; no need to serialize. 5682292SN/A serializeOnNextInst[tid] = false; 5692292SN/A } else if (!insts_to_rename.empty()) { 5702292SN/A insts_to_rename.front()->setSerializeBefore(); 5712292SN/A } 5722292SN/A } 5732292SN/A 5742292SN/A int renamed_insts = 0; 5752292SN/A 5762292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5772292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5782292SN/A 5792292SN/A assert(!insts_to_rename.empty()); 5802292SN/A 5812292SN/A inst = insts_to_rename.front(); 5822292SN/A 5832292SN/A insts_to_rename.pop_front(); 5842292SN/A 5852292SN/A if (renameStatus[tid] == Unblocking) { 5867720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 5877720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 5882292SN/A } 5892292SN/A 5902292SN/A if (inst->isSquashed()) { 5917720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 5927720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 5937720Sgblack@eecs.umich.edu inst->pcState()); 5942292SN/A 5952292SN/A ++renameSquashedInsts; 5962292SN/A 5972292SN/A // Decrement how many instructions are available. 5982292SN/A --insts_available; 5992292SN/A 6002292SN/A continue; 6012292SN/A } 6022292SN/A 6032292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6047720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6052292SN/A 6069531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6079531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 6089531Sgeoffrey.blake@arm.com if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6099531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6109531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6119531Sgeoffrey.blake@arm.com blockThisCycle = true; 6129531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6139531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6149531Sgeoffrey.blake@arm.com 6159531Sgeoffrey.blake@arm.com break; 6169531Sgeoffrey.blake@arm.com } 6179531Sgeoffrey.blake@arm.com 6182292SN/A // Handle serializeAfter/serializeBefore instructions. 6192292SN/A // serializeAfter marks the next instruction as serializeBefore. 6202292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6212292SN/A // is empty. 6222336SN/A 6232336SN/A // In this model, IPR accesses are serialize before 6242336SN/A // instructions, and store conditionals are serialize after 6252336SN/A // instructions. This is mainly due to lack of support for 6262336SN/A // out-of-order operations of either of those classes of 6272336SN/A // instructions. 6282336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6292336SN/A !inst->isSerializeHandled()) { 6302292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6312292SN/A 6322301SN/A if (!inst->isTempSerializeBefore()) { 6332301SN/A renamedSerializing++; 6342292SN/A inst->setSerializeHandled(); 6352301SN/A } else { 6362301SN/A renamedTempSerializing++; 6372301SN/A } 6382292SN/A 6392301SN/A // Change status over to SerializeStall so that other stages know 6402292SN/A // what this is blocked on. 6412301SN/A renameStatus[tid] = SerializeStall; 6422292SN/A 6432301SN/A serializeInst[tid] = inst; 6442292SN/A 6452292SN/A blockThisCycle = true; 6462292SN/A 6472292SN/A break; 6482336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6492336SN/A !inst->isSerializeHandled()) { 6502292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6512292SN/A 6522307SN/A renamedSerializing++; 6532307SN/A 6542292SN/A inst->setSerializeHandled(); 6552292SN/A 6562292SN/A serializeAfter(insts_to_rename, tid); 6572292SN/A } 6582292SN/A 6592292SN/A renameSrcRegs(inst, inst->threadNumber); 6602292SN/A 6612292SN/A renameDestRegs(inst, inst->threadNumber); 6622292SN/A 6632292SN/A ++renamed_insts; 6642292SN/A 6658471SGiacomo.Gabrielli@arm.com 6662292SN/A // Put instruction in rename queue. 6672292SN/A toIEW->insts[toIEWIndex] = inst; 6682292SN/A ++(toIEW->size); 6692292SN/A 6702292SN/A // Increment which instruction we're on. 6712292SN/A ++toIEWIndex; 6722292SN/A 6732292SN/A // Decrement how many instructions are available. 6742292SN/A --insts_available; 6752292SN/A } 6762292SN/A 6772292SN/A instsInProgress[tid] += renamed_insts; 6782307SN/A renameRenamedInsts += renamed_insts; 6792292SN/A 6802292SN/A // If we wrote to the time buffer, record this. 6812292SN/A if (toIEWIndex) { 6822292SN/A wroteToTimeBuffer = true; 6832292SN/A } 6842292SN/A 6852292SN/A // Check if there's any instructions left that haven't yet been renamed. 6862292SN/A // If so then block. 6872292SN/A if (insts_available) { 6882292SN/A blockThisCycle = true; 6892292SN/A } 6902292SN/A 6912292SN/A if (blockThisCycle) { 6922292SN/A block(tid); 6932292SN/A toDecode->renameUnblock[tid] = false; 6942292SN/A } 6952292SN/A} 6962292SN/A 6972292SN/Atemplate<class Impl> 6982292SN/Avoid 6996221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7002292SN/A{ 7012292SN/A DynInstPtr inst = NULL; 7022292SN/A 7032292SN/A while (!insts[tid].empty()) { 7042292SN/A inst = insts[tid].front(); 7052292SN/A 7062292SN/A insts[tid].pop_front(); 7072292SN/A 7082292SN/A assert(tid == inst->threadNumber); 7092292SN/A 7107720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7117720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7122292SN/A 7132307SN/A ++renameSkidInsts; 7142307SN/A 7152292SN/A skidBuffer[tid].push_back(inst); 7162292SN/A } 7172292SN/A 7182292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7193798Sgblack@eecs.umich.edu { 7203798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7213798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7223798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7233798Sgblack@eecs.umich.edu { 7243798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7257720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7263798Sgblack@eecs.umich.edu (*it)->seqNum); 7273798Sgblack@eecs.umich.edu } 7282292SN/A panic("Skidbuffer Exceeded Max Size"); 7293798Sgblack@eecs.umich.edu } 7302292SN/A} 7312292SN/A 7322292SN/Atemplate <class Impl> 7332292SN/Avoid 7342292SN/ADefaultRename<Impl>::sortInsts() 7352292SN/A{ 7362292SN/A int insts_from_decode = fromDecode->size; 7372292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7382292SN/A DynInstPtr inst = fromDecode->insts[i]; 7392292SN/A insts[inst->threadNumber].push_back(inst); 7409527SMatt.Horsnell@arm.com#if TRACING_ON 7419527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7429527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7439527SMatt.Horsnell@arm.com } 7449527SMatt.Horsnell@arm.com#endif 7452292SN/A } 7462292SN/A} 7472292SN/A 7482292SN/Atemplate<class Impl> 7492292SN/Abool 7502292SN/ADefaultRename<Impl>::skidsEmpty() 7512292SN/A{ 7526221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7536221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7542292SN/A 7553867Sbinkertn@umich.edu while (threads != end) { 7566221Snate@binkert.org ThreadID tid = *threads++; 7573867Sbinkertn@umich.edu 7583867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7592292SN/A return false; 7602292SN/A } 7612292SN/A 7622292SN/A return true; 7632292SN/A} 7642292SN/A 7652292SN/Atemplate<class Impl> 7662292SN/Avoid 7672292SN/ADefaultRename<Impl>::updateStatus() 7682292SN/A{ 7692292SN/A bool any_unblocking = false; 7702292SN/A 7716221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7726221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7732292SN/A 7743867Sbinkertn@umich.edu while (threads != end) { 7756221Snate@binkert.org ThreadID tid = *threads++; 7762292SN/A 7772292SN/A if (renameStatus[tid] == Unblocking) { 7782292SN/A any_unblocking = true; 7792292SN/A break; 7802292SN/A } 7812292SN/A } 7822292SN/A 7832292SN/A // Rename will have activity if it's unblocking. 7842292SN/A if (any_unblocking) { 7852292SN/A if (_status == Inactive) { 7862292SN/A _status = Active; 7872292SN/A 7882292SN/A DPRINTF(Activity, "Activating stage.\n"); 7892292SN/A 7902733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7912292SN/A } 7922292SN/A } else { 7932292SN/A // If it's not unblocking, then rename will not have any internal 7942292SN/A // activity. Switch it to inactive. 7952292SN/A if (_status == Active) { 7962292SN/A _status = Inactive; 7972292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 7982292SN/A 7992733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8002292SN/A } 8012292SN/A } 8022292SN/A} 8032292SN/A 8042292SN/Atemplate <class Impl> 8052292SN/Abool 8066221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8072292SN/A{ 8082292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8092292SN/A 8102292SN/A // Add the current inputs onto the skid buffer, so they can be 8112292SN/A // reprocessed when this stage unblocks. 8122292SN/A skidInsert(tid); 8132292SN/A 8142292SN/A // Only signal backwards to block if the previous stages do not think 8152292SN/A // rename is already blocked. 8162292SN/A if (renameStatus[tid] != Blocked) { 8173798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8183798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8193798Sgblack@eecs.umich.edu // stages to block. 8203798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8212292SN/A toDecode->renameBlock[tid] = true; 8222292SN/A toDecode->renameUnblock[tid] = false; 8232292SN/A wroteToTimeBuffer = true; 8242292SN/A } 8252292SN/A 8262329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8272329SN/A // it would not know to complete the serialize stall. 8282301SN/A if (renameStatus[tid] != SerializeStall) { 8292292SN/A // Set status to Blocked. 8302292SN/A renameStatus[tid] = Blocked; 8312292SN/A return true; 8322292SN/A } 8332292SN/A } 8342292SN/A 8352292SN/A return false; 8362292SN/A} 8372292SN/A 8382292SN/Atemplate <class Impl> 8392292SN/Abool 8406221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8412292SN/A{ 8422292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8432292SN/A 8442292SN/A // Rename is done unblocking if the skid buffer is empty. 8452301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8462292SN/A 8472292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8482292SN/A 8492292SN/A toDecode->renameUnblock[tid] = true; 8502292SN/A wroteToTimeBuffer = true; 8512292SN/A 8522292SN/A renameStatus[tid] = Running; 8532292SN/A return true; 8542292SN/A } 8552292SN/A 8562292SN/A return false; 8572292SN/A} 8582292SN/A 8592292SN/Atemplate <class Impl> 8602292SN/Avoid 8616221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8622292SN/A{ 8632980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8642980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8652292SN/A 8661060SN/A // After a syscall squashes everything, the history buffer may be empty 8671060SN/A // but the ROB may still be squashing instructions. 8682292SN/A if (historyBuffer[tid].empty()) { 8691060SN/A return; 8701060SN/A } 8711060SN/A 8721060SN/A // Go through the most recent instructions, undoing the mappings 8731060SN/A // they did and freeing up the registers. 8742292SN/A while (!historyBuffer[tid].empty() && 8759919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 8762292SN/A assert(hb_it != historyBuffer[tid].end()); 8771062SN/A 8782292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8799919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 8801060SN/A 8819919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 8829919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 8839919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 8849919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 8859919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 8869919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 8879919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 8889919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 8899919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 8909919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8911060SN/A 8929919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 8939919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 8949919Ssteve.reinhardt@amd.com } 8951062SN/A 8962292SN/A historyBuffer[tid].erase(hb_it++); 8971061SN/A 8981062SN/A ++renameUndoneMaps; 8991060SN/A } 9001060SN/A} 9011060SN/A 9021060SN/Atemplate<class Impl> 9031060SN/Avoid 9046221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9051060SN/A{ 9062292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9072292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9082292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9092292SN/A 9102980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9112980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9121060SN/A 9131061SN/A --hb_it; 9141060SN/A 9152292SN/A if (historyBuffer[tid].empty()) { 9162292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9172292SN/A return; 9182292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9192292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9202292SN/A "that a syscall happened recently.\n", tid); 9211060SN/A return; 9221060SN/A } 9231060SN/A 9242292SN/A // Commit all the renames up until (and including) the committed sequence 9252292SN/A // number. Some or even all of the committed instructions may not have 9262292SN/A // rename histories if they did not have destination registers that were 9272292SN/A // renamed. 9282292SN/A while (!historyBuffer[tid].empty() && 9292292SN/A hb_it != historyBuffer[tid].end() && 9309919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9311060SN/A 9322329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9332329SN/A "[sn:%lli].\n", 9349919Ssteve.reinhardt@amd.com tid, hb_it->prevPhysReg, hb_it->instSeqNum); 9351061SN/A 9369919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 9379919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 9389919Ssteve.reinhardt@amd.com // the old one. 9399919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9409919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 9419919Ssteve.reinhardt@amd.com } 9429919Ssteve.reinhardt@amd.com 9432292SN/A ++renameCommittedMaps; 9441061SN/A 9452292SN/A historyBuffer[tid].erase(hb_it--); 9461060SN/A } 9471060SN/A} 9481060SN/A 9491061SN/Atemplate <class Impl> 9501061SN/Ainline void 9516221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9521061SN/A{ 9539919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 9549919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 9551061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9561061SN/A 9571061SN/A // Get the architectual register numbers from the source and 9589919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 9592292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9601061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9619919Ssteve.reinhardt@amd.com RegIndex rel_src_reg; 9629919Ssteve.reinhardt@amd.com RegIndex flat_rel_src_reg; 9639919Ssteve.reinhardt@amd.com PhysRegIndex renamed_reg; 9649919Ssteve.reinhardt@amd.com 9659919Ssteve.reinhardt@amd.com switch (regIdxToClass(src_reg, &rel_src_reg)) { 9669913Ssteve.reinhardt@amd.com case IntRegClass: 9679919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 9689919Ssteve.reinhardt@amd.com renamed_reg = map->lookupInt(flat_rel_src_reg); 9699919Ssteve.reinhardt@amd.com intRenameLookups++; 9709913Ssteve.reinhardt@amd.com break; 9719913Ssteve.reinhardt@amd.com 9729913Ssteve.reinhardt@amd.com case FloatRegClass: 9739919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 9749919Ssteve.reinhardt@amd.com renamed_reg = map->lookupFloat(flat_rel_src_reg); 9759919Ssteve.reinhardt@amd.com fpRenameLookups++; 9769913Ssteve.reinhardt@amd.com break; 9779913Ssteve.reinhardt@amd.com 9789920Syasuko.eckert@amd.com case CCRegClass: 9799920Syasuko.eckert@amd.com flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 9809920Syasuko.eckert@amd.com renamed_reg = map->lookupCC(flat_rel_src_reg); 9819920Syasuko.eckert@amd.com break; 9829920Syasuko.eckert@amd.com 9839913Ssteve.reinhardt@amd.com case MiscRegClass: 9849919Ssteve.reinhardt@amd.com // misc regs don't get flattened 9859919Ssteve.reinhardt@amd.com flat_rel_src_reg = rel_src_reg; 9869919Ssteve.reinhardt@amd.com renamed_reg = map->lookupMisc(flat_rel_src_reg); 9879913Ssteve.reinhardt@amd.com break; 9889913Ssteve.reinhardt@amd.com 9899913Ssteve.reinhardt@amd.com default: 9907649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9913773Sgblack@eecs.umich.edu } 9924352Sgblack@eecs.umich.edu 9939919Ssteve.reinhardt@amd.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 9949919Ssteve.reinhardt@amd.com "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 9959919Ssteve.reinhardt@amd.com (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 9961061SN/A 9971061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9981061SN/A 9992292SN/A // See if the register is ready or not. 10009919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 10017767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10027767Sgblack@eecs.umich.edu tid, renamed_reg); 10031061SN/A 10041061SN/A inst->markSrcRegReady(src_idx); 10054636Sgblack@eecs.umich.edu } else { 10067767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10077767Sgblack@eecs.umich.edu tid, renamed_reg); 10081061SN/A } 10091062SN/A 10101062SN/A ++renameRenameLookups; 10111061SN/A } 10121061SN/A} 10131061SN/A 10141061SN/Atemplate <class Impl> 10151061SN/Ainline void 10166221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10171061SN/A{ 10189919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10199919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10201061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10211061SN/A 10222292SN/A // Rename the destination registers. 10232292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10242292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10259919Ssteve.reinhardt@amd.com RegIndex rel_dest_reg; 10269919Ssteve.reinhardt@amd.com RegIndex flat_rel_dest_reg; 10279919Ssteve.reinhardt@amd.com RegIndex flat_uni_dest_reg; 10289919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10299919Ssteve.reinhardt@amd.com 10309919Ssteve.reinhardt@amd.com switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 10319913Ssteve.reinhardt@amd.com case IntRegClass: 10329919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 10339919Ssteve.reinhardt@amd.com rename_result = map->renameInt(flat_rel_dest_reg); 10349919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 10359913Ssteve.reinhardt@amd.com break; 10369913Ssteve.reinhardt@amd.com 10379913Ssteve.reinhardt@amd.com case FloatRegClass: 10389919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 10399919Ssteve.reinhardt@amd.com rename_result = map->renameFloat(flat_rel_dest_reg); 10409919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 10419913Ssteve.reinhardt@amd.com break; 10429913Ssteve.reinhardt@amd.com 10439920Syasuko.eckert@amd.com case CCRegClass: 10449920Syasuko.eckert@amd.com flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 10459920Syasuko.eckert@amd.com rename_result = map->renameCC(flat_rel_dest_reg); 10469920Syasuko.eckert@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 10479920Syasuko.eckert@amd.com break; 10489920Syasuko.eckert@amd.com 10499913Ssteve.reinhardt@amd.com case MiscRegClass: 10509919Ssteve.reinhardt@amd.com // misc regs don't get flattened 10519919Ssteve.reinhardt@amd.com flat_rel_dest_reg = rel_dest_reg; 10529919Ssteve.reinhardt@amd.com rename_result = map->renameMisc(flat_rel_dest_reg); 10539919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 10549913Ssteve.reinhardt@amd.com break; 10559913Ssteve.reinhardt@amd.com 10569913Ssteve.reinhardt@amd.com default: 10577649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10583773Sgblack@eecs.umich.edu } 10593773Sgblack@eecs.umich.edu 10609919Ssteve.reinhardt@amd.com inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 10611061SN/A 10629919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 10639916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 10641062SN/A 10652292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10669919Ssteve.reinhardt@amd.com "reg %i.\n", tid, (int)flat_rel_dest_reg, 10672292SN/A (int)rename_result.first); 10681062SN/A 10692292SN/A // Record the rename information so that a history can be kept. 10709919Ssteve.reinhardt@amd.com RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 10712292SN/A rename_result.first, 10722292SN/A rename_result.second); 10731062SN/A 10742292SN/A historyBuffer[tid].push_front(hb_entry); 10751062SN/A 10762935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10772935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10782935Sksewell@umich.edu historyBuffer[tid].size(), 10792292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10801062SN/A 10812292SN/A // Tell the instruction to rename the appropriate destination 10822292SN/A // register (dest_idx) to the new physical register 10832292SN/A // (rename_result.first), and record the previous physical 10842292SN/A // register that the same logical register was renamed to 10852292SN/A // (rename_result.second). 10862292SN/A inst->renameDestReg(dest_idx, 10872292SN/A rename_result.first, 10882292SN/A rename_result.second); 10891062SN/A 10902292SN/A ++renameRenamedOperands; 10911061SN/A } 10921061SN/A} 10931061SN/A 10941061SN/Atemplate <class Impl> 10951061SN/Ainline int 10966221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 10971061SN/A{ 10982292SN/A int num_free = freeEntries[tid].robEntries - 10992292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11002292SN/A 11012292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11022292SN/A 11032292SN/A return num_free; 11041061SN/A} 11051061SN/A 11061061SN/Atemplate <class Impl> 11071061SN/Ainline int 11086221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11091061SN/A{ 11102292SN/A int num_free = freeEntries[tid].iqEntries - 11112292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11122292SN/A 11132292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11142292SN/A 11152292SN/A return num_free; 11162292SN/A} 11172292SN/A 11182292SN/Atemplate <class Impl> 11192292SN/Ainline int 11206221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11212292SN/A{ 11222292SN/A int num_free = freeEntries[tid].lsqEntries - 11232292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11242292SN/A 11252292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11262292SN/A 11272292SN/A return num_free; 11282292SN/A} 11292292SN/A 11302292SN/Atemplate <class Impl> 11312292SN/Aunsigned 11322292SN/ADefaultRename<Impl>::validInsts() 11332292SN/A{ 11342292SN/A unsigned inst_count = 0; 11352292SN/A 11362292SN/A for (int i=0; i<fromDecode->size; i++) { 11372731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11382292SN/A inst_count++; 11392292SN/A } 11402292SN/A 11412292SN/A return inst_count; 11422292SN/A} 11432292SN/A 11442292SN/Atemplate <class Impl> 11452292SN/Avoid 11466221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11472292SN/A{ 11482292SN/A if (fromIEW->iewBlock[tid]) { 11492292SN/A stalls[tid].iew = true; 11502292SN/A } 11512292SN/A 11522292SN/A if (fromIEW->iewUnblock[tid]) { 11532292SN/A assert(stalls[tid].iew); 11542292SN/A stalls[tid].iew = false; 11552292SN/A } 11562292SN/A 11572292SN/A if (fromCommit->commitBlock[tid]) { 11582292SN/A stalls[tid].commit = true; 11592292SN/A } 11602292SN/A 11612292SN/A if (fromCommit->commitUnblock[tid]) { 11622292SN/A assert(stalls[tid].commit); 11632292SN/A stalls[tid].commit = false; 11642292SN/A } 11652292SN/A} 11662292SN/A 11672292SN/Atemplate <class Impl> 11682292SN/Abool 11696221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11702292SN/A{ 11712292SN/A bool ret_val = false; 11722292SN/A 11732292SN/A if (stalls[tid].iew) { 11742292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11752292SN/A ret_val = true; 11762292SN/A } else if (stalls[tid].commit) { 11772292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11782292SN/A ret_val = true; 11792292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11802292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11812292SN/A ret_val = true; 11822292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11832292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11842292SN/A ret_val = true; 11852292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11862292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11872292SN/A ret_val = true; 11882292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11892292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11902292SN/A ret_val = true; 11912301SN/A } else if (renameStatus[tid] == SerializeStall && 11922292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11932301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11942292SN/A "empty.\n", 11952292SN/A tid); 11962292SN/A ret_val = true; 11972292SN/A } 11982292SN/A 11992292SN/A return ret_val; 12002292SN/A} 12012292SN/A 12022292SN/Atemplate <class Impl> 12032292SN/Avoid 12046221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12052292SN/A{ 12068607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12078607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12082292SN/A 12098607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedLSQ) 12108607Sgblack@eecs.umich.edu freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 12112292SN/A 12122292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12132292SN/A freeEntries[tid].robEntries = 12142292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12152292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12162292SN/A } 12172292SN/A 12182292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12192292SN/A tid, 12202292SN/A freeEntries[tid].iqEntries, 12212292SN/A freeEntries[tid].robEntries, 12222292SN/A freeEntries[tid].lsqEntries); 12232292SN/A 12242292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12252292SN/A tid, instsInProgress[tid]); 12262292SN/A} 12272292SN/A 12282292SN/Atemplate <class Impl> 12292292SN/Abool 12306221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12312292SN/A{ 12322292SN/A // Check if there's a squash signal, squash if there is 12332292SN/A // Check stall signals, block if necessary. 12342292SN/A // If status was blocked 12352292SN/A // check if stall conditions have passed 12362292SN/A // if so then go to unblocking 12372292SN/A // If status was Squashing 12382292SN/A // check if squashing is not high. Switch to running this cycle. 12392301SN/A // If status was serialize stall 12402292SN/A // check if ROB is empty and no insts are in flight to the ROB 12412292SN/A 12422292SN/A readFreeEntries(tid); 12432292SN/A readStallSignals(tid); 12442292SN/A 12452292SN/A if (fromCommit->commitInfo[tid].squash) { 12462292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12472292SN/A "commit.\n", tid); 12482292SN/A 12494632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12502292SN/A 12512292SN/A return true; 12522292SN/A } 12532292SN/A 12542292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12552292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12562292SN/A 12572292SN/A renameStatus[tid] = Squashing; 12582292SN/A 12592292SN/A return true; 12602292SN/A } 12612292SN/A 12622292SN/A if (checkStall(tid)) { 12632292SN/A return block(tid); 12642292SN/A } 12652292SN/A 12662292SN/A if (renameStatus[tid] == Blocked) { 12672292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12682292SN/A tid); 12692292SN/A 12702292SN/A renameStatus[tid] = Unblocking; 12712292SN/A 12722292SN/A unblock(tid); 12732292SN/A 12742292SN/A return true; 12752292SN/A } 12762292SN/A 12772292SN/A if (renameStatus[tid] == Squashing) { 12782292SN/A // Switch status to running if rename isn't being told to block or 12792292SN/A // squash this cycle. 12803798Sgblack@eecs.umich.edu if (resumeSerialize) { 12813798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12823798Sgblack@eecs.umich.edu tid); 12832292SN/A 12843798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12853798Sgblack@eecs.umich.edu return true; 12863798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12873798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12883798Sgblack@eecs.umich.edu tid); 12893798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12903798Sgblack@eecs.umich.edu return true; 12913798Sgblack@eecs.umich.edu } else { 12923788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12933788Sgblack@eecs.umich.edu tid); 12942292SN/A 12953788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12963788Sgblack@eecs.umich.edu return false; 12973788Sgblack@eecs.umich.edu } 12982292SN/A } 12992292SN/A 13002301SN/A if (renameStatus[tid] == SerializeStall) { 13012292SN/A // Stall ends once the ROB is free. 13022301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13032292SN/A "unblocking.\n", tid); 13042292SN/A 13052301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13062292SN/A 13072292SN/A renameStatus[tid] = Unblocking; 13082292SN/A 13092292SN/A unblock(tid); 13102292SN/A 13112292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13127720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13132292SN/A 13142292SN/A // Put instruction into queue here. 13152301SN/A serial_inst->clearSerializeBefore(); 13162292SN/A 13172292SN/A if (!skidBuffer[tid].empty()) { 13182301SN/A skidBuffer[tid].push_front(serial_inst); 13192292SN/A } else { 13202301SN/A insts[tid].push_front(serial_inst); 13212292SN/A } 13222292SN/A 13232292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13242703Sktlim@umich.edu " Adding to front of list.\n", tid); 13252292SN/A 13262301SN/A serializeInst[tid] = NULL; 13272292SN/A 13282292SN/A return true; 13292292SN/A } 13302292SN/A 13312292SN/A // If we've reached this point, we have not gotten any signals that 13322292SN/A // cause rename to change its status. Rename remains the same as before. 13332292SN/A return false; 13341061SN/A} 13351061SN/A 13361060SN/Atemplate<class Impl> 13371060SN/Avoid 13386221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13391060SN/A{ 13402292SN/A if (inst_list.empty()) { 13412292SN/A // Mark a bit to say that I must serialize on the next instruction. 13422292SN/A serializeOnNextInst[tid] = true; 13431060SN/A return; 13441060SN/A } 13451060SN/A 13462292SN/A // Set the next instruction as serializing. 13472292SN/A inst_list.front()->setSerializeBefore(); 13482292SN/A} 13492292SN/A 13502292SN/Atemplate <class Impl> 13512292SN/Ainline void 13522292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13532292SN/A{ 13542292SN/A switch (source) { 13552292SN/A case ROB: 13562292SN/A ++renameROBFullEvents; 13572292SN/A break; 13582292SN/A case IQ: 13592292SN/A ++renameIQFullEvents; 13602292SN/A break; 13612292SN/A case LSQ: 13622292SN/A ++renameLSQFullEvents; 13632292SN/A break; 13642292SN/A default: 13652292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13662292SN/A break; 13671060SN/A } 13682292SN/A} 13691060SN/A 13702292SN/Atemplate <class Impl> 13712292SN/Avoid 13722292SN/ADefaultRename<Impl>::dumpHistory() 13732292SN/A{ 13742980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13751060SN/A 13766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13771060SN/A 13786221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13791060SN/A 13806221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13812292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13822292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13832292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13841060SN/A 13852292SN/A buf_it++; 13861062SN/A } 13871060SN/A } 13881060SN/A} 1389