rename_impl.hh revision 9531
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 37854SAli.Saidi@ARM.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412935Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 441060SN/A#include <list> 451060SN/A 463773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476329Sgblack@eecs.umich.edu#include "arch/registers.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 491717SN/A#include "cpu/o3/rename.hh" 508232Snate@binkert.org#include "debug/Activity.hh" 518232Snate@binkert.org#include "debug/Rename.hh" 529527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 535529Snate@binkert.org#include "params/DerivO3CPU.hh" 541060SN/A 556221Snate@binkert.orgusing namespace std; 566221Snate@binkert.org 571061SN/Atemplate <class Impl> 585529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 594329Sktlim@umich.edu : cpu(_cpu), 604329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 612292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 622292SN/A commitToRenameDelay(params->commitToRenameDelay), 632292SN/A renameWidth(params->renameWidth), 642292SN/A commitWidth(params->commitWidth), 655529Snate@binkert.org numThreads(params->numThreads), 662361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 671060SN/A{ 682292SN/A // @todo: Make into a parameter. 698907Slukefahr@umich.edu skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 702292SN/A} 712292SN/A 722292SN/Atemplate <class Impl> 732292SN/Astd::string 742292SN/ADefaultRename<Impl>::name() const 752292SN/A{ 762292SN/A return cpu->name() + ".rename"; 771060SN/A} 781060SN/A 791061SN/Atemplate <class Impl> 801060SN/Avoid 812292SN/ADefaultRename<Impl>::regStats() 821062SN/A{ 831062SN/A renameSquashCycles 848240Snate@binkert.org .name(name() + ".SquashCycles") 851062SN/A .desc("Number of cycles rename is squashing") 861062SN/A .prereq(renameSquashCycles); 871062SN/A renameIdleCycles 888240Snate@binkert.org .name(name() + ".IdleCycles") 891062SN/A .desc("Number of cycles rename is idle") 901062SN/A .prereq(renameIdleCycles); 911062SN/A renameBlockCycles 928240Snate@binkert.org .name(name() + ".BlockCycles") 931062SN/A .desc("Number of cycles rename is blocking") 941062SN/A .prereq(renameBlockCycles); 952301SN/A renameSerializeStallCycles 968240Snate@binkert.org .name(name() + ".serializeStallCycles") 972301SN/A .desc("count of cycles rename stalled for serializing inst") 982301SN/A .flags(Stats::total); 992292SN/A renameRunCycles 1008240Snate@binkert.org .name(name() + ".RunCycles") 1012292SN/A .desc("Number of cycles rename is running") 1022292SN/A .prereq(renameIdleCycles); 1031062SN/A renameUnblockCycles 1048240Snate@binkert.org .name(name() + ".UnblockCycles") 1051062SN/A .desc("Number of cycles rename is unblocking") 1061062SN/A .prereq(renameUnblockCycles); 1071062SN/A renameRenamedInsts 1088240Snate@binkert.org .name(name() + ".RenamedInsts") 1091062SN/A .desc("Number of instructions processed by rename") 1101062SN/A .prereq(renameRenamedInsts); 1111062SN/A renameSquashedInsts 1128240Snate@binkert.org .name(name() + ".SquashedInsts") 1131062SN/A .desc("Number of squashed instructions processed by rename") 1141062SN/A .prereq(renameSquashedInsts); 1151062SN/A renameROBFullEvents 1168240Snate@binkert.org .name(name() + ".ROBFullEvents") 1172292SN/A .desc("Number of times rename has blocked due to ROB full") 1181062SN/A .prereq(renameROBFullEvents); 1191062SN/A renameIQFullEvents 1208240Snate@binkert.org .name(name() + ".IQFullEvents") 1212292SN/A .desc("Number of times rename has blocked due to IQ full") 1221062SN/A .prereq(renameIQFullEvents); 1232292SN/A renameLSQFullEvents 1248240Snate@binkert.org .name(name() + ".LSQFullEvents") 1252292SN/A .desc("Number of times rename has blocked due to LSQ full") 1262292SN/A .prereq(renameLSQFullEvents); 1271062SN/A renameFullRegistersEvents 1288240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1291062SN/A .desc("Number of times there has been no free registers") 1301062SN/A .prereq(renameFullRegistersEvents); 1311062SN/A renameRenamedOperands 1328240Snate@binkert.org .name(name() + ".RenamedOperands") 1331062SN/A .desc("Number of destination operands rename has renamed") 1341062SN/A .prereq(renameRenamedOperands); 1351062SN/A renameRenameLookups 1368240Snate@binkert.org .name(name() + ".RenameLookups") 1371062SN/A .desc("Number of register rename lookups that rename has made") 1381062SN/A .prereq(renameRenameLookups); 1391062SN/A renameCommittedMaps 1408240Snate@binkert.org .name(name() + ".CommittedMaps") 1411062SN/A .desc("Number of HB maps that are committed") 1421062SN/A .prereq(renameCommittedMaps); 1431062SN/A renameUndoneMaps 1448240Snate@binkert.org .name(name() + ".UndoneMaps") 1451062SN/A .desc("Number of HB maps that are undone due to squashing") 1461062SN/A .prereq(renameUndoneMaps); 1472301SN/A renamedSerializing 1488240Snate@binkert.org .name(name() + ".serializingInsts") 1492301SN/A .desc("count of serializing insts renamed") 1502301SN/A .flags(Stats::total) 1512301SN/A ; 1522301SN/A renamedTempSerializing 1538240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1542301SN/A .desc("count of temporary serializing insts renamed") 1552301SN/A .flags(Stats::total) 1562301SN/A ; 1572307SN/A renameSkidInsts 1588240Snate@binkert.org .name(name() + ".skidInsts") 1592307SN/A .desc("count of insts added to the skid buffer") 1602307SN/A .flags(Stats::total) 1612307SN/A ; 1627897Shestness@cs.utexas.edu intRenameLookups 1638240Snate@binkert.org .name(name() + ".int_rename_lookups") 1647897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1657897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1667897Shestness@cs.utexas.edu fpRenameLookups 1678240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1687897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1697897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1701062SN/A} 1711062SN/A 1721062SN/Atemplate <class Impl> 1731062SN/Avoid 1742292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1751060SN/A{ 1761060SN/A timeBuffer = tb_ptr; 1771060SN/A 1781060SN/A // Setup wire to read information from time buffer, from IEW stage. 1791060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1821060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1831060SN/A 1841060SN/A // Setup wire to write information to previous stages. 1851060SN/A toDecode = timeBuffer->getWire(0); 1861060SN/A} 1871060SN/A 1881061SN/Atemplate <class Impl> 1891060SN/Avoid 1902292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1911060SN/A{ 1921060SN/A renameQueue = rq_ptr; 1931060SN/A 1941060SN/A // Setup wire to write information to future stages. 1951060SN/A toIEW = renameQueue->getWire(0); 1961060SN/A} 1971060SN/A 1981061SN/Atemplate <class Impl> 1991060SN/Avoid 2002292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2011060SN/A{ 2021060SN/A decodeQueue = dq_ptr; 2031060SN/A 2041060SN/A // Setup wire to get information from decode. 2051060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2061060SN/A} 2071060SN/A 2081061SN/Atemplate <class Impl> 2091060SN/Avoid 2109427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2111060SN/A{ 2129444SAndreas.Sandberg@ARM.com resetStage(); 2139444SAndreas.Sandberg@ARM.com} 2149444SAndreas.Sandberg@ARM.com 2159444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2169444SAndreas.Sandberg@ARM.comvoid 2179444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2189444SAndreas.Sandberg@ARM.com{ 2199444SAndreas.Sandberg@ARM.com _status = Inactive; 2209444SAndreas.Sandberg@ARM.com 2219444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2229444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2239444SAndreas.Sandberg@ARM.com 2242329SN/A // Grab the number of free entries directly from the stages. 2256221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2269444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2279444SAndreas.Sandberg@ARM.com 2282292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2292292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2302292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2312292SN/A emptyROB[tid] = true; 2329444SAndreas.Sandberg@ARM.com 2339444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2349444SAndreas.Sandberg@ARM.com stalls[tid].commit = false; 2359444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2369444SAndreas.Sandberg@ARM.com 2379444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 2389444SAndreas.Sandberg@ARM.com 2399444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2402292SN/A } 2411060SN/A} 2421060SN/A 2432292SN/Atemplate<class Impl> 2442292SN/Avoid 2456221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2462292SN/A{ 2472292SN/A activeThreads = at_ptr; 2482292SN/A} 2492292SN/A 2502292SN/A 2511061SN/Atemplate <class Impl> 2521060SN/Avoid 2532292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2541060SN/A{ 2556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2566221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2571060SN/A} 2581060SN/A 2591061SN/Atemplate <class Impl> 2601060SN/Avoid 2612292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2621060SN/A{ 2632292SN/A freeList = fl_ptr; 2642292SN/A} 2651060SN/A 2662292SN/Atemplate<class Impl> 2672292SN/Avoid 2682292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2692292SN/A{ 2702292SN/A scoreboard = _scoreboard; 2711060SN/A} 2721060SN/A 2731061SN/Atemplate <class Impl> 2742863Sktlim@umich.edubool 2759444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 2761060SN/A{ 2779444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2789444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 2799444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 2809444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 2819444SAndreas.Sandberg@ARM.com !insts[tid].empty()) 2829444SAndreas.Sandberg@ARM.com return false; 2839444SAndreas.Sandberg@ARM.com } 2842863Sktlim@umich.edu return true; 2852316SN/A} 2861060SN/A 2872316SN/Atemplate <class Impl> 2882316SN/Avoid 2892307SN/ADefaultRename<Impl>::takeOverFrom() 2901060SN/A{ 2919444SAndreas.Sandberg@ARM.com resetStage(); 2929444SAndreas.Sandberg@ARM.com} 2931060SN/A 2949444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2959444SAndreas.Sandberg@ARM.comvoid 2969444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 2979444SAndreas.Sandberg@ARM.com{ 2986221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2999444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3009444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3019444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3029444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3032307SN/A } 3042307SN/A} 3052307SN/A 3062307SN/Atemplate <class Impl> 3072307SN/Avoid 3086221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3091858SN/A{ 3102292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3111858SN/A 3122292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3132292SN/A // If it still needs to block, the blocking should happen the next 3142292SN/A // cycle and there should be space to hold everything due to the squash. 3152292SN/A if (renameStatus[tid] == Blocked || 3163788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3172292SN/A toDecode->renameUnblock[tid] = 1; 3182698Sktlim@umich.edu 3193788Sgblack@eecs.umich.edu resumeSerialize = false; 3202301SN/A serializeInst[tid] = NULL; 3213788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3223788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3233788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3243788Sgblack@eecs.umich.edu resumeSerialize = true; 3253788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3263788Sgblack@eecs.umich.edu } else { 3273788Sgblack@eecs.umich.edu resumeSerialize = false; 3283788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3293788Sgblack@eecs.umich.edu 3303788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3313788Sgblack@eecs.umich.edu } 3322292SN/A } 3332292SN/A 3342292SN/A // Set the status to Squashing. 3352292SN/A renameStatus[tid] = Squashing; 3362292SN/A 3372329SN/A // Squash any instructions from decode. 3382292SN/A unsigned squashCount = 0; 3392292SN/A 3402292SN/A for (int i=0; i<fromDecode->size; i++) { 3412935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3422935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3432731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3442292SN/A wroteToTimeBuffer = true; 3452292SN/A squashCount++; 3462292SN/A } 3472935Sksewell@umich.edu 3482292SN/A } 3492292SN/A 3502935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3514632Sgblack@eecs.umich.edu // insts in them. 3523093Sksewell@umich.edu insts[tid].clear(); 3532292SN/A 3542292SN/A // Clear the skid buffer in case it has any data in it. 3553093Sksewell@umich.edu skidBuffer[tid].clear(); 3564632Sgblack@eecs.umich.edu 3572935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3582292SN/A} 3592292SN/A 3602292SN/Atemplate <class Impl> 3612292SN/Avoid 3622292SN/ADefaultRename<Impl>::tick() 3632292SN/A{ 3642292SN/A wroteToTimeBuffer = false; 3652292SN/A 3662292SN/A blockThisCycle = false; 3672292SN/A 3682292SN/A bool status_change = false; 3692292SN/A 3702292SN/A toIEWIndex = 0; 3712292SN/A 3722292SN/A sortInsts(); 3732292SN/A 3746221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3756221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3762292SN/A 3772292SN/A // Check stall and squash signals. 3783867Sbinkertn@umich.edu while (threads != end) { 3796221Snate@binkert.org ThreadID tid = *threads++; 3802292SN/A 3812292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3822292SN/A 3832292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3842292SN/A 3852292SN/A rename(status_change, tid); 3862292SN/A } 3872292SN/A 3882292SN/A if (status_change) { 3892292SN/A updateStatus(); 3902292SN/A } 3912292SN/A 3922292SN/A if (wroteToTimeBuffer) { 3932292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 3942292SN/A cpu->activityThisCycle(); 3952292SN/A } 3962292SN/A 3973867Sbinkertn@umich.edu threads = activeThreads->begin(); 3982292SN/A 3993867Sbinkertn@umich.edu while (threads != end) { 4006221Snate@binkert.org ThreadID tid = *threads++; 4012292SN/A 4022292SN/A // If we committed this cycle then doneSeqNum will be > 0 4032292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4042292SN/A !fromCommit->commitInfo[tid].squash && 4052292SN/A renameStatus[tid] != Squashing) { 4062292SN/A 4072292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4082292SN/A tid); 4092292SN/A } 4102292SN/A } 4112292SN/A 4122292SN/A // @todo: make into updateProgress function 4136221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4142292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4152292SN/A 4162292SN/A assert(instsInProgress[tid] >=0); 4172292SN/A } 4182292SN/A 4192292SN/A} 4202292SN/A 4212292SN/Atemplate<class Impl> 4222292SN/Avoid 4236221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4242292SN/A{ 4252292SN/A // If status is Running or idle, 4262292SN/A // call renameInsts() 4272292SN/A // If status is Unblocking, 4282292SN/A // buffer any instructions coming from decode 4292292SN/A // continue trying to empty skid buffer 4302292SN/A // check if stall conditions have passed 4312292SN/A 4322292SN/A if (renameStatus[tid] == Blocked) { 4332292SN/A ++renameBlockCycles; 4342292SN/A } else if (renameStatus[tid] == Squashing) { 4352292SN/A ++renameSquashCycles; 4362301SN/A } else if (renameStatus[tid] == SerializeStall) { 4372301SN/A ++renameSerializeStallCycles; 4383788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4393788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4403788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4413788Sgblack@eecs.umich.edu if (resumeSerialize) { 4423788Sgblack@eecs.umich.edu resumeSerialize = false; 4433788Sgblack@eecs.umich.edu block(tid); 4443788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4453788Sgblack@eecs.umich.edu } 4463798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4473798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4483798Sgblack@eecs.umich.edu block(tid); 4493798Sgblack@eecs.umich.edu resumeUnblocking = false; 4503798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4513798Sgblack@eecs.umich.edu } 4522292SN/A } 4532292SN/A 4542292SN/A if (renameStatus[tid] == Running || 4552292SN/A renameStatus[tid] == Idle) { 4562292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4572292SN/A "stage.\n", tid); 4582292SN/A 4592292SN/A renameInsts(tid); 4602292SN/A } else if (renameStatus[tid] == Unblocking) { 4612292SN/A renameInsts(tid); 4622292SN/A 4632292SN/A if (validInsts()) { 4642292SN/A // Add the current inputs to the skid buffer so they can be 4652292SN/A // reprocessed when this stage unblocks. 4662292SN/A skidInsert(tid); 4672292SN/A } 4682292SN/A 4692292SN/A // If we switched over to blocking, then there's a potential for 4702292SN/A // an overall status change. 4712292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4721858SN/A } 4731858SN/A} 4741858SN/A 4751858SN/Atemplate <class Impl> 4761858SN/Avoid 4776221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4781858SN/A{ 4792292SN/A // Instructions can be either in the skid buffer or the queue of 4802292SN/A // instructions coming from decode, depending on the status. 4812292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4822292SN/A skidBuffer[tid].size() : insts[tid].size(); 4831858SN/A 4842292SN/A // Check the decode queue to see if instructions are available. 4852292SN/A // If there are no available instructions to rename, then do nothing. 4862292SN/A if (insts_available == 0) { 4872292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4882292SN/A tid); 4892292SN/A // Should I change status to idle? 4902292SN/A ++renameIdleCycles; 4912292SN/A return; 4922292SN/A } else if (renameStatus[tid] == Unblocking) { 4932292SN/A ++renameUnblockCycles; 4942292SN/A } else if (renameStatus[tid] == Running) { 4952292SN/A ++renameRunCycles; 4962292SN/A } 4971858SN/A 4982292SN/A DynInstPtr inst; 4992292SN/A 5002292SN/A // Will have to do a different calculation for the number of free 5012292SN/A // entries. 5022292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5032292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5042292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5052292SN/A int min_free_entries = free_rob_entries; 5062292SN/A 5072292SN/A FullSource source = ROB; 5082292SN/A 5092292SN/A if (free_iq_entries < min_free_entries) { 5102292SN/A min_free_entries = free_iq_entries; 5112292SN/A source = IQ; 5122292SN/A } 5132292SN/A 5142292SN/A if (free_lsq_entries < min_free_entries) { 5152292SN/A min_free_entries = free_lsq_entries; 5162292SN/A source = LSQ; 5172292SN/A } 5182292SN/A 5192292SN/A // Check if there's any space left. 5202292SN/A if (min_free_entries <= 0) { 5212292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5222292SN/A "entries.\n" 5232292SN/A "ROB has %i free entries.\n" 5242292SN/A "IQ has %i free entries.\n" 5252292SN/A "LSQ has %i free entries.\n", 5262292SN/A tid, 5272292SN/A free_rob_entries, 5282292SN/A free_iq_entries, 5292292SN/A free_lsq_entries); 5302292SN/A 5312292SN/A blockThisCycle = true; 5322292SN/A 5332292SN/A block(tid); 5342292SN/A 5352292SN/A incrFullStat(source); 5362292SN/A 5372292SN/A return; 5382292SN/A } else if (min_free_entries < insts_available) { 5392292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5402292SN/A "%i insts available, but only %i insts can be " 5412292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5422292SN/A tid, insts_available, min_free_entries); 5432292SN/A 5442292SN/A insts_available = min_free_entries; 5452292SN/A 5462292SN/A blockThisCycle = true; 5472292SN/A 5482292SN/A incrFullStat(source); 5492292SN/A } 5502292SN/A 5512292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5522292SN/A skidBuffer[tid] : insts[tid]; 5532292SN/A 5542292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5552292SN/A "send iew.\n", tid, insts_available); 5562292SN/A 5572292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5582292SN/A "dispatched to IQ last cycle.\n", 5592292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5602292SN/A 5612292SN/A // Handle serializing the next instruction if necessary. 5622292SN/A if (serializeOnNextInst[tid]) { 5632292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5642292SN/A // ROB already empty; no need to serialize. 5652292SN/A serializeOnNextInst[tid] = false; 5662292SN/A } else if (!insts_to_rename.empty()) { 5672292SN/A insts_to_rename.front()->setSerializeBefore(); 5682292SN/A } 5692292SN/A } 5702292SN/A 5712292SN/A int renamed_insts = 0; 5722292SN/A 5732292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5742292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5752292SN/A 5762292SN/A assert(!insts_to_rename.empty()); 5772292SN/A 5782292SN/A inst = insts_to_rename.front(); 5792292SN/A 5802292SN/A insts_to_rename.pop_front(); 5812292SN/A 5822292SN/A if (renameStatus[tid] == Unblocking) { 5837720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 5847720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 5852292SN/A } 5862292SN/A 5872292SN/A if (inst->isSquashed()) { 5887720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 5897720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 5907720Sgblack@eecs.umich.edu inst->pcState()); 5912292SN/A 5922292SN/A ++renameSquashedInsts; 5932292SN/A 5942292SN/A // Decrement how many instructions are available. 5952292SN/A --insts_available; 5962292SN/A 5972292SN/A continue; 5982292SN/A } 5992292SN/A 6002292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6017720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6022292SN/A 6039531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6049531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 6059531Sgeoffrey.blake@arm.com if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6069531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6079531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6089531Sgeoffrey.blake@arm.com blockThisCycle = true; 6099531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6109531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6119531Sgeoffrey.blake@arm.com 6129531Sgeoffrey.blake@arm.com break; 6139531Sgeoffrey.blake@arm.com } 6149531Sgeoffrey.blake@arm.com 6152292SN/A // Handle serializeAfter/serializeBefore instructions. 6162292SN/A // serializeAfter marks the next instruction as serializeBefore. 6172292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6182292SN/A // is empty. 6192336SN/A 6202336SN/A // In this model, IPR accesses are serialize before 6212336SN/A // instructions, and store conditionals are serialize after 6222336SN/A // instructions. This is mainly due to lack of support for 6232336SN/A // out-of-order operations of either of those classes of 6242336SN/A // instructions. 6252336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6262336SN/A !inst->isSerializeHandled()) { 6272292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6282292SN/A 6292301SN/A if (!inst->isTempSerializeBefore()) { 6302301SN/A renamedSerializing++; 6312292SN/A inst->setSerializeHandled(); 6322301SN/A } else { 6332301SN/A renamedTempSerializing++; 6342301SN/A } 6352292SN/A 6362301SN/A // Change status over to SerializeStall so that other stages know 6372292SN/A // what this is blocked on. 6382301SN/A renameStatus[tid] = SerializeStall; 6392292SN/A 6402301SN/A serializeInst[tid] = inst; 6412292SN/A 6422292SN/A blockThisCycle = true; 6432292SN/A 6442292SN/A break; 6452336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6462336SN/A !inst->isSerializeHandled()) { 6472292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6482292SN/A 6492307SN/A renamedSerializing++; 6502307SN/A 6512292SN/A inst->setSerializeHandled(); 6522292SN/A 6532292SN/A serializeAfter(insts_to_rename, tid); 6542292SN/A } 6552292SN/A 6562292SN/A renameSrcRegs(inst, inst->threadNumber); 6572292SN/A 6582292SN/A renameDestRegs(inst, inst->threadNumber); 6592292SN/A 6602292SN/A ++renamed_insts; 6612292SN/A 6628471SGiacomo.Gabrielli@arm.com 6632292SN/A // Put instruction in rename queue. 6642292SN/A toIEW->insts[toIEWIndex] = inst; 6652292SN/A ++(toIEW->size); 6662292SN/A 6672292SN/A // Increment which instruction we're on. 6682292SN/A ++toIEWIndex; 6692292SN/A 6702292SN/A // Decrement how many instructions are available. 6712292SN/A --insts_available; 6722292SN/A } 6732292SN/A 6742292SN/A instsInProgress[tid] += renamed_insts; 6752307SN/A renameRenamedInsts += renamed_insts; 6762292SN/A 6772292SN/A // If we wrote to the time buffer, record this. 6782292SN/A if (toIEWIndex) { 6792292SN/A wroteToTimeBuffer = true; 6802292SN/A } 6812292SN/A 6822292SN/A // Check if there's any instructions left that haven't yet been renamed. 6832292SN/A // If so then block. 6842292SN/A if (insts_available) { 6852292SN/A blockThisCycle = true; 6862292SN/A } 6872292SN/A 6882292SN/A if (blockThisCycle) { 6892292SN/A block(tid); 6902292SN/A toDecode->renameUnblock[tid] = false; 6912292SN/A } 6922292SN/A} 6932292SN/A 6942292SN/Atemplate<class Impl> 6952292SN/Avoid 6966221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 6972292SN/A{ 6982292SN/A DynInstPtr inst = NULL; 6992292SN/A 7002292SN/A while (!insts[tid].empty()) { 7012292SN/A inst = insts[tid].front(); 7022292SN/A 7032292SN/A insts[tid].pop_front(); 7042292SN/A 7052292SN/A assert(tid == inst->threadNumber); 7062292SN/A 7077720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7087720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7092292SN/A 7102307SN/A ++renameSkidInsts; 7112307SN/A 7122292SN/A skidBuffer[tid].push_back(inst); 7132292SN/A } 7142292SN/A 7152292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7163798Sgblack@eecs.umich.edu { 7173798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7183798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7193798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7203798Sgblack@eecs.umich.edu { 7213798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7227720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7233798Sgblack@eecs.umich.edu (*it)->seqNum); 7243798Sgblack@eecs.umich.edu } 7252292SN/A panic("Skidbuffer Exceeded Max Size"); 7263798Sgblack@eecs.umich.edu } 7272292SN/A} 7282292SN/A 7292292SN/Atemplate <class Impl> 7302292SN/Avoid 7312292SN/ADefaultRename<Impl>::sortInsts() 7322292SN/A{ 7332292SN/A int insts_from_decode = fromDecode->size; 7342292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7352292SN/A DynInstPtr inst = fromDecode->insts[i]; 7362292SN/A insts[inst->threadNumber].push_back(inst); 7379527SMatt.Horsnell@arm.com#if TRACING_ON 7389527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7399527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7409527SMatt.Horsnell@arm.com } 7419527SMatt.Horsnell@arm.com#endif 7422292SN/A } 7432292SN/A} 7442292SN/A 7452292SN/Atemplate<class Impl> 7462292SN/Abool 7472292SN/ADefaultRename<Impl>::skidsEmpty() 7482292SN/A{ 7496221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7506221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7512292SN/A 7523867Sbinkertn@umich.edu while (threads != end) { 7536221Snate@binkert.org ThreadID tid = *threads++; 7543867Sbinkertn@umich.edu 7553867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7562292SN/A return false; 7572292SN/A } 7582292SN/A 7592292SN/A return true; 7602292SN/A} 7612292SN/A 7622292SN/Atemplate<class Impl> 7632292SN/Avoid 7642292SN/ADefaultRename<Impl>::updateStatus() 7652292SN/A{ 7662292SN/A bool any_unblocking = false; 7672292SN/A 7686221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7696221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7702292SN/A 7713867Sbinkertn@umich.edu while (threads != end) { 7726221Snate@binkert.org ThreadID tid = *threads++; 7732292SN/A 7742292SN/A if (renameStatus[tid] == Unblocking) { 7752292SN/A any_unblocking = true; 7762292SN/A break; 7772292SN/A } 7782292SN/A } 7792292SN/A 7802292SN/A // Rename will have activity if it's unblocking. 7812292SN/A if (any_unblocking) { 7822292SN/A if (_status == Inactive) { 7832292SN/A _status = Active; 7842292SN/A 7852292SN/A DPRINTF(Activity, "Activating stage.\n"); 7862292SN/A 7872733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7882292SN/A } 7892292SN/A } else { 7902292SN/A // If it's not unblocking, then rename will not have any internal 7912292SN/A // activity. Switch it to inactive. 7922292SN/A if (_status == Active) { 7932292SN/A _status = Inactive; 7942292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 7952292SN/A 7962733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 7972292SN/A } 7982292SN/A } 7992292SN/A} 8002292SN/A 8012292SN/Atemplate <class Impl> 8022292SN/Abool 8036221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8042292SN/A{ 8052292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8062292SN/A 8072292SN/A // Add the current inputs onto the skid buffer, so they can be 8082292SN/A // reprocessed when this stage unblocks. 8092292SN/A skidInsert(tid); 8102292SN/A 8112292SN/A // Only signal backwards to block if the previous stages do not think 8122292SN/A // rename is already blocked. 8132292SN/A if (renameStatus[tid] != Blocked) { 8143798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8153798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8163798Sgblack@eecs.umich.edu // stages to block. 8173798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8182292SN/A toDecode->renameBlock[tid] = true; 8192292SN/A toDecode->renameUnblock[tid] = false; 8202292SN/A wroteToTimeBuffer = true; 8212292SN/A } 8222292SN/A 8232329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8242329SN/A // it would not know to complete the serialize stall. 8252301SN/A if (renameStatus[tid] != SerializeStall) { 8262292SN/A // Set status to Blocked. 8272292SN/A renameStatus[tid] = Blocked; 8282292SN/A return true; 8292292SN/A } 8302292SN/A } 8312292SN/A 8322292SN/A return false; 8332292SN/A} 8342292SN/A 8352292SN/Atemplate <class Impl> 8362292SN/Abool 8376221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8382292SN/A{ 8392292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8402292SN/A 8412292SN/A // Rename is done unblocking if the skid buffer is empty. 8422301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8432292SN/A 8442292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8452292SN/A 8462292SN/A toDecode->renameUnblock[tid] = true; 8472292SN/A wroteToTimeBuffer = true; 8482292SN/A 8492292SN/A renameStatus[tid] = Running; 8502292SN/A return true; 8512292SN/A } 8522292SN/A 8532292SN/A return false; 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Avoid 8586221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8592292SN/A{ 8602980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8612980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8622292SN/A 8631060SN/A // After a syscall squashes everything, the history buffer may be empty 8641060SN/A // but the ROB may still be squashing instructions. 8652292SN/A if (historyBuffer[tid].empty()) { 8661060SN/A return; 8671060SN/A } 8681060SN/A 8691060SN/A // Go through the most recent instructions, undoing the mappings 8701060SN/A // they did and freeing up the registers. 8712292SN/A while (!historyBuffer[tid].empty() && 8722292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8732292SN/A assert(hb_it != historyBuffer[tid].end()); 8741062SN/A 8752292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8762292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8771060SN/A 8782292SN/A // Tell the rename map to set the architected register to the 8792292SN/A // previous physical register that it was renamed to. 8802292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8811060SN/A 8822292SN/A // Put the renamed physical register back on the free list. 8832292SN/A freeList->addReg(hb_it->newPhysReg); 8841062SN/A 8852367SN/A // Be sure to mark its register as ready if it's a misc register. 8862367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 8872367SN/A scoreboard->setReg(hb_it->newPhysReg); 8882367SN/A } 8892367SN/A 8902292SN/A historyBuffer[tid].erase(hb_it++); 8911061SN/A 8921062SN/A ++renameUndoneMaps; 8931060SN/A } 8941060SN/A} 8951060SN/A 8961060SN/Atemplate<class Impl> 8971060SN/Avoid 8986221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 8991060SN/A{ 9002292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9012292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9022292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9032292SN/A 9042980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9052980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9061060SN/A 9071061SN/A --hb_it; 9081060SN/A 9092292SN/A if (historyBuffer[tid].empty()) { 9102292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9112292SN/A return; 9122292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9132292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9142292SN/A "that a syscall happened recently.\n", tid); 9151060SN/A return; 9161060SN/A } 9171060SN/A 9182292SN/A // Commit all the renames up until (and including) the committed sequence 9192292SN/A // number. Some or even all of the committed instructions may not have 9202292SN/A // rename histories if they did not have destination registers that were 9212292SN/A // renamed. 9222292SN/A while (!historyBuffer[tid].empty() && 9232292SN/A hb_it != historyBuffer[tid].end() && 9242292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9251060SN/A 9262329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9272329SN/A "[sn:%lli].\n", 9282292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9291061SN/A 9302292SN/A freeList->addReg((*hb_it).prevPhysReg); 9312292SN/A ++renameCommittedMaps; 9321061SN/A 9332292SN/A historyBuffer[tid].erase(hb_it--); 9341060SN/A } 9351060SN/A} 9361060SN/A 9371061SN/Atemplate <class Impl> 9381061SN/Ainline void 9396221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9401061SN/A{ 9412292SN/A assert(renameMap[tid] != 0); 9422292SN/A 9431061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9441061SN/A 9451061SN/A // Get the architectual register numbers from the source and 9461061SN/A // destination operands, and redirect them to the right register. 9471061SN/A // Will need to mark dependencies though. 9482292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9491061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9503773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9513773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9526313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9537767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9547767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9555082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9565082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9576313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9587767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9597767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9605082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9617649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9627767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9637767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9647767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 9657767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 9667649Sminkyu.jeong@arm.com } else { 9677649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9683773Sgblack@eecs.umich.edu } 9694352Sgblack@eecs.umich.edu 9701061SN/A // Look up the source registers to get the phys. register they've 9711061SN/A // been renamed to, and set the sources to those registers. 9723773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9731061SN/A 9742292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9753773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9762292SN/A (int)renamed_reg); 9771061SN/A 9781061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9791061SN/A 9802292SN/A // See if the register is ready or not. 9812292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9827767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 9837767Sgblack@eecs.umich.edu tid, renamed_reg); 9841061SN/A 9851061SN/A inst->markSrcRegReady(src_idx); 9864636Sgblack@eecs.umich.edu } else { 9877767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 9887767Sgblack@eecs.umich.edu tid, renamed_reg); 9891061SN/A } 9901062SN/A 9911062SN/A ++renameRenameLookups; 9927897Shestness@cs.utexas.edu inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 9931061SN/A } 9941061SN/A} 9951061SN/A 9961061SN/Atemplate <class Impl> 9971061SN/Ainline void 9986221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 9991061SN/A{ 10002292SN/A typename RenameMap::RenameInfo rename_result; 10011061SN/A 10021061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10031061SN/A 10042292SN/A // Rename the destination registers. 10052292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10062292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10073773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10083773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10094352Sgblack@eecs.umich.edu // Integer registers are flattened. 10106313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10117767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10127767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10137767Sgblack@eecs.umich.edu } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 10147767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10157767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10167767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10177767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10187767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10197649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10204352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10214352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10227767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10237767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10247767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10257767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10267649Sminkyu.jeong@arm.com } else { 10277649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10283773Sgblack@eecs.umich.edu } 10293773Sgblack@eecs.umich.edu 10303773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10311061SN/A 10322292SN/A // Get the physical register that the destination will be 10332292SN/A // renamed to. 10343773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10351061SN/A 10362292SN/A //Mark Scoreboard entry as not ready 10377854SAli.Saidi@ARM.com if (dest_reg < TheISA::Ctrl_Base_DepTag) 10387854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10391062SN/A 10402292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10413773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10422292SN/A (int)rename_result.first); 10431062SN/A 10442292SN/A // Record the rename information so that a history can be kept. 10453773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10462292SN/A rename_result.first, 10472292SN/A rename_result.second); 10481062SN/A 10492292SN/A historyBuffer[tid].push_front(hb_entry); 10501062SN/A 10512935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10522935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10532935Sksewell@umich.edu historyBuffer[tid].size(), 10542292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10551062SN/A 10562292SN/A // Tell the instruction to rename the appropriate destination 10572292SN/A // register (dest_idx) to the new physical register 10582292SN/A // (rename_result.first), and record the previous physical 10592292SN/A // register that the same logical register was renamed to 10602292SN/A // (rename_result.second). 10612292SN/A inst->renameDestReg(dest_idx, 10622292SN/A rename_result.first, 10632292SN/A rename_result.second); 10641062SN/A 10652292SN/A ++renameRenamedOperands; 10661061SN/A } 10671061SN/A} 10681061SN/A 10691061SN/Atemplate <class Impl> 10701061SN/Ainline int 10716221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 10721061SN/A{ 10732292SN/A int num_free = freeEntries[tid].robEntries - 10742292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10752292SN/A 10762292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10772292SN/A 10782292SN/A return num_free; 10791061SN/A} 10801061SN/A 10811061SN/Atemplate <class Impl> 10821061SN/Ainline int 10836221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 10841061SN/A{ 10852292SN/A int num_free = freeEntries[tid].iqEntries - 10862292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10872292SN/A 10882292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10892292SN/A 10902292SN/A return num_free; 10912292SN/A} 10922292SN/A 10932292SN/Atemplate <class Impl> 10942292SN/Ainline int 10956221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 10962292SN/A{ 10972292SN/A int num_free = freeEntries[tid].lsqEntries - 10982292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10992292SN/A 11002292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11012292SN/A 11022292SN/A return num_free; 11032292SN/A} 11042292SN/A 11052292SN/Atemplate <class Impl> 11062292SN/Aunsigned 11072292SN/ADefaultRename<Impl>::validInsts() 11082292SN/A{ 11092292SN/A unsigned inst_count = 0; 11102292SN/A 11112292SN/A for (int i=0; i<fromDecode->size; i++) { 11122731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11132292SN/A inst_count++; 11142292SN/A } 11152292SN/A 11162292SN/A return inst_count; 11172292SN/A} 11182292SN/A 11192292SN/Atemplate <class Impl> 11202292SN/Avoid 11216221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11222292SN/A{ 11232292SN/A if (fromIEW->iewBlock[tid]) { 11242292SN/A stalls[tid].iew = true; 11252292SN/A } 11262292SN/A 11272292SN/A if (fromIEW->iewUnblock[tid]) { 11282292SN/A assert(stalls[tid].iew); 11292292SN/A stalls[tid].iew = false; 11302292SN/A } 11312292SN/A 11322292SN/A if (fromCommit->commitBlock[tid]) { 11332292SN/A stalls[tid].commit = true; 11342292SN/A } 11352292SN/A 11362292SN/A if (fromCommit->commitUnblock[tid]) { 11372292SN/A assert(stalls[tid].commit); 11382292SN/A stalls[tid].commit = false; 11392292SN/A } 11402292SN/A} 11412292SN/A 11422292SN/Atemplate <class Impl> 11432292SN/Abool 11446221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11452292SN/A{ 11462292SN/A bool ret_val = false; 11472292SN/A 11482292SN/A if (stalls[tid].iew) { 11492292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11502292SN/A ret_val = true; 11512292SN/A } else if (stalls[tid].commit) { 11522292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11532292SN/A ret_val = true; 11542292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11552292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11562292SN/A ret_val = true; 11572292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11582292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11592292SN/A ret_val = true; 11602292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11612292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11622292SN/A ret_val = true; 11632292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11642292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11652292SN/A ret_val = true; 11662301SN/A } else if (renameStatus[tid] == SerializeStall && 11672292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11682301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11692292SN/A "empty.\n", 11702292SN/A tid); 11712292SN/A ret_val = true; 11722292SN/A } 11732292SN/A 11742292SN/A return ret_val; 11752292SN/A} 11762292SN/A 11772292SN/Atemplate <class Impl> 11782292SN/Avoid 11796221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 11802292SN/A{ 11818607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 11828607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 11832292SN/A 11848607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedLSQ) 11858607Sgblack@eecs.umich.edu freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 11862292SN/A 11872292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11882292SN/A freeEntries[tid].robEntries = 11892292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11902292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11912292SN/A } 11922292SN/A 11932292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11942292SN/A tid, 11952292SN/A freeEntries[tid].iqEntries, 11962292SN/A freeEntries[tid].robEntries, 11972292SN/A freeEntries[tid].lsqEntries); 11982292SN/A 11992292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12002292SN/A tid, instsInProgress[tid]); 12012292SN/A} 12022292SN/A 12032292SN/Atemplate <class Impl> 12042292SN/Abool 12056221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12062292SN/A{ 12072292SN/A // Check if there's a squash signal, squash if there is 12082292SN/A // Check stall signals, block if necessary. 12092292SN/A // If status was blocked 12102292SN/A // check if stall conditions have passed 12112292SN/A // if so then go to unblocking 12122292SN/A // If status was Squashing 12132292SN/A // check if squashing is not high. Switch to running this cycle. 12142301SN/A // If status was serialize stall 12152292SN/A // check if ROB is empty and no insts are in flight to the ROB 12162292SN/A 12172292SN/A readFreeEntries(tid); 12182292SN/A readStallSignals(tid); 12192292SN/A 12202292SN/A if (fromCommit->commitInfo[tid].squash) { 12212292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12222292SN/A "commit.\n", tid); 12232292SN/A 12244632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12252292SN/A 12262292SN/A return true; 12272292SN/A } 12282292SN/A 12292292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12302292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12312292SN/A 12322292SN/A renameStatus[tid] = Squashing; 12332292SN/A 12342292SN/A return true; 12352292SN/A } 12362292SN/A 12372292SN/A if (checkStall(tid)) { 12382292SN/A return block(tid); 12392292SN/A } 12402292SN/A 12412292SN/A if (renameStatus[tid] == Blocked) { 12422292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12432292SN/A tid); 12442292SN/A 12452292SN/A renameStatus[tid] = Unblocking; 12462292SN/A 12472292SN/A unblock(tid); 12482292SN/A 12492292SN/A return true; 12502292SN/A } 12512292SN/A 12522292SN/A if (renameStatus[tid] == Squashing) { 12532292SN/A // Switch status to running if rename isn't being told to block or 12542292SN/A // squash this cycle. 12553798Sgblack@eecs.umich.edu if (resumeSerialize) { 12563798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12573798Sgblack@eecs.umich.edu tid); 12582292SN/A 12593798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12603798Sgblack@eecs.umich.edu return true; 12613798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12623798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12633798Sgblack@eecs.umich.edu tid); 12643798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12653798Sgblack@eecs.umich.edu return true; 12663798Sgblack@eecs.umich.edu } else { 12673788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12683788Sgblack@eecs.umich.edu tid); 12692292SN/A 12703788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 12713788Sgblack@eecs.umich.edu return false; 12723788Sgblack@eecs.umich.edu } 12732292SN/A } 12742292SN/A 12752301SN/A if (renameStatus[tid] == SerializeStall) { 12762292SN/A // Stall ends once the ROB is free. 12772301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 12782292SN/A "unblocking.\n", tid); 12792292SN/A 12802301SN/A DynInstPtr serial_inst = serializeInst[tid]; 12812292SN/A 12822292SN/A renameStatus[tid] = Unblocking; 12832292SN/A 12842292SN/A unblock(tid); 12852292SN/A 12862292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 12877720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 12882292SN/A 12892292SN/A // Put instruction into queue here. 12902301SN/A serial_inst->clearSerializeBefore(); 12912292SN/A 12922292SN/A if (!skidBuffer[tid].empty()) { 12932301SN/A skidBuffer[tid].push_front(serial_inst); 12942292SN/A } else { 12952301SN/A insts[tid].push_front(serial_inst); 12962292SN/A } 12972292SN/A 12982292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12992703Sktlim@umich.edu " Adding to front of list.\n", tid); 13002292SN/A 13012301SN/A serializeInst[tid] = NULL; 13022292SN/A 13032292SN/A return true; 13042292SN/A } 13052292SN/A 13062292SN/A // If we've reached this point, we have not gotten any signals that 13072292SN/A // cause rename to change its status. Rename remains the same as before. 13082292SN/A return false; 13091061SN/A} 13101061SN/A 13111060SN/Atemplate<class Impl> 13121060SN/Avoid 13136221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13141060SN/A{ 13152292SN/A if (inst_list.empty()) { 13162292SN/A // Mark a bit to say that I must serialize on the next instruction. 13172292SN/A serializeOnNextInst[tid] = true; 13181060SN/A return; 13191060SN/A } 13201060SN/A 13212292SN/A // Set the next instruction as serializing. 13222292SN/A inst_list.front()->setSerializeBefore(); 13232292SN/A} 13242292SN/A 13252292SN/Atemplate <class Impl> 13262292SN/Ainline void 13272292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13282292SN/A{ 13292292SN/A switch (source) { 13302292SN/A case ROB: 13312292SN/A ++renameROBFullEvents; 13322292SN/A break; 13332292SN/A case IQ: 13342292SN/A ++renameIQFullEvents; 13352292SN/A break; 13362292SN/A case LSQ: 13372292SN/A ++renameLSQFullEvents; 13382292SN/A break; 13392292SN/A default: 13402292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13412292SN/A break; 13421060SN/A } 13432292SN/A} 13441060SN/A 13452292SN/Atemplate <class Impl> 13462292SN/Avoid 13472292SN/ADefaultRename<Impl>::dumpHistory() 13482292SN/A{ 13492980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13501060SN/A 13516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13521060SN/A 13536221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13541060SN/A 13556221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13562292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13572292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13582292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13591060SN/A 13602292SN/A buf_it++; 13611062SN/A } 13621060SN/A } 13631060SN/A} 1364