rename_impl.hh revision 8907
11689SN/A/* 27854SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37854SAli.Saidi@ARM.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412935Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 441060SN/A#include <list> 451060SN/A 463773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476329Sgblack@eecs.umich.edu#include "arch/registers.hh" 486658Snate@binkert.org#include "config/the_isa.hh" 491717SN/A#include "cpu/o3/rename.hh" 508232Snate@binkert.org#include "debug/Activity.hh" 518232Snate@binkert.org#include "debug/Rename.hh" 525529Snate@binkert.org#include "params/DerivO3CPU.hh" 531060SN/A 546221Snate@binkert.orgusing namespace std; 556221Snate@binkert.org 561061SN/Atemplate <class Impl> 575529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 584329Sktlim@umich.edu : cpu(_cpu), 594329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 602292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 612292SN/A commitToRenameDelay(params->commitToRenameDelay), 622292SN/A renameWidth(params->renameWidth), 632292SN/A commitWidth(params->commitWidth), 643788Sgblack@eecs.umich.edu resumeSerialize(false), 653798Sgblack@eecs.umich.edu resumeUnblocking(false), 665529Snate@binkert.org numThreads(params->numThreads), 672361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 681060SN/A{ 692292SN/A _status = Inactive; 702292SN/A 716221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 726221Snate@binkert.org renameStatus[tid] = Idle; 732292SN/A 746221Snate@binkert.org freeEntries[tid].iqEntries = 0; 756221Snate@binkert.org freeEntries[tid].lsqEntries = 0; 766221Snate@binkert.org freeEntries[tid].robEntries = 0; 772292SN/A 786221Snate@binkert.org stalls[tid].iew = false; 796221Snate@binkert.org stalls[tid].commit = false; 806221Snate@binkert.org serializeInst[tid] = NULL; 812292SN/A 826221Snate@binkert.org instsInProgress[tid] = 0; 832292SN/A 846221Snate@binkert.org emptyROB[tid] = true; 852292SN/A 866221Snate@binkert.org serializeOnNextInst[tid] = false; 872292SN/A } 882292SN/A 892292SN/A // @todo: Make into a parameter. 908907Slukefahr@umich.edu skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 942292SN/Astd::string 952292SN/ADefaultRename<Impl>::name() const 962292SN/A{ 972292SN/A return cpu->name() + ".rename"; 981060SN/A} 991060SN/A 1001061SN/Atemplate <class Impl> 1011060SN/Avoid 1022292SN/ADefaultRename<Impl>::regStats() 1031062SN/A{ 1041062SN/A renameSquashCycles 1058240Snate@binkert.org .name(name() + ".SquashCycles") 1061062SN/A .desc("Number of cycles rename is squashing") 1071062SN/A .prereq(renameSquashCycles); 1081062SN/A renameIdleCycles 1098240Snate@binkert.org .name(name() + ".IdleCycles") 1101062SN/A .desc("Number of cycles rename is idle") 1111062SN/A .prereq(renameIdleCycles); 1121062SN/A renameBlockCycles 1138240Snate@binkert.org .name(name() + ".BlockCycles") 1141062SN/A .desc("Number of cycles rename is blocking") 1151062SN/A .prereq(renameBlockCycles); 1162301SN/A renameSerializeStallCycles 1178240Snate@binkert.org .name(name() + ".serializeStallCycles") 1182301SN/A .desc("count of cycles rename stalled for serializing inst") 1192301SN/A .flags(Stats::total); 1202292SN/A renameRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles rename is running") 1232292SN/A .prereq(renameIdleCycles); 1241062SN/A renameUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles rename is unblocking") 1271062SN/A .prereq(renameUnblockCycles); 1281062SN/A renameRenamedInsts 1298240Snate@binkert.org .name(name() + ".RenamedInsts") 1301062SN/A .desc("Number of instructions processed by rename") 1311062SN/A .prereq(renameRenamedInsts); 1321062SN/A renameSquashedInsts 1338240Snate@binkert.org .name(name() + ".SquashedInsts") 1341062SN/A .desc("Number of squashed instructions processed by rename") 1351062SN/A .prereq(renameSquashedInsts); 1361062SN/A renameROBFullEvents 1378240Snate@binkert.org .name(name() + ".ROBFullEvents") 1382292SN/A .desc("Number of times rename has blocked due to ROB full") 1391062SN/A .prereq(renameROBFullEvents); 1401062SN/A renameIQFullEvents 1418240Snate@binkert.org .name(name() + ".IQFullEvents") 1422292SN/A .desc("Number of times rename has blocked due to IQ full") 1431062SN/A .prereq(renameIQFullEvents); 1442292SN/A renameLSQFullEvents 1458240Snate@binkert.org .name(name() + ".LSQFullEvents") 1462292SN/A .desc("Number of times rename has blocked due to LSQ full") 1472292SN/A .prereq(renameLSQFullEvents); 1481062SN/A renameFullRegistersEvents 1498240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1501062SN/A .desc("Number of times there has been no free registers") 1511062SN/A .prereq(renameFullRegistersEvents); 1521062SN/A renameRenamedOperands 1538240Snate@binkert.org .name(name() + ".RenamedOperands") 1541062SN/A .desc("Number of destination operands rename has renamed") 1551062SN/A .prereq(renameRenamedOperands); 1561062SN/A renameRenameLookups 1578240Snate@binkert.org .name(name() + ".RenameLookups") 1581062SN/A .desc("Number of register rename lookups that rename has made") 1591062SN/A .prereq(renameRenameLookups); 1601062SN/A renameCommittedMaps 1618240Snate@binkert.org .name(name() + ".CommittedMaps") 1621062SN/A .desc("Number of HB maps that are committed") 1631062SN/A .prereq(renameCommittedMaps); 1641062SN/A renameUndoneMaps 1658240Snate@binkert.org .name(name() + ".UndoneMaps") 1661062SN/A .desc("Number of HB maps that are undone due to squashing") 1671062SN/A .prereq(renameUndoneMaps); 1682301SN/A renamedSerializing 1698240Snate@binkert.org .name(name() + ".serializingInsts") 1702301SN/A .desc("count of serializing insts renamed") 1712301SN/A .flags(Stats::total) 1722301SN/A ; 1732301SN/A renamedTempSerializing 1748240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1752301SN/A .desc("count of temporary serializing insts renamed") 1762301SN/A .flags(Stats::total) 1772301SN/A ; 1782307SN/A renameSkidInsts 1798240Snate@binkert.org .name(name() + ".skidInsts") 1802307SN/A .desc("count of insts added to the skid buffer") 1812307SN/A .flags(Stats::total) 1822307SN/A ; 1837897Shestness@cs.utexas.edu intRenameLookups 1848240Snate@binkert.org .name(name() + ".int_rename_lookups") 1857897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1867897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1877897Shestness@cs.utexas.edu fpRenameLookups 1888240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1897897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1907897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1911062SN/A} 1921062SN/A 1931062SN/Atemplate <class Impl> 1941062SN/Avoid 1952292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1961060SN/A{ 1971060SN/A timeBuffer = tb_ptr; 1981060SN/A 1991060SN/A // Setup wire to read information from time buffer, from IEW stage. 2001060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2011060SN/A 2021060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2031060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2041060SN/A 2051060SN/A // Setup wire to write information to previous stages. 2061060SN/A toDecode = timeBuffer->getWire(0); 2071060SN/A} 2081060SN/A 2091061SN/Atemplate <class Impl> 2101060SN/Avoid 2112292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2121060SN/A{ 2131060SN/A renameQueue = rq_ptr; 2141060SN/A 2151060SN/A // Setup wire to write information to future stages. 2161060SN/A toIEW = renameQueue->getWire(0); 2171060SN/A} 2181060SN/A 2191061SN/Atemplate <class Impl> 2201060SN/Avoid 2212292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2221060SN/A{ 2231060SN/A decodeQueue = dq_ptr; 2241060SN/A 2251060SN/A // Setup wire to get information from decode. 2261060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2271060SN/A} 2281060SN/A 2291061SN/Atemplate <class Impl> 2301060SN/Avoid 2312292SN/ADefaultRename<Impl>::initStage() 2321060SN/A{ 2332329SN/A // Grab the number of free entries directly from the stages. 2346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2352292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2362292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2372292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2382292SN/A emptyROB[tid] = true; 2392292SN/A } 2401060SN/A} 2411060SN/A 2422292SN/Atemplate<class Impl> 2432292SN/Avoid 2446221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2452292SN/A{ 2462292SN/A activeThreads = at_ptr; 2472292SN/A} 2482292SN/A 2492292SN/A 2501061SN/Atemplate <class Impl> 2511060SN/Avoid 2522292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2531060SN/A{ 2546221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2556221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2561060SN/A} 2571060SN/A 2581061SN/Atemplate <class Impl> 2591060SN/Avoid 2602292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2611060SN/A{ 2622292SN/A freeList = fl_ptr; 2632292SN/A} 2641060SN/A 2652292SN/Atemplate<class Impl> 2662292SN/Avoid 2672292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2682292SN/A{ 2692292SN/A scoreboard = _scoreboard; 2701060SN/A} 2711060SN/A 2721061SN/Atemplate <class Impl> 2732863Sktlim@umich.edubool 2742843Sktlim@umich.eduDefaultRename<Impl>::drain() 2751060SN/A{ 2762348SN/A // Rename is ready to switch out at any time. 2772843Sktlim@umich.edu cpu->signalDrained(); 2782863Sktlim@umich.edu return true; 2792316SN/A} 2801060SN/A 2812316SN/Atemplate <class Impl> 2822316SN/Avoid 2832843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2842316SN/A{ 2852348SN/A // Clear any state, fix up the rename map. 2866221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2872980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2886221Snate@binkert.org historyBuffer[tid].begin(); 2892307SN/A 2906221Snate@binkert.org while (!historyBuffer[tid].empty()) { 2916221Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2922307SN/A 2932307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2946221Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2952307SN/A 2962307SN/A // Tell the rename map to set the architected register to the 2972307SN/A // previous physical register that it was renamed to. 2986221Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2992307SN/A 3002307SN/A // Put the renamed physical register back on the free list. 3012307SN/A freeList->addReg(hb_it->newPhysReg); 3022307SN/A 3032361SN/A // Be sure to mark its register as ready if it's a misc register. 3042361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 3052361SN/A scoreboard->setReg(hb_it->newPhysReg); 3062361SN/A } 3072361SN/A 3086221Snate@binkert.org historyBuffer[tid].erase(hb_it++); 3092307SN/A } 3106221Snate@binkert.org insts[tid].clear(); 3116221Snate@binkert.org skidBuffer[tid].clear(); 3121060SN/A } 3131060SN/A} 3141060SN/A 3151061SN/Atemplate <class Impl> 3161060SN/Avoid 3172307SN/ADefaultRename<Impl>::takeOverFrom() 3181060SN/A{ 3192307SN/A _status = Inactive; 3202307SN/A initStage(); 3211060SN/A 3222329SN/A // Reset all state prior to taking over from the other CPU. 3236221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3246221Snate@binkert.org renameStatus[tid] = Idle; 3251060SN/A 3266221Snate@binkert.org stalls[tid].iew = false; 3276221Snate@binkert.org stalls[tid].commit = false; 3286221Snate@binkert.org serializeInst[tid] = NULL; 3292307SN/A 3306221Snate@binkert.org instsInProgress[tid] = 0; 3312307SN/A 3326221Snate@binkert.org emptyROB[tid] = true; 3332307SN/A 3346221Snate@binkert.org serializeOnNextInst[tid] = false; 3352307SN/A } 3362307SN/A} 3372307SN/A 3382307SN/Atemplate <class Impl> 3392307SN/Avoid 3406221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3411858SN/A{ 3422292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3431858SN/A 3442292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3452292SN/A // If it still needs to block, the blocking should happen the next 3462292SN/A // cycle and there should be space to hold everything due to the squash. 3472292SN/A if (renameStatus[tid] == Blocked || 3483788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3492292SN/A toDecode->renameUnblock[tid] = 1; 3502698Sktlim@umich.edu 3513788Sgblack@eecs.umich.edu resumeSerialize = false; 3522301SN/A serializeInst[tid] = NULL; 3533788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3543788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3553788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3563788Sgblack@eecs.umich.edu resumeSerialize = true; 3573788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3583788Sgblack@eecs.umich.edu } else { 3593788Sgblack@eecs.umich.edu resumeSerialize = false; 3603788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3613788Sgblack@eecs.umich.edu 3623788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3633788Sgblack@eecs.umich.edu } 3642292SN/A } 3652292SN/A 3662292SN/A // Set the status to Squashing. 3672292SN/A renameStatus[tid] = Squashing; 3682292SN/A 3692329SN/A // Squash any instructions from decode. 3702292SN/A unsigned squashCount = 0; 3712292SN/A 3722292SN/A for (int i=0; i<fromDecode->size; i++) { 3732935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3742935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3752731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3762292SN/A wroteToTimeBuffer = true; 3772292SN/A squashCount++; 3782292SN/A } 3792935Sksewell@umich.edu 3802292SN/A } 3812292SN/A 3822935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3834632Sgblack@eecs.umich.edu // insts in them. 3843093Sksewell@umich.edu insts[tid].clear(); 3852292SN/A 3862292SN/A // Clear the skid buffer in case it has any data in it. 3873093Sksewell@umich.edu skidBuffer[tid].clear(); 3884632Sgblack@eecs.umich.edu 3892935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3902292SN/A} 3912292SN/A 3922292SN/Atemplate <class Impl> 3932292SN/Avoid 3942292SN/ADefaultRename<Impl>::tick() 3952292SN/A{ 3962292SN/A wroteToTimeBuffer = false; 3972292SN/A 3982292SN/A blockThisCycle = false; 3992292SN/A 4002292SN/A bool status_change = false; 4012292SN/A 4022292SN/A toIEWIndex = 0; 4032292SN/A 4042292SN/A sortInsts(); 4052292SN/A 4066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4076221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4082292SN/A 4092292SN/A // Check stall and squash signals. 4103867Sbinkertn@umich.edu while (threads != end) { 4116221Snate@binkert.org ThreadID tid = *threads++; 4122292SN/A 4132292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4142292SN/A 4152292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4162292SN/A 4172292SN/A rename(status_change, tid); 4182292SN/A } 4192292SN/A 4202292SN/A if (status_change) { 4212292SN/A updateStatus(); 4222292SN/A } 4232292SN/A 4242292SN/A if (wroteToTimeBuffer) { 4252292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4262292SN/A cpu->activityThisCycle(); 4272292SN/A } 4282292SN/A 4293867Sbinkertn@umich.edu threads = activeThreads->begin(); 4302292SN/A 4313867Sbinkertn@umich.edu while (threads != end) { 4326221Snate@binkert.org ThreadID tid = *threads++; 4332292SN/A 4342292SN/A // If we committed this cycle then doneSeqNum will be > 0 4352292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4362292SN/A !fromCommit->commitInfo[tid].squash && 4372292SN/A renameStatus[tid] != Squashing) { 4382292SN/A 4392292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4402292SN/A tid); 4412292SN/A } 4422292SN/A } 4432292SN/A 4442292SN/A // @todo: make into updateProgress function 4456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4462292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4472292SN/A 4482292SN/A assert(instsInProgress[tid] >=0); 4492292SN/A } 4502292SN/A 4512292SN/A} 4522292SN/A 4532292SN/Atemplate<class Impl> 4542292SN/Avoid 4556221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4562292SN/A{ 4572292SN/A // If status is Running or idle, 4582292SN/A // call renameInsts() 4592292SN/A // If status is Unblocking, 4602292SN/A // buffer any instructions coming from decode 4612292SN/A // continue trying to empty skid buffer 4622292SN/A // check if stall conditions have passed 4632292SN/A 4642292SN/A if (renameStatus[tid] == Blocked) { 4652292SN/A ++renameBlockCycles; 4662292SN/A } else if (renameStatus[tid] == Squashing) { 4672292SN/A ++renameSquashCycles; 4682301SN/A } else if (renameStatus[tid] == SerializeStall) { 4692301SN/A ++renameSerializeStallCycles; 4703788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4713788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4723788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4733788Sgblack@eecs.umich.edu if (resumeSerialize) { 4743788Sgblack@eecs.umich.edu resumeSerialize = false; 4753788Sgblack@eecs.umich.edu block(tid); 4763788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4773788Sgblack@eecs.umich.edu } 4783798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4793798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4803798Sgblack@eecs.umich.edu block(tid); 4813798Sgblack@eecs.umich.edu resumeUnblocking = false; 4823798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4833798Sgblack@eecs.umich.edu } 4842292SN/A } 4852292SN/A 4862292SN/A if (renameStatus[tid] == Running || 4872292SN/A renameStatus[tid] == Idle) { 4882292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4892292SN/A "stage.\n", tid); 4902292SN/A 4912292SN/A renameInsts(tid); 4922292SN/A } else if (renameStatus[tid] == Unblocking) { 4932292SN/A renameInsts(tid); 4942292SN/A 4952292SN/A if (validInsts()) { 4962292SN/A // Add the current inputs to the skid buffer so they can be 4972292SN/A // reprocessed when this stage unblocks. 4982292SN/A skidInsert(tid); 4992292SN/A } 5002292SN/A 5012292SN/A // If we switched over to blocking, then there's a potential for 5022292SN/A // an overall status change. 5032292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5041858SN/A } 5051858SN/A} 5061858SN/A 5071858SN/Atemplate <class Impl> 5081858SN/Avoid 5096221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5101858SN/A{ 5112292SN/A // Instructions can be either in the skid buffer or the queue of 5122292SN/A // instructions coming from decode, depending on the status. 5132292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5142292SN/A skidBuffer[tid].size() : insts[tid].size(); 5151858SN/A 5162292SN/A // Check the decode queue to see if instructions are available. 5172292SN/A // If there are no available instructions to rename, then do nothing. 5182292SN/A if (insts_available == 0) { 5192292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5202292SN/A tid); 5212292SN/A // Should I change status to idle? 5222292SN/A ++renameIdleCycles; 5232292SN/A return; 5242292SN/A } else if (renameStatus[tid] == Unblocking) { 5252292SN/A ++renameUnblockCycles; 5262292SN/A } else if (renameStatus[tid] == Running) { 5272292SN/A ++renameRunCycles; 5282292SN/A } 5291858SN/A 5302292SN/A DynInstPtr inst; 5312292SN/A 5322292SN/A // Will have to do a different calculation for the number of free 5332292SN/A // entries. 5342292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5352292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5362292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5372292SN/A int min_free_entries = free_rob_entries; 5382292SN/A 5392292SN/A FullSource source = ROB; 5402292SN/A 5412292SN/A if (free_iq_entries < min_free_entries) { 5422292SN/A min_free_entries = free_iq_entries; 5432292SN/A source = IQ; 5442292SN/A } 5452292SN/A 5462292SN/A if (free_lsq_entries < min_free_entries) { 5472292SN/A min_free_entries = free_lsq_entries; 5482292SN/A source = LSQ; 5492292SN/A } 5502292SN/A 5512292SN/A // Check if there's any space left. 5522292SN/A if (min_free_entries <= 0) { 5532292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5542292SN/A "entries.\n" 5552292SN/A "ROB has %i free entries.\n" 5562292SN/A "IQ has %i free entries.\n" 5572292SN/A "LSQ has %i free entries.\n", 5582292SN/A tid, 5592292SN/A free_rob_entries, 5602292SN/A free_iq_entries, 5612292SN/A free_lsq_entries); 5622292SN/A 5632292SN/A blockThisCycle = true; 5642292SN/A 5652292SN/A block(tid); 5662292SN/A 5672292SN/A incrFullStat(source); 5682292SN/A 5692292SN/A return; 5702292SN/A } else if (min_free_entries < insts_available) { 5712292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5722292SN/A "%i insts available, but only %i insts can be " 5732292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5742292SN/A tid, insts_available, min_free_entries); 5752292SN/A 5762292SN/A insts_available = min_free_entries; 5772292SN/A 5782292SN/A blockThisCycle = true; 5792292SN/A 5802292SN/A incrFullStat(source); 5812292SN/A } 5822292SN/A 5832292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5842292SN/A skidBuffer[tid] : insts[tid]; 5852292SN/A 5862292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5872292SN/A "send iew.\n", tid, insts_available); 5882292SN/A 5892292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5902292SN/A "dispatched to IQ last cycle.\n", 5912292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5922292SN/A 5932292SN/A // Handle serializing the next instruction if necessary. 5942292SN/A if (serializeOnNextInst[tid]) { 5952292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5962292SN/A // ROB already empty; no need to serialize. 5972292SN/A serializeOnNextInst[tid] = false; 5982292SN/A } else if (!insts_to_rename.empty()) { 5992292SN/A insts_to_rename.front()->setSerializeBefore(); 6002292SN/A } 6012292SN/A } 6022292SN/A 6032292SN/A int renamed_insts = 0; 6042292SN/A 6052292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6062292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6072292SN/A 6082292SN/A assert(!insts_to_rename.empty()); 6092292SN/A 6102292SN/A inst = insts_to_rename.front(); 6112292SN/A 6122292SN/A insts_to_rename.pop_front(); 6132292SN/A 6142292SN/A if (renameStatus[tid] == Unblocking) { 6157720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6167720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6172292SN/A } 6182292SN/A 6192292SN/A if (inst->isSquashed()) { 6207720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6217720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6227720Sgblack@eecs.umich.edu inst->pcState()); 6232292SN/A 6242292SN/A ++renameSquashedInsts; 6252292SN/A 6262292SN/A // Decrement how many instructions are available. 6272292SN/A --insts_available; 6282292SN/A 6292292SN/A continue; 6302292SN/A } 6312292SN/A 6322292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6337720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6342292SN/A 6352292SN/A // Handle serializeAfter/serializeBefore instructions. 6362292SN/A // serializeAfter marks the next instruction as serializeBefore. 6372292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6382292SN/A // is empty. 6392336SN/A 6402336SN/A // In this model, IPR accesses are serialize before 6412336SN/A // instructions, and store conditionals are serialize after 6422336SN/A // instructions. This is mainly due to lack of support for 6432336SN/A // out-of-order operations of either of those classes of 6442336SN/A // instructions. 6452336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6462336SN/A !inst->isSerializeHandled()) { 6472292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6482292SN/A 6492301SN/A if (!inst->isTempSerializeBefore()) { 6502301SN/A renamedSerializing++; 6512292SN/A inst->setSerializeHandled(); 6522301SN/A } else { 6532301SN/A renamedTempSerializing++; 6542301SN/A } 6552292SN/A 6562301SN/A // Change status over to SerializeStall so that other stages know 6572292SN/A // what this is blocked on. 6582301SN/A renameStatus[tid] = SerializeStall; 6592292SN/A 6602301SN/A serializeInst[tid] = inst; 6612292SN/A 6622292SN/A blockThisCycle = true; 6632292SN/A 6642292SN/A break; 6652336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6662336SN/A !inst->isSerializeHandled()) { 6672292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6682292SN/A 6692307SN/A renamedSerializing++; 6702307SN/A 6712292SN/A inst->setSerializeHandled(); 6722292SN/A 6732292SN/A serializeAfter(insts_to_rename, tid); 6742292SN/A } 6752292SN/A 6762292SN/A // Check here to make sure there are enough destination registers 6772292SN/A // to rename to. Otherwise block. 6782292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6792292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6802292SN/A "physical registers to rename to.\n"); 6812292SN/A blockThisCycle = true; 6824345Sktlim@umich.edu insts_to_rename.push_front(inst); 6832292SN/A ++renameFullRegistersEvents; 6842292SN/A 6852292SN/A break; 6862292SN/A } 6872292SN/A 6882292SN/A renameSrcRegs(inst, inst->threadNumber); 6892292SN/A 6902292SN/A renameDestRegs(inst, inst->threadNumber); 6912292SN/A 6922292SN/A ++renamed_insts; 6932292SN/A 6948471SGiacomo.Gabrielli@arm.com#if TRACING_ON 6958471SGiacomo.Gabrielli@arm.com inst->renameTick = curTick(); 6968471SGiacomo.Gabrielli@arm.com#endif 6978471SGiacomo.Gabrielli@arm.com 6982292SN/A // Put instruction in rename queue. 6992292SN/A toIEW->insts[toIEWIndex] = inst; 7002292SN/A ++(toIEW->size); 7012292SN/A 7022292SN/A // Increment which instruction we're on. 7032292SN/A ++toIEWIndex; 7042292SN/A 7052292SN/A // Decrement how many instructions are available. 7062292SN/A --insts_available; 7072292SN/A } 7082292SN/A 7092292SN/A instsInProgress[tid] += renamed_insts; 7102307SN/A renameRenamedInsts += renamed_insts; 7112292SN/A 7122292SN/A // If we wrote to the time buffer, record this. 7132292SN/A if (toIEWIndex) { 7142292SN/A wroteToTimeBuffer = true; 7152292SN/A } 7162292SN/A 7172292SN/A // Check if there's any instructions left that haven't yet been renamed. 7182292SN/A // If so then block. 7192292SN/A if (insts_available) { 7202292SN/A blockThisCycle = true; 7212292SN/A } 7222292SN/A 7232292SN/A if (blockThisCycle) { 7242292SN/A block(tid); 7252292SN/A toDecode->renameUnblock[tid] = false; 7262292SN/A } 7272292SN/A} 7282292SN/A 7292292SN/Atemplate<class Impl> 7302292SN/Avoid 7316221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7322292SN/A{ 7332292SN/A DynInstPtr inst = NULL; 7342292SN/A 7352292SN/A while (!insts[tid].empty()) { 7362292SN/A inst = insts[tid].front(); 7372292SN/A 7382292SN/A insts[tid].pop_front(); 7392292SN/A 7402292SN/A assert(tid == inst->threadNumber); 7412292SN/A 7427720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7437720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7442292SN/A 7452307SN/A ++renameSkidInsts; 7462307SN/A 7472292SN/A skidBuffer[tid].push_back(inst); 7482292SN/A } 7492292SN/A 7502292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7513798Sgblack@eecs.umich.edu { 7523798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7533798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7543798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7553798Sgblack@eecs.umich.edu { 7563798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7577720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7583798Sgblack@eecs.umich.edu (*it)->seqNum); 7593798Sgblack@eecs.umich.edu } 7602292SN/A panic("Skidbuffer Exceeded Max Size"); 7613798Sgblack@eecs.umich.edu } 7622292SN/A} 7632292SN/A 7642292SN/Atemplate <class Impl> 7652292SN/Avoid 7662292SN/ADefaultRename<Impl>::sortInsts() 7672292SN/A{ 7682292SN/A int insts_from_decode = fromDecode->size; 7692292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7702292SN/A DynInstPtr inst = fromDecode->insts[i]; 7712292SN/A insts[inst->threadNumber].push_back(inst); 7722292SN/A } 7732292SN/A} 7742292SN/A 7752292SN/Atemplate<class Impl> 7762292SN/Abool 7772292SN/ADefaultRename<Impl>::skidsEmpty() 7782292SN/A{ 7796221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7806221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7812292SN/A 7823867Sbinkertn@umich.edu while (threads != end) { 7836221Snate@binkert.org ThreadID tid = *threads++; 7843867Sbinkertn@umich.edu 7853867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7862292SN/A return false; 7872292SN/A } 7882292SN/A 7892292SN/A return true; 7902292SN/A} 7912292SN/A 7922292SN/Atemplate<class Impl> 7932292SN/Avoid 7942292SN/ADefaultRename<Impl>::updateStatus() 7952292SN/A{ 7962292SN/A bool any_unblocking = false; 7972292SN/A 7986221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7996221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8002292SN/A 8013867Sbinkertn@umich.edu while (threads != end) { 8026221Snate@binkert.org ThreadID tid = *threads++; 8032292SN/A 8042292SN/A if (renameStatus[tid] == Unblocking) { 8052292SN/A any_unblocking = true; 8062292SN/A break; 8072292SN/A } 8082292SN/A } 8092292SN/A 8102292SN/A // Rename will have activity if it's unblocking. 8112292SN/A if (any_unblocking) { 8122292SN/A if (_status == Inactive) { 8132292SN/A _status = Active; 8142292SN/A 8152292SN/A DPRINTF(Activity, "Activating stage.\n"); 8162292SN/A 8172733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8182292SN/A } 8192292SN/A } else { 8202292SN/A // If it's not unblocking, then rename will not have any internal 8212292SN/A // activity. Switch it to inactive. 8222292SN/A if (_status == Active) { 8232292SN/A _status = Inactive; 8242292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8252292SN/A 8262733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8272292SN/A } 8282292SN/A } 8292292SN/A} 8302292SN/A 8312292SN/Atemplate <class Impl> 8322292SN/Abool 8336221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8342292SN/A{ 8352292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8362292SN/A 8372292SN/A // Add the current inputs onto the skid buffer, so they can be 8382292SN/A // reprocessed when this stage unblocks. 8392292SN/A skidInsert(tid); 8402292SN/A 8412292SN/A // Only signal backwards to block if the previous stages do not think 8422292SN/A // rename is already blocked. 8432292SN/A if (renameStatus[tid] != Blocked) { 8443798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8453798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8463798Sgblack@eecs.umich.edu // stages to block. 8473798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8482292SN/A toDecode->renameBlock[tid] = true; 8492292SN/A toDecode->renameUnblock[tid] = false; 8502292SN/A wroteToTimeBuffer = true; 8512292SN/A } 8522292SN/A 8532329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8542329SN/A // it would not know to complete the serialize stall. 8552301SN/A if (renameStatus[tid] != SerializeStall) { 8562292SN/A // Set status to Blocked. 8572292SN/A renameStatus[tid] = Blocked; 8582292SN/A return true; 8592292SN/A } 8602292SN/A } 8612292SN/A 8622292SN/A return false; 8632292SN/A} 8642292SN/A 8652292SN/Atemplate <class Impl> 8662292SN/Abool 8676221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8682292SN/A{ 8692292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8702292SN/A 8712292SN/A // Rename is done unblocking if the skid buffer is empty. 8722301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8732292SN/A 8742292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8752292SN/A 8762292SN/A toDecode->renameUnblock[tid] = true; 8772292SN/A wroteToTimeBuffer = true; 8782292SN/A 8792292SN/A renameStatus[tid] = Running; 8802292SN/A return true; 8812292SN/A } 8822292SN/A 8832292SN/A return false; 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Avoid 8886221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8892292SN/A{ 8902980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8912980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8922292SN/A 8931060SN/A // After a syscall squashes everything, the history buffer may be empty 8941060SN/A // but the ROB may still be squashing instructions. 8952292SN/A if (historyBuffer[tid].empty()) { 8961060SN/A return; 8971060SN/A } 8981060SN/A 8991060SN/A // Go through the most recent instructions, undoing the mappings 9001060SN/A // they did and freeing up the registers. 9012292SN/A while (!historyBuffer[tid].empty() && 9022292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 9032292SN/A assert(hb_it != historyBuffer[tid].end()); 9041062SN/A 9052292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9062292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 9071060SN/A 9082292SN/A // Tell the rename map to set the architected register to the 9092292SN/A // previous physical register that it was renamed to. 9102292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9111060SN/A 9122292SN/A // Put the renamed physical register back on the free list. 9132292SN/A freeList->addReg(hb_it->newPhysReg); 9141062SN/A 9152367SN/A // Be sure to mark its register as ready if it's a misc register. 9162367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9172367SN/A scoreboard->setReg(hb_it->newPhysReg); 9182367SN/A } 9192367SN/A 9202292SN/A historyBuffer[tid].erase(hb_it++); 9211061SN/A 9221062SN/A ++renameUndoneMaps; 9231060SN/A } 9241060SN/A} 9251060SN/A 9261060SN/Atemplate<class Impl> 9271060SN/Avoid 9286221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9291060SN/A{ 9302292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9312292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9322292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9332292SN/A 9342980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9352980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9361060SN/A 9371061SN/A --hb_it; 9381060SN/A 9392292SN/A if (historyBuffer[tid].empty()) { 9402292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9412292SN/A return; 9422292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9432292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9442292SN/A "that a syscall happened recently.\n", tid); 9451060SN/A return; 9461060SN/A } 9471060SN/A 9482292SN/A // Commit all the renames up until (and including) the committed sequence 9492292SN/A // number. Some or even all of the committed instructions may not have 9502292SN/A // rename histories if they did not have destination registers that were 9512292SN/A // renamed. 9522292SN/A while (!historyBuffer[tid].empty() && 9532292SN/A hb_it != historyBuffer[tid].end() && 9542292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9551060SN/A 9562329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9572329SN/A "[sn:%lli].\n", 9582292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9591061SN/A 9602292SN/A freeList->addReg((*hb_it).prevPhysReg); 9612292SN/A ++renameCommittedMaps; 9621061SN/A 9632292SN/A historyBuffer[tid].erase(hb_it--); 9641060SN/A } 9651060SN/A} 9661060SN/A 9671061SN/Atemplate <class Impl> 9681061SN/Ainline void 9696221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9701061SN/A{ 9712292SN/A assert(renameMap[tid] != 0); 9722292SN/A 9731061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9741061SN/A 9751061SN/A // Get the architectual register numbers from the source and 9761061SN/A // destination operands, and redirect them to the right register. 9771061SN/A // Will need to mark dependencies though. 9782292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9791061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9803773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9813773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9826313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9837767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9847767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9855082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9865082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9876313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9887767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9897767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9905082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9917649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9927767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9937767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9947767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 9957767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 9967649Sminkyu.jeong@arm.com } else { 9977649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9983773Sgblack@eecs.umich.edu } 9994352Sgblack@eecs.umich.edu 10003773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 10011061SN/A 10021061SN/A // Look up the source registers to get the phys. register they've 10031061SN/A // been renamed to, and set the sources to those registers. 10043773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 10051061SN/A 10062292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 10073773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 10082292SN/A (int)renamed_reg); 10091061SN/A 10101061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10111061SN/A 10122292SN/A // See if the register is ready or not. 10132292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10147767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10157767Sgblack@eecs.umich.edu tid, renamed_reg); 10161061SN/A 10171061SN/A inst->markSrcRegReady(src_idx); 10184636Sgblack@eecs.umich.edu } else { 10197767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10207767Sgblack@eecs.umich.edu tid, renamed_reg); 10211061SN/A } 10221062SN/A 10231062SN/A ++renameRenameLookups; 10247897Shestness@cs.utexas.edu inst->isFloating() ? fpRenameLookups++ : intRenameLookups++; 10251061SN/A } 10261061SN/A} 10271061SN/A 10281061SN/Atemplate <class Impl> 10291061SN/Ainline void 10306221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10311061SN/A{ 10322292SN/A typename RenameMap::RenameInfo rename_result; 10331061SN/A 10341061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10351061SN/A 10362292SN/A // Rename the destination registers. 10372292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10382292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10393773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10403773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10414352Sgblack@eecs.umich.edu // Integer registers are flattened. 10426313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10437767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10447767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10457767Sgblack@eecs.umich.edu } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 10467767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10477767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10487767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10497767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10507767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10517649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10524352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10534352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10547767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10557767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10567767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10577767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10587649Sminkyu.jeong@arm.com } else { 10597649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10603773Sgblack@eecs.umich.edu } 10613773Sgblack@eecs.umich.edu 10623773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10631061SN/A 10642292SN/A // Get the physical register that the destination will be 10652292SN/A // renamed to. 10663773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10671061SN/A 10682292SN/A //Mark Scoreboard entry as not ready 10697854SAli.Saidi@ARM.com if (dest_reg < TheISA::Ctrl_Base_DepTag) 10707854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10711062SN/A 10722292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10733773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10742292SN/A (int)rename_result.first); 10751062SN/A 10762292SN/A // Record the rename information so that a history can be kept. 10773773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10782292SN/A rename_result.first, 10792292SN/A rename_result.second); 10801062SN/A 10812292SN/A historyBuffer[tid].push_front(hb_entry); 10821062SN/A 10832935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10842935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10852935Sksewell@umich.edu historyBuffer[tid].size(), 10862292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10871062SN/A 10882292SN/A // Tell the instruction to rename the appropriate destination 10892292SN/A // register (dest_idx) to the new physical register 10902292SN/A // (rename_result.first), and record the previous physical 10912292SN/A // register that the same logical register was renamed to 10922292SN/A // (rename_result.second). 10932292SN/A inst->renameDestReg(dest_idx, 10942292SN/A rename_result.first, 10952292SN/A rename_result.second); 10961062SN/A 10972292SN/A ++renameRenamedOperands; 10981061SN/A } 10991061SN/A} 11001061SN/A 11011061SN/Atemplate <class Impl> 11021061SN/Ainline int 11036221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11041061SN/A{ 11052292SN/A int num_free = freeEntries[tid].robEntries - 11062292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11072292SN/A 11082292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11092292SN/A 11102292SN/A return num_free; 11111061SN/A} 11121061SN/A 11131061SN/Atemplate <class Impl> 11141061SN/Ainline int 11156221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11161061SN/A{ 11172292SN/A int num_free = freeEntries[tid].iqEntries - 11182292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11192292SN/A 11202292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11212292SN/A 11222292SN/A return num_free; 11232292SN/A} 11242292SN/A 11252292SN/Atemplate <class Impl> 11262292SN/Ainline int 11276221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11282292SN/A{ 11292292SN/A int num_free = freeEntries[tid].lsqEntries - 11302292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11312292SN/A 11322292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11332292SN/A 11342292SN/A return num_free; 11352292SN/A} 11362292SN/A 11372292SN/Atemplate <class Impl> 11382292SN/Aunsigned 11392292SN/ADefaultRename<Impl>::validInsts() 11402292SN/A{ 11412292SN/A unsigned inst_count = 0; 11422292SN/A 11432292SN/A for (int i=0; i<fromDecode->size; i++) { 11442731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11452292SN/A inst_count++; 11462292SN/A } 11472292SN/A 11482292SN/A return inst_count; 11492292SN/A} 11502292SN/A 11512292SN/Atemplate <class Impl> 11522292SN/Avoid 11536221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11542292SN/A{ 11552292SN/A if (fromIEW->iewBlock[tid]) { 11562292SN/A stalls[tid].iew = true; 11572292SN/A } 11582292SN/A 11592292SN/A if (fromIEW->iewUnblock[tid]) { 11602292SN/A assert(stalls[tid].iew); 11612292SN/A stalls[tid].iew = false; 11622292SN/A } 11632292SN/A 11642292SN/A if (fromCommit->commitBlock[tid]) { 11652292SN/A stalls[tid].commit = true; 11662292SN/A } 11672292SN/A 11682292SN/A if (fromCommit->commitUnblock[tid]) { 11692292SN/A assert(stalls[tid].commit); 11702292SN/A stalls[tid].commit = false; 11712292SN/A } 11722292SN/A} 11732292SN/A 11742292SN/Atemplate <class Impl> 11752292SN/Abool 11766221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11772292SN/A{ 11782292SN/A bool ret_val = false; 11792292SN/A 11802292SN/A if (stalls[tid].iew) { 11812292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11822292SN/A ret_val = true; 11832292SN/A } else if (stalls[tid].commit) { 11842292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11852292SN/A ret_val = true; 11862292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11872292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11882292SN/A ret_val = true; 11892292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11902292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11912292SN/A ret_val = true; 11922292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11932292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11942292SN/A ret_val = true; 11952292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11962292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11972292SN/A ret_val = true; 11982301SN/A } else if (renameStatus[tid] == SerializeStall && 11992292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12002301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12012292SN/A "empty.\n", 12022292SN/A tid); 12032292SN/A ret_val = true; 12042292SN/A } 12052292SN/A 12062292SN/A return ret_val; 12072292SN/A} 12082292SN/A 12092292SN/Atemplate <class Impl> 12102292SN/Avoid 12116221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12122292SN/A{ 12138607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12148607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12152292SN/A 12168607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedLSQ) 12178607Sgblack@eecs.umich.edu freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 12182292SN/A 12192292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12202292SN/A freeEntries[tid].robEntries = 12212292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12222292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12232292SN/A } 12242292SN/A 12252292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12262292SN/A tid, 12272292SN/A freeEntries[tid].iqEntries, 12282292SN/A freeEntries[tid].robEntries, 12292292SN/A freeEntries[tid].lsqEntries); 12302292SN/A 12312292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12322292SN/A tid, instsInProgress[tid]); 12332292SN/A} 12342292SN/A 12352292SN/Atemplate <class Impl> 12362292SN/Abool 12376221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12382292SN/A{ 12392292SN/A // Check if there's a squash signal, squash if there is 12402292SN/A // Check stall signals, block if necessary. 12412292SN/A // If status was blocked 12422292SN/A // check if stall conditions have passed 12432292SN/A // if so then go to unblocking 12442292SN/A // If status was Squashing 12452292SN/A // check if squashing is not high. Switch to running this cycle. 12462301SN/A // If status was serialize stall 12472292SN/A // check if ROB is empty and no insts are in flight to the ROB 12482292SN/A 12492292SN/A readFreeEntries(tid); 12502292SN/A readStallSignals(tid); 12512292SN/A 12522292SN/A if (fromCommit->commitInfo[tid].squash) { 12532292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12542292SN/A "commit.\n", tid); 12552292SN/A 12564632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12572292SN/A 12582292SN/A return true; 12592292SN/A } 12602292SN/A 12612292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12622292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12632292SN/A 12642292SN/A renameStatus[tid] = Squashing; 12652292SN/A 12662292SN/A return true; 12672292SN/A } 12682292SN/A 12692292SN/A if (checkStall(tid)) { 12702292SN/A return block(tid); 12712292SN/A } 12722292SN/A 12732292SN/A if (renameStatus[tid] == Blocked) { 12742292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12752292SN/A tid); 12762292SN/A 12772292SN/A renameStatus[tid] = Unblocking; 12782292SN/A 12792292SN/A unblock(tid); 12802292SN/A 12812292SN/A return true; 12822292SN/A } 12832292SN/A 12842292SN/A if (renameStatus[tid] == Squashing) { 12852292SN/A // Switch status to running if rename isn't being told to block or 12862292SN/A // squash this cycle. 12873798Sgblack@eecs.umich.edu if (resumeSerialize) { 12883798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12893798Sgblack@eecs.umich.edu tid); 12902292SN/A 12913798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12923798Sgblack@eecs.umich.edu return true; 12933798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12943798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12953798Sgblack@eecs.umich.edu tid); 12963798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12973798Sgblack@eecs.umich.edu return true; 12983798Sgblack@eecs.umich.edu } else { 12993788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13003788Sgblack@eecs.umich.edu tid); 13012292SN/A 13023788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13033788Sgblack@eecs.umich.edu return false; 13043788Sgblack@eecs.umich.edu } 13052292SN/A } 13062292SN/A 13072301SN/A if (renameStatus[tid] == SerializeStall) { 13082292SN/A // Stall ends once the ROB is free. 13092301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13102292SN/A "unblocking.\n", tid); 13112292SN/A 13122301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13132292SN/A 13142292SN/A renameStatus[tid] = Unblocking; 13152292SN/A 13162292SN/A unblock(tid); 13172292SN/A 13182292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13197720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13202292SN/A 13212292SN/A // Put instruction into queue here. 13222301SN/A serial_inst->clearSerializeBefore(); 13232292SN/A 13242292SN/A if (!skidBuffer[tid].empty()) { 13252301SN/A skidBuffer[tid].push_front(serial_inst); 13262292SN/A } else { 13272301SN/A insts[tid].push_front(serial_inst); 13282292SN/A } 13292292SN/A 13302292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13312703Sktlim@umich.edu " Adding to front of list.\n", tid); 13322292SN/A 13332301SN/A serializeInst[tid] = NULL; 13342292SN/A 13352292SN/A return true; 13362292SN/A } 13372292SN/A 13382292SN/A // If we've reached this point, we have not gotten any signals that 13392292SN/A // cause rename to change its status. Rename remains the same as before. 13402292SN/A return false; 13411061SN/A} 13421061SN/A 13431060SN/Atemplate<class Impl> 13441060SN/Avoid 13456221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13461060SN/A{ 13472292SN/A if (inst_list.empty()) { 13482292SN/A // Mark a bit to say that I must serialize on the next instruction. 13492292SN/A serializeOnNextInst[tid] = true; 13501060SN/A return; 13511060SN/A } 13521060SN/A 13532292SN/A // Set the next instruction as serializing. 13542292SN/A inst_list.front()->setSerializeBefore(); 13552292SN/A} 13562292SN/A 13572292SN/Atemplate <class Impl> 13582292SN/Ainline void 13592292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13602292SN/A{ 13612292SN/A switch (source) { 13622292SN/A case ROB: 13632292SN/A ++renameROBFullEvents; 13642292SN/A break; 13652292SN/A case IQ: 13662292SN/A ++renameIQFullEvents; 13672292SN/A break; 13682292SN/A case LSQ: 13692292SN/A ++renameLSQFullEvents; 13702292SN/A break; 13712292SN/A default: 13722292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13732292SN/A break; 13741060SN/A } 13752292SN/A} 13761060SN/A 13772292SN/Atemplate <class Impl> 13782292SN/Avoid 13792292SN/ADefaultRename<Impl>::dumpHistory() 13802292SN/A{ 13812980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13821060SN/A 13836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13841060SN/A 13856221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13861060SN/A 13876221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13882292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13892292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13902292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13911060SN/A 13922292SN/A buf_it++; 13931062SN/A } 13941060SN/A } 13951060SN/A} 1396