rename_impl.hh revision 7854
11689SN/A/* 27854SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37854SAli.Saidi@ARM.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 412935Sksewell@umich.edu * Korey Sewell 421689SN/A */ 431689SN/A 441060SN/A#include <list> 451060SN/A 463773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 476329Sgblack@eecs.umich.edu#include "arch/registers.hh" 481858SN/A#include "config/full_system.hh" 496658Snate@binkert.org#include "config/the_isa.hh" 501717SN/A#include "cpu/o3/rename.hh" 515529Snate@binkert.org#include "params/DerivO3CPU.hh" 521060SN/A 536221Snate@binkert.orgusing namespace std; 546221Snate@binkert.org 551061SN/Atemplate <class Impl> 565529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 574329Sktlim@umich.edu : cpu(_cpu), 584329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 592292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 602292SN/A commitToRenameDelay(params->commitToRenameDelay), 612292SN/A renameWidth(params->renameWidth), 622292SN/A commitWidth(params->commitWidth), 633788Sgblack@eecs.umich.edu resumeSerialize(false), 643798Sgblack@eecs.umich.edu resumeUnblocking(false), 655529Snate@binkert.org numThreads(params->numThreads), 662361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 671060SN/A{ 682292SN/A _status = Inactive; 692292SN/A 706221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 716221Snate@binkert.org renameStatus[tid] = Idle; 722292SN/A 736221Snate@binkert.org freeEntries[tid].iqEntries = 0; 746221Snate@binkert.org freeEntries[tid].lsqEntries = 0; 756221Snate@binkert.org freeEntries[tid].robEntries = 0; 762292SN/A 776221Snate@binkert.org stalls[tid].iew = false; 786221Snate@binkert.org stalls[tid].commit = false; 796221Snate@binkert.org serializeInst[tid] = NULL; 802292SN/A 816221Snate@binkert.org instsInProgress[tid] = 0; 822292SN/A 836221Snate@binkert.org emptyROB[tid] = true; 842292SN/A 856221Snate@binkert.org serializeOnNextInst[tid] = false; 862292SN/A } 872292SN/A 882292SN/A // @todo: Make into a parameter. 892292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 902292SN/A} 912292SN/A 922292SN/Atemplate <class Impl> 932292SN/Astd::string 942292SN/ADefaultRename<Impl>::name() const 952292SN/A{ 962292SN/A return cpu->name() + ".rename"; 971060SN/A} 981060SN/A 991061SN/Atemplate <class Impl> 1001060SN/Avoid 1012292SN/ADefaultRename<Impl>::regStats() 1021062SN/A{ 1031062SN/A renameSquashCycles 1042301SN/A .name(name() + ".RENAME:SquashCycles") 1051062SN/A .desc("Number of cycles rename is squashing") 1061062SN/A .prereq(renameSquashCycles); 1071062SN/A renameIdleCycles 1082301SN/A .name(name() + ".RENAME:IdleCycles") 1091062SN/A .desc("Number of cycles rename is idle") 1101062SN/A .prereq(renameIdleCycles); 1111062SN/A renameBlockCycles 1122301SN/A .name(name() + ".RENAME:BlockCycles") 1131062SN/A .desc("Number of cycles rename is blocking") 1141062SN/A .prereq(renameBlockCycles); 1152301SN/A renameSerializeStallCycles 1162301SN/A .name(name() + ".RENAME:serializeStallCycles") 1172301SN/A .desc("count of cycles rename stalled for serializing inst") 1182301SN/A .flags(Stats::total); 1192292SN/A renameRunCycles 1202301SN/A .name(name() + ".RENAME:RunCycles") 1212292SN/A .desc("Number of cycles rename is running") 1222292SN/A .prereq(renameIdleCycles); 1231062SN/A renameUnblockCycles 1242301SN/A .name(name() + ".RENAME:UnblockCycles") 1251062SN/A .desc("Number of cycles rename is unblocking") 1261062SN/A .prereq(renameUnblockCycles); 1271062SN/A renameRenamedInsts 1282301SN/A .name(name() + ".RENAME:RenamedInsts") 1291062SN/A .desc("Number of instructions processed by rename") 1301062SN/A .prereq(renameRenamedInsts); 1311062SN/A renameSquashedInsts 1322301SN/A .name(name() + ".RENAME:SquashedInsts") 1331062SN/A .desc("Number of squashed instructions processed by rename") 1341062SN/A .prereq(renameSquashedInsts); 1351062SN/A renameROBFullEvents 1362301SN/A .name(name() + ".RENAME:ROBFullEvents") 1372292SN/A .desc("Number of times rename has blocked due to ROB full") 1381062SN/A .prereq(renameROBFullEvents); 1391062SN/A renameIQFullEvents 1402301SN/A .name(name() + ".RENAME:IQFullEvents") 1412292SN/A .desc("Number of times rename has blocked due to IQ full") 1421062SN/A .prereq(renameIQFullEvents); 1432292SN/A renameLSQFullEvents 1442301SN/A .name(name() + ".RENAME:LSQFullEvents") 1452292SN/A .desc("Number of times rename has blocked due to LSQ full") 1462292SN/A .prereq(renameLSQFullEvents); 1471062SN/A renameFullRegistersEvents 1482301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1491062SN/A .desc("Number of times there has been no free registers") 1501062SN/A .prereq(renameFullRegistersEvents); 1511062SN/A renameRenamedOperands 1522301SN/A .name(name() + ".RENAME:RenamedOperands") 1531062SN/A .desc("Number of destination operands rename has renamed") 1541062SN/A .prereq(renameRenamedOperands); 1551062SN/A renameRenameLookups 1562301SN/A .name(name() + ".RENAME:RenameLookups") 1571062SN/A .desc("Number of register rename lookups that rename has made") 1581062SN/A .prereq(renameRenameLookups); 1591062SN/A renameCommittedMaps 1602301SN/A .name(name() + ".RENAME:CommittedMaps") 1611062SN/A .desc("Number of HB maps that are committed") 1621062SN/A .prereq(renameCommittedMaps); 1631062SN/A renameUndoneMaps 1642301SN/A .name(name() + ".RENAME:UndoneMaps") 1651062SN/A .desc("Number of HB maps that are undone due to squashing") 1661062SN/A .prereq(renameUndoneMaps); 1672301SN/A renamedSerializing 1682301SN/A .name(name() + ".RENAME:serializingInsts") 1692301SN/A .desc("count of serializing insts renamed") 1702301SN/A .flags(Stats::total) 1712301SN/A ; 1722301SN/A renamedTempSerializing 1732301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1742301SN/A .desc("count of temporary serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772307SN/A renameSkidInsts 1782307SN/A .name(name() + ".RENAME:skidInsts") 1792307SN/A .desc("count of insts added to the skid buffer") 1802307SN/A .flags(Stats::total) 1812307SN/A ; 1821062SN/A} 1831062SN/A 1841062SN/Atemplate <class Impl> 1851062SN/Avoid 1862292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1871060SN/A{ 1881060SN/A timeBuffer = tb_ptr; 1891060SN/A 1901060SN/A // Setup wire to read information from time buffer, from IEW stage. 1911060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1921060SN/A 1931060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1941060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1951060SN/A 1961060SN/A // Setup wire to write information to previous stages. 1971060SN/A toDecode = timeBuffer->getWire(0); 1981060SN/A} 1991060SN/A 2001061SN/Atemplate <class Impl> 2011060SN/Avoid 2022292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2031060SN/A{ 2041060SN/A renameQueue = rq_ptr; 2051060SN/A 2061060SN/A // Setup wire to write information to future stages. 2071060SN/A toIEW = renameQueue->getWire(0); 2081060SN/A} 2091060SN/A 2101061SN/Atemplate <class Impl> 2111060SN/Avoid 2122292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2131060SN/A{ 2141060SN/A decodeQueue = dq_ptr; 2151060SN/A 2161060SN/A // Setup wire to get information from decode. 2171060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2181060SN/A} 2191060SN/A 2201061SN/Atemplate <class Impl> 2211060SN/Avoid 2222292SN/ADefaultRename<Impl>::initStage() 2231060SN/A{ 2242329SN/A // Grab the number of free entries directly from the stages. 2256221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2262292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2272292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2282292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2292292SN/A emptyROB[tid] = true; 2302292SN/A } 2311060SN/A} 2321060SN/A 2332292SN/Atemplate<class Impl> 2342292SN/Avoid 2356221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2362292SN/A{ 2372292SN/A activeThreads = at_ptr; 2382292SN/A} 2392292SN/A 2402292SN/A 2411061SN/Atemplate <class Impl> 2421060SN/Avoid 2432292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2441060SN/A{ 2456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2466221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2471060SN/A} 2481060SN/A 2491061SN/Atemplate <class Impl> 2501060SN/Avoid 2512292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2521060SN/A{ 2532292SN/A freeList = fl_ptr; 2542292SN/A} 2551060SN/A 2562292SN/Atemplate<class Impl> 2572292SN/Avoid 2582292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2592292SN/A{ 2602292SN/A scoreboard = _scoreboard; 2611060SN/A} 2621060SN/A 2631061SN/Atemplate <class Impl> 2642863Sktlim@umich.edubool 2652843Sktlim@umich.eduDefaultRename<Impl>::drain() 2661060SN/A{ 2672348SN/A // Rename is ready to switch out at any time. 2682843Sktlim@umich.edu cpu->signalDrained(); 2692863Sktlim@umich.edu return true; 2702316SN/A} 2711060SN/A 2722316SN/Atemplate <class Impl> 2732316SN/Avoid 2742843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2752316SN/A{ 2762348SN/A // Clear any state, fix up the rename map. 2776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2782980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2796221Snate@binkert.org historyBuffer[tid].begin(); 2802307SN/A 2816221Snate@binkert.org while (!historyBuffer[tid].empty()) { 2826221Snate@binkert.org assert(hb_it != historyBuffer[tid].end()); 2832307SN/A 2842307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2856221Snate@binkert.org "number %i.\n", tid, (*hb_it).instSeqNum); 2862307SN/A 2872307SN/A // Tell the rename map to set the architected register to the 2882307SN/A // previous physical register that it was renamed to. 2896221Snate@binkert.org renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2902307SN/A 2912307SN/A // Put the renamed physical register back on the free list. 2922307SN/A freeList->addReg(hb_it->newPhysReg); 2932307SN/A 2942361SN/A // Be sure to mark its register as ready if it's a misc register. 2952361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2962361SN/A scoreboard->setReg(hb_it->newPhysReg); 2972361SN/A } 2982361SN/A 2996221Snate@binkert.org historyBuffer[tid].erase(hb_it++); 3002307SN/A } 3016221Snate@binkert.org insts[tid].clear(); 3026221Snate@binkert.org skidBuffer[tid].clear(); 3031060SN/A } 3041060SN/A} 3051060SN/A 3061061SN/Atemplate <class Impl> 3071060SN/Avoid 3082307SN/ADefaultRename<Impl>::takeOverFrom() 3091060SN/A{ 3102307SN/A _status = Inactive; 3112307SN/A initStage(); 3121060SN/A 3132329SN/A // Reset all state prior to taking over from the other CPU. 3146221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3156221Snate@binkert.org renameStatus[tid] = Idle; 3161060SN/A 3176221Snate@binkert.org stalls[tid].iew = false; 3186221Snate@binkert.org stalls[tid].commit = false; 3196221Snate@binkert.org serializeInst[tid] = NULL; 3202307SN/A 3216221Snate@binkert.org instsInProgress[tid] = 0; 3222307SN/A 3236221Snate@binkert.org emptyROB[tid] = true; 3242307SN/A 3256221Snate@binkert.org serializeOnNextInst[tid] = false; 3262307SN/A } 3272307SN/A} 3282307SN/A 3292307SN/Atemplate <class Impl> 3302307SN/Avoid 3316221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3321858SN/A{ 3332292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3341858SN/A 3352292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3362292SN/A // If it still needs to block, the blocking should happen the next 3372292SN/A // cycle and there should be space to hold everything due to the squash. 3382292SN/A if (renameStatus[tid] == Blocked || 3393788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3402292SN/A toDecode->renameUnblock[tid] = 1; 3412698Sktlim@umich.edu 3423788Sgblack@eecs.umich.edu resumeSerialize = false; 3432301SN/A serializeInst[tid] = NULL; 3443788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3453788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3463788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3473788Sgblack@eecs.umich.edu resumeSerialize = true; 3483788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3493788Sgblack@eecs.umich.edu } else { 3503788Sgblack@eecs.umich.edu resumeSerialize = false; 3513788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3523788Sgblack@eecs.umich.edu 3533788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3543788Sgblack@eecs.umich.edu } 3552292SN/A } 3562292SN/A 3572292SN/A // Set the status to Squashing. 3582292SN/A renameStatus[tid] = Squashing; 3592292SN/A 3602329SN/A // Squash any instructions from decode. 3612292SN/A unsigned squashCount = 0; 3622292SN/A 3632292SN/A for (int i=0; i<fromDecode->size; i++) { 3642935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3652935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3662731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3672292SN/A wroteToTimeBuffer = true; 3682292SN/A squashCount++; 3692292SN/A } 3702935Sksewell@umich.edu 3712292SN/A } 3722292SN/A 3732935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3744632Sgblack@eecs.umich.edu // insts in them. 3753093Sksewell@umich.edu insts[tid].clear(); 3762292SN/A 3772292SN/A // Clear the skid buffer in case it has any data in it. 3783093Sksewell@umich.edu skidBuffer[tid].clear(); 3794632Sgblack@eecs.umich.edu 3802935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3812292SN/A} 3822292SN/A 3832292SN/Atemplate <class Impl> 3842292SN/Avoid 3852292SN/ADefaultRename<Impl>::tick() 3862292SN/A{ 3872292SN/A wroteToTimeBuffer = false; 3882292SN/A 3892292SN/A blockThisCycle = false; 3902292SN/A 3912292SN/A bool status_change = false; 3922292SN/A 3932292SN/A toIEWIndex = 0; 3942292SN/A 3952292SN/A sortInsts(); 3962292SN/A 3976221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3986221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3992292SN/A 4002292SN/A // Check stall and squash signals. 4013867Sbinkertn@umich.edu while (threads != end) { 4026221Snate@binkert.org ThreadID tid = *threads++; 4032292SN/A 4042292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4052292SN/A 4062292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4072292SN/A 4082292SN/A rename(status_change, tid); 4092292SN/A } 4102292SN/A 4112292SN/A if (status_change) { 4122292SN/A updateStatus(); 4132292SN/A } 4142292SN/A 4152292SN/A if (wroteToTimeBuffer) { 4162292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4172292SN/A cpu->activityThisCycle(); 4182292SN/A } 4192292SN/A 4203867Sbinkertn@umich.edu threads = activeThreads->begin(); 4212292SN/A 4223867Sbinkertn@umich.edu while (threads != end) { 4236221Snate@binkert.org ThreadID tid = *threads++; 4242292SN/A 4252292SN/A // If we committed this cycle then doneSeqNum will be > 0 4262292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4272292SN/A !fromCommit->commitInfo[tid].squash && 4282292SN/A renameStatus[tid] != Squashing) { 4292292SN/A 4302292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4312292SN/A tid); 4322292SN/A } 4332292SN/A } 4342292SN/A 4352292SN/A // @todo: make into updateProgress function 4366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4372292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4382292SN/A 4392292SN/A assert(instsInProgress[tid] >=0); 4402292SN/A } 4412292SN/A 4422292SN/A} 4432292SN/A 4442292SN/Atemplate<class Impl> 4452292SN/Avoid 4466221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4472292SN/A{ 4482292SN/A // If status is Running or idle, 4492292SN/A // call renameInsts() 4502292SN/A // If status is Unblocking, 4512292SN/A // buffer any instructions coming from decode 4522292SN/A // continue trying to empty skid buffer 4532292SN/A // check if stall conditions have passed 4542292SN/A 4552292SN/A if (renameStatus[tid] == Blocked) { 4562292SN/A ++renameBlockCycles; 4572292SN/A } else if (renameStatus[tid] == Squashing) { 4582292SN/A ++renameSquashCycles; 4592301SN/A } else if (renameStatus[tid] == SerializeStall) { 4602301SN/A ++renameSerializeStallCycles; 4613788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4623788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4633788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4643788Sgblack@eecs.umich.edu if (resumeSerialize) { 4653788Sgblack@eecs.umich.edu resumeSerialize = false; 4663788Sgblack@eecs.umich.edu block(tid); 4673788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4683788Sgblack@eecs.umich.edu } 4693798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4703798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4713798Sgblack@eecs.umich.edu block(tid); 4723798Sgblack@eecs.umich.edu resumeUnblocking = false; 4733798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4743798Sgblack@eecs.umich.edu } 4752292SN/A } 4762292SN/A 4772292SN/A if (renameStatus[tid] == Running || 4782292SN/A renameStatus[tid] == Idle) { 4792292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4802292SN/A "stage.\n", tid); 4812292SN/A 4822292SN/A renameInsts(tid); 4832292SN/A } else if (renameStatus[tid] == Unblocking) { 4842292SN/A renameInsts(tid); 4852292SN/A 4862292SN/A if (validInsts()) { 4872292SN/A // Add the current inputs to the skid buffer so they can be 4882292SN/A // reprocessed when this stage unblocks. 4892292SN/A skidInsert(tid); 4902292SN/A } 4912292SN/A 4922292SN/A // If we switched over to blocking, then there's a potential for 4932292SN/A // an overall status change. 4942292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4951858SN/A } 4961858SN/A} 4971858SN/A 4981858SN/Atemplate <class Impl> 4991858SN/Avoid 5006221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5011858SN/A{ 5022292SN/A // Instructions can be either in the skid buffer or the queue of 5032292SN/A // instructions coming from decode, depending on the status. 5042292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5052292SN/A skidBuffer[tid].size() : insts[tid].size(); 5061858SN/A 5072292SN/A // Check the decode queue to see if instructions are available. 5082292SN/A // If there are no available instructions to rename, then do nothing. 5092292SN/A if (insts_available == 0) { 5102292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5112292SN/A tid); 5122292SN/A // Should I change status to idle? 5132292SN/A ++renameIdleCycles; 5142292SN/A return; 5152292SN/A } else if (renameStatus[tid] == Unblocking) { 5162292SN/A ++renameUnblockCycles; 5172292SN/A } else if (renameStatus[tid] == Running) { 5182292SN/A ++renameRunCycles; 5192292SN/A } 5201858SN/A 5212292SN/A DynInstPtr inst; 5222292SN/A 5232292SN/A // Will have to do a different calculation for the number of free 5242292SN/A // entries. 5252292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5262292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5272292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5282292SN/A int min_free_entries = free_rob_entries; 5292292SN/A 5302292SN/A FullSource source = ROB; 5312292SN/A 5322292SN/A if (free_iq_entries < min_free_entries) { 5332292SN/A min_free_entries = free_iq_entries; 5342292SN/A source = IQ; 5352292SN/A } 5362292SN/A 5372292SN/A if (free_lsq_entries < min_free_entries) { 5382292SN/A min_free_entries = free_lsq_entries; 5392292SN/A source = LSQ; 5402292SN/A } 5412292SN/A 5422292SN/A // Check if there's any space left. 5432292SN/A if (min_free_entries <= 0) { 5442292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5452292SN/A "entries.\n" 5462292SN/A "ROB has %i free entries.\n" 5472292SN/A "IQ has %i free entries.\n" 5482292SN/A "LSQ has %i free entries.\n", 5492292SN/A tid, 5502292SN/A free_rob_entries, 5512292SN/A free_iq_entries, 5522292SN/A free_lsq_entries); 5532292SN/A 5542292SN/A blockThisCycle = true; 5552292SN/A 5562292SN/A block(tid); 5572292SN/A 5582292SN/A incrFullStat(source); 5592292SN/A 5602292SN/A return; 5612292SN/A } else if (min_free_entries < insts_available) { 5622292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5632292SN/A "%i insts available, but only %i insts can be " 5642292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5652292SN/A tid, insts_available, min_free_entries); 5662292SN/A 5672292SN/A insts_available = min_free_entries; 5682292SN/A 5692292SN/A blockThisCycle = true; 5702292SN/A 5712292SN/A incrFullStat(source); 5722292SN/A } 5732292SN/A 5742292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5752292SN/A skidBuffer[tid] : insts[tid]; 5762292SN/A 5772292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5782292SN/A "send iew.\n", tid, insts_available); 5792292SN/A 5802292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5812292SN/A "dispatched to IQ last cycle.\n", 5822292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5832292SN/A 5842292SN/A // Handle serializing the next instruction if necessary. 5852292SN/A if (serializeOnNextInst[tid]) { 5862292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5872292SN/A // ROB already empty; no need to serialize. 5882292SN/A serializeOnNextInst[tid] = false; 5892292SN/A } else if (!insts_to_rename.empty()) { 5902292SN/A insts_to_rename.front()->setSerializeBefore(); 5912292SN/A } 5922292SN/A } 5932292SN/A 5942292SN/A int renamed_insts = 0; 5952292SN/A 5962292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5972292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5982292SN/A 5992292SN/A assert(!insts_to_rename.empty()); 6002292SN/A 6012292SN/A inst = insts_to_rename.front(); 6022292SN/A 6032292SN/A insts_to_rename.pop_front(); 6042292SN/A 6052292SN/A if (renameStatus[tid] == Unblocking) { 6067720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6077720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6082292SN/A } 6092292SN/A 6102292SN/A if (inst->isSquashed()) { 6117720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6127720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6137720Sgblack@eecs.umich.edu inst->pcState()); 6142292SN/A 6152292SN/A ++renameSquashedInsts; 6162292SN/A 6172292SN/A // Decrement how many instructions are available. 6182292SN/A --insts_available; 6192292SN/A 6202292SN/A continue; 6212292SN/A } 6222292SN/A 6232292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6247720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6252292SN/A 6262292SN/A // Handle serializeAfter/serializeBefore instructions. 6272292SN/A // serializeAfter marks the next instruction as serializeBefore. 6282292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6292292SN/A // is empty. 6302336SN/A 6312336SN/A // In this model, IPR accesses are serialize before 6322336SN/A // instructions, and store conditionals are serialize after 6332336SN/A // instructions. This is mainly due to lack of support for 6342336SN/A // out-of-order operations of either of those classes of 6352336SN/A // instructions. 6362336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6372336SN/A !inst->isSerializeHandled()) { 6382292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6392292SN/A 6402301SN/A if (!inst->isTempSerializeBefore()) { 6412301SN/A renamedSerializing++; 6422292SN/A inst->setSerializeHandled(); 6432301SN/A } else { 6442301SN/A renamedTempSerializing++; 6452301SN/A } 6462292SN/A 6472301SN/A // Change status over to SerializeStall so that other stages know 6482292SN/A // what this is blocked on. 6492301SN/A renameStatus[tid] = SerializeStall; 6502292SN/A 6512301SN/A serializeInst[tid] = inst; 6522292SN/A 6532292SN/A blockThisCycle = true; 6542292SN/A 6552292SN/A break; 6562336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6572336SN/A !inst->isSerializeHandled()) { 6582292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6592292SN/A 6602307SN/A renamedSerializing++; 6612307SN/A 6622292SN/A inst->setSerializeHandled(); 6632292SN/A 6642292SN/A serializeAfter(insts_to_rename, tid); 6652292SN/A } 6662292SN/A 6672292SN/A // Check here to make sure there are enough destination registers 6682292SN/A // to rename to. Otherwise block. 6692292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6702292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6712292SN/A "physical registers to rename to.\n"); 6722292SN/A blockThisCycle = true; 6734345Sktlim@umich.edu insts_to_rename.push_front(inst); 6742292SN/A ++renameFullRegistersEvents; 6752292SN/A 6762292SN/A break; 6772292SN/A } 6782292SN/A 6792292SN/A renameSrcRegs(inst, inst->threadNumber); 6802292SN/A 6812292SN/A renameDestRegs(inst, inst->threadNumber); 6822292SN/A 6832292SN/A ++renamed_insts; 6842292SN/A 6852292SN/A // Put instruction in rename queue. 6862292SN/A toIEW->insts[toIEWIndex] = inst; 6872292SN/A ++(toIEW->size); 6882292SN/A 6892292SN/A // Increment which instruction we're on. 6902292SN/A ++toIEWIndex; 6912292SN/A 6922292SN/A // Decrement how many instructions are available. 6932292SN/A --insts_available; 6942292SN/A } 6952292SN/A 6962292SN/A instsInProgress[tid] += renamed_insts; 6972307SN/A renameRenamedInsts += renamed_insts; 6982292SN/A 6992292SN/A // If we wrote to the time buffer, record this. 7002292SN/A if (toIEWIndex) { 7012292SN/A wroteToTimeBuffer = true; 7022292SN/A } 7032292SN/A 7042292SN/A // Check if there's any instructions left that haven't yet been renamed. 7052292SN/A // If so then block. 7062292SN/A if (insts_available) { 7072292SN/A blockThisCycle = true; 7082292SN/A } 7092292SN/A 7102292SN/A if (blockThisCycle) { 7112292SN/A block(tid); 7122292SN/A toDecode->renameUnblock[tid] = false; 7132292SN/A } 7142292SN/A} 7152292SN/A 7162292SN/Atemplate<class Impl> 7172292SN/Avoid 7186221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7192292SN/A{ 7202292SN/A DynInstPtr inst = NULL; 7212292SN/A 7222292SN/A while (!insts[tid].empty()) { 7232292SN/A inst = insts[tid].front(); 7242292SN/A 7252292SN/A insts[tid].pop_front(); 7262292SN/A 7272292SN/A assert(tid == inst->threadNumber); 7282292SN/A 7297720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7307720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7312292SN/A 7322307SN/A ++renameSkidInsts; 7332307SN/A 7342292SN/A skidBuffer[tid].push_back(inst); 7352292SN/A } 7362292SN/A 7372292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7383798Sgblack@eecs.umich.edu { 7393798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7403798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7413798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7423798Sgblack@eecs.umich.edu { 7433798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7447720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7453798Sgblack@eecs.umich.edu (*it)->seqNum); 7463798Sgblack@eecs.umich.edu } 7472292SN/A panic("Skidbuffer Exceeded Max Size"); 7483798Sgblack@eecs.umich.edu } 7492292SN/A} 7502292SN/A 7512292SN/Atemplate <class Impl> 7522292SN/Avoid 7532292SN/ADefaultRename<Impl>::sortInsts() 7542292SN/A{ 7552292SN/A int insts_from_decode = fromDecode->size; 7562329SN/A#ifdef DEBUG 7576221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 7586221Snate@binkert.org assert(insts[tid].empty()); 7592329SN/A#endif 7602292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7612292SN/A DynInstPtr inst = fromDecode->insts[i]; 7622292SN/A insts[inst->threadNumber].push_back(inst); 7632292SN/A } 7642292SN/A} 7652292SN/A 7662292SN/Atemplate<class Impl> 7672292SN/Abool 7682292SN/ADefaultRename<Impl>::skidsEmpty() 7692292SN/A{ 7706221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7716221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7722292SN/A 7733867Sbinkertn@umich.edu while (threads != end) { 7746221Snate@binkert.org ThreadID tid = *threads++; 7753867Sbinkertn@umich.edu 7763867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7772292SN/A return false; 7782292SN/A } 7792292SN/A 7802292SN/A return true; 7812292SN/A} 7822292SN/A 7832292SN/Atemplate<class Impl> 7842292SN/Avoid 7852292SN/ADefaultRename<Impl>::updateStatus() 7862292SN/A{ 7872292SN/A bool any_unblocking = false; 7882292SN/A 7896221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7906221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7912292SN/A 7923867Sbinkertn@umich.edu while (threads != end) { 7936221Snate@binkert.org ThreadID tid = *threads++; 7942292SN/A 7952292SN/A if (renameStatus[tid] == Unblocking) { 7962292SN/A any_unblocking = true; 7972292SN/A break; 7982292SN/A } 7992292SN/A } 8002292SN/A 8012292SN/A // Rename will have activity if it's unblocking. 8022292SN/A if (any_unblocking) { 8032292SN/A if (_status == Inactive) { 8042292SN/A _status = Active; 8052292SN/A 8062292SN/A DPRINTF(Activity, "Activating stage.\n"); 8072292SN/A 8082733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8092292SN/A } 8102292SN/A } else { 8112292SN/A // If it's not unblocking, then rename will not have any internal 8122292SN/A // activity. Switch it to inactive. 8132292SN/A if (_status == Active) { 8142292SN/A _status = Inactive; 8152292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8162292SN/A 8172733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8182292SN/A } 8192292SN/A } 8202292SN/A} 8212292SN/A 8222292SN/Atemplate <class Impl> 8232292SN/Abool 8246221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8252292SN/A{ 8262292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8272292SN/A 8282292SN/A // Add the current inputs onto the skid buffer, so they can be 8292292SN/A // reprocessed when this stage unblocks. 8302292SN/A skidInsert(tid); 8312292SN/A 8322292SN/A // Only signal backwards to block if the previous stages do not think 8332292SN/A // rename is already blocked. 8342292SN/A if (renameStatus[tid] != Blocked) { 8353798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8363798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8373798Sgblack@eecs.umich.edu // stages to block. 8383798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8392292SN/A toDecode->renameBlock[tid] = true; 8402292SN/A toDecode->renameUnblock[tid] = false; 8412292SN/A wroteToTimeBuffer = true; 8422292SN/A } 8432292SN/A 8442329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8452329SN/A // it would not know to complete the serialize stall. 8462301SN/A if (renameStatus[tid] != SerializeStall) { 8472292SN/A // Set status to Blocked. 8482292SN/A renameStatus[tid] = Blocked; 8492292SN/A return true; 8502292SN/A } 8512292SN/A } 8522292SN/A 8532292SN/A return false; 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Abool 8586221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8592292SN/A{ 8602292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8612292SN/A 8622292SN/A // Rename is done unblocking if the skid buffer is empty. 8632301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8642292SN/A 8652292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8662292SN/A 8672292SN/A toDecode->renameUnblock[tid] = true; 8682292SN/A wroteToTimeBuffer = true; 8692292SN/A 8702292SN/A renameStatus[tid] = Running; 8712292SN/A return true; 8722292SN/A } 8732292SN/A 8742292SN/A return false; 8752292SN/A} 8762292SN/A 8772292SN/Atemplate <class Impl> 8782292SN/Avoid 8796221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8802292SN/A{ 8812980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8822980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8832292SN/A 8841060SN/A // After a syscall squashes everything, the history buffer may be empty 8851060SN/A // but the ROB may still be squashing instructions. 8862292SN/A if (historyBuffer[tid].empty()) { 8871060SN/A return; 8881060SN/A } 8891060SN/A 8901060SN/A // Go through the most recent instructions, undoing the mappings 8911060SN/A // they did and freeing up the registers. 8922292SN/A while (!historyBuffer[tid].empty() && 8932292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8942292SN/A assert(hb_it != historyBuffer[tid].end()); 8951062SN/A 8962292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8972292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8981060SN/A 8992292SN/A // Tell the rename map to set the architected register to the 9002292SN/A // previous physical register that it was renamed to. 9012292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9021060SN/A 9032292SN/A // Put the renamed physical register back on the free list. 9042292SN/A freeList->addReg(hb_it->newPhysReg); 9051062SN/A 9062367SN/A // Be sure to mark its register as ready if it's a misc register. 9072367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9082367SN/A scoreboard->setReg(hb_it->newPhysReg); 9092367SN/A } 9102367SN/A 9112292SN/A historyBuffer[tid].erase(hb_it++); 9121061SN/A 9131062SN/A ++renameUndoneMaps; 9141060SN/A } 9151060SN/A} 9161060SN/A 9171060SN/Atemplate<class Impl> 9181060SN/Avoid 9196221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9201060SN/A{ 9212292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9222292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9232292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9242292SN/A 9252980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9262980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9271060SN/A 9281061SN/A --hb_it; 9291060SN/A 9302292SN/A if (historyBuffer[tid].empty()) { 9312292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9322292SN/A return; 9332292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9342292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9352292SN/A "that a syscall happened recently.\n", tid); 9361060SN/A return; 9371060SN/A } 9381060SN/A 9392292SN/A // Commit all the renames up until (and including) the committed sequence 9402292SN/A // number. Some or even all of the committed instructions may not have 9412292SN/A // rename histories if they did not have destination registers that were 9422292SN/A // renamed. 9432292SN/A while (!historyBuffer[tid].empty() && 9442292SN/A hb_it != historyBuffer[tid].end() && 9452292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9461060SN/A 9472329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9482329SN/A "[sn:%lli].\n", 9492292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9501061SN/A 9512292SN/A freeList->addReg((*hb_it).prevPhysReg); 9522292SN/A ++renameCommittedMaps; 9531061SN/A 9542292SN/A historyBuffer[tid].erase(hb_it--); 9551060SN/A } 9561060SN/A} 9571060SN/A 9581061SN/Atemplate <class Impl> 9591061SN/Ainline void 9606221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9611061SN/A{ 9622292SN/A assert(renameMap[tid] != 0); 9632292SN/A 9641061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9651061SN/A 9661061SN/A // Get the architectual register numbers from the source and 9671061SN/A // destination operands, and redirect them to the right register. 9681061SN/A // Will need to mark dependencies though. 9692292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9701061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9713773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 9723773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 9736313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); 9747767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9757767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9765082Sgblack@eecs.umich.edu } else if (src_reg < TheISA::Ctrl_Base_DepTag) { 9775082Sgblack@eecs.umich.edu src_reg = src_reg - TheISA::FP_Base_DepTag; 9786313Sgblack@eecs.umich.edu flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); 9797767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 9807767Sgblack@eecs.umich.edu (int)src_reg, (int)flat_src_reg); 9815082Sgblack@eecs.umich.edu flat_src_reg += TheISA::NumIntRegs; 9827649Sminkyu.jeong@arm.com } else if (src_reg < TheISA::Max_DepTag) { 9837767Sgblack@eecs.umich.edu flat_src_reg = src_reg - TheISA::Ctrl_Base_DepTag + 9847767Sgblack@eecs.umich.edu TheISA::NumFloatRegs + TheISA::NumIntRegs; 9857767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 9867767Sgblack@eecs.umich.edu src_reg, flat_src_reg); 9877649Sminkyu.jeong@arm.com } else { 9887649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9893773Sgblack@eecs.umich.edu } 9904352Sgblack@eecs.umich.edu 9913773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 9921061SN/A 9931061SN/A // Look up the source registers to get the phys. register they've 9941061SN/A // been renamed to, and set the sources to those registers. 9953773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 9961061SN/A 9972292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9983773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 9992292SN/A (int)renamed_reg); 10001061SN/A 10011061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10021061SN/A 10032292SN/A // See if the register is ready or not. 10042292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10057767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10067767Sgblack@eecs.umich.edu tid, renamed_reg); 10071061SN/A 10081061SN/A inst->markSrcRegReady(src_idx); 10094636Sgblack@eecs.umich.edu } else { 10107767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10117767Sgblack@eecs.umich.edu tid, renamed_reg); 10121061SN/A } 10131062SN/A 10141062SN/A ++renameRenameLookups; 10151061SN/A } 10161061SN/A} 10171061SN/A 10181061SN/Atemplate <class Impl> 10191061SN/Ainline void 10206221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10211061SN/A{ 10222292SN/A typename RenameMap::RenameInfo rename_result; 10231061SN/A 10241061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10251061SN/A 10262292SN/A // Rename the destination registers. 10272292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10282292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10293773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10303773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10314352Sgblack@eecs.umich.edu // Integer registers are flattened. 10326313Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); 10337767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10347767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10357767Sgblack@eecs.umich.edu } else if (dest_reg < TheISA::Ctrl_Base_DepTag) { 10367767Sgblack@eecs.umich.edu dest_reg = dest_reg - TheISA::FP_Base_DepTag; 10377767Sgblack@eecs.umich.edu flat_dest_reg = inst->tcBase()->flattenFloatIndex(dest_reg); 10387767Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", 10397767Sgblack@eecs.umich.edu (int)dest_reg, (int)flat_dest_reg); 10407767Sgblack@eecs.umich.edu flat_dest_reg += TheISA::NumIntRegs; 10417649Sminkyu.jeong@arm.com } else if (dest_reg < TheISA::Max_DepTag) { 10424352Sgblack@eecs.umich.edu // Floating point and Miscellaneous registers need their indexes 10434352Sgblack@eecs.umich.edu // adjusted to account for the expanded number of flattened int regs. 10447767Sgblack@eecs.umich.edu flat_dest_reg = dest_reg - TheISA::Ctrl_Base_DepTag + 10457767Sgblack@eecs.umich.edu TheISA::NumIntRegs + TheISA::NumFloatRegs; 10467767Sgblack@eecs.umich.edu DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", 10477767Sgblack@eecs.umich.edu dest_reg, flat_dest_reg); 10487649Sminkyu.jeong@arm.com } else { 10497649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10503773Sgblack@eecs.umich.edu } 10513773Sgblack@eecs.umich.edu 10523773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10531061SN/A 10542292SN/A // Get the physical register that the destination will be 10552292SN/A // renamed to. 10563773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10571061SN/A 10582292SN/A //Mark Scoreboard entry as not ready 10597854SAli.Saidi@ARM.com if (dest_reg < TheISA::Ctrl_Base_DepTag) 10607854SAli.Saidi@ARM.com scoreboard->unsetReg(rename_result.first); 10611062SN/A 10622292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10633773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10642292SN/A (int)rename_result.first); 10651062SN/A 10662292SN/A // Record the rename information so that a history can be kept. 10673773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10682292SN/A rename_result.first, 10692292SN/A rename_result.second); 10701062SN/A 10712292SN/A historyBuffer[tid].push_front(hb_entry); 10721062SN/A 10732935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10742935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10752935Sksewell@umich.edu historyBuffer[tid].size(), 10762292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10771062SN/A 10782292SN/A // Tell the instruction to rename the appropriate destination 10792292SN/A // register (dest_idx) to the new physical register 10802292SN/A // (rename_result.first), and record the previous physical 10812292SN/A // register that the same logical register was renamed to 10822292SN/A // (rename_result.second). 10832292SN/A inst->renameDestReg(dest_idx, 10842292SN/A rename_result.first, 10852292SN/A rename_result.second); 10861062SN/A 10872292SN/A ++renameRenamedOperands; 10881061SN/A } 10891061SN/A} 10901061SN/A 10911061SN/Atemplate <class Impl> 10921061SN/Ainline int 10936221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 10941061SN/A{ 10952292SN/A int num_free = freeEntries[tid].robEntries - 10962292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10972292SN/A 10982292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10992292SN/A 11002292SN/A return num_free; 11011061SN/A} 11021061SN/A 11031061SN/Atemplate <class Impl> 11041061SN/Ainline int 11056221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11061061SN/A{ 11072292SN/A int num_free = freeEntries[tid].iqEntries - 11082292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11092292SN/A 11102292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11112292SN/A 11122292SN/A return num_free; 11132292SN/A} 11142292SN/A 11152292SN/Atemplate <class Impl> 11162292SN/Ainline int 11176221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11182292SN/A{ 11192292SN/A int num_free = freeEntries[tid].lsqEntries - 11202292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11212292SN/A 11222292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11232292SN/A 11242292SN/A return num_free; 11252292SN/A} 11262292SN/A 11272292SN/Atemplate <class Impl> 11282292SN/Aunsigned 11292292SN/ADefaultRename<Impl>::validInsts() 11302292SN/A{ 11312292SN/A unsigned inst_count = 0; 11322292SN/A 11332292SN/A for (int i=0; i<fromDecode->size; i++) { 11342731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11352292SN/A inst_count++; 11362292SN/A } 11372292SN/A 11382292SN/A return inst_count; 11392292SN/A} 11402292SN/A 11412292SN/Atemplate <class Impl> 11422292SN/Avoid 11436221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11442292SN/A{ 11452292SN/A if (fromIEW->iewBlock[tid]) { 11462292SN/A stalls[tid].iew = true; 11472292SN/A } 11482292SN/A 11492292SN/A if (fromIEW->iewUnblock[tid]) { 11502292SN/A assert(stalls[tid].iew); 11512292SN/A stalls[tid].iew = false; 11522292SN/A } 11532292SN/A 11542292SN/A if (fromCommit->commitBlock[tid]) { 11552292SN/A stalls[tid].commit = true; 11562292SN/A } 11572292SN/A 11582292SN/A if (fromCommit->commitUnblock[tid]) { 11592292SN/A assert(stalls[tid].commit); 11602292SN/A stalls[tid].commit = false; 11612292SN/A } 11622292SN/A} 11632292SN/A 11642292SN/Atemplate <class Impl> 11652292SN/Abool 11666221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11672292SN/A{ 11682292SN/A bool ret_val = false; 11692292SN/A 11702292SN/A if (stalls[tid].iew) { 11712292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11722292SN/A ret_val = true; 11732292SN/A } else if (stalls[tid].commit) { 11742292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11752292SN/A ret_val = true; 11762292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11772292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11782292SN/A ret_val = true; 11792292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11802292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11812292SN/A ret_val = true; 11822292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11832292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11842292SN/A ret_val = true; 11852292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11862292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11872292SN/A ret_val = true; 11882301SN/A } else if (renameStatus[tid] == SerializeStall && 11892292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11902301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11912292SN/A "empty.\n", 11922292SN/A tid); 11932292SN/A ret_val = true; 11942292SN/A } 11952292SN/A 11962292SN/A return ret_val; 11972292SN/A} 11982292SN/A 11992292SN/Atemplate <class Impl> 12002292SN/Avoid 12016221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12022292SN/A{ 12032292SN/A bool updated = false; 12042292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 12052292SN/A freeEntries[tid].iqEntries = 12062292SN/A fromIEW->iewInfo[tid].freeIQEntries; 12072292SN/A updated = true; 12082292SN/A } 12092292SN/A 12102292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 12112292SN/A freeEntries[tid].lsqEntries = 12122292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 12132292SN/A updated = true; 12142292SN/A } 12152292SN/A 12162292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12172292SN/A freeEntries[tid].robEntries = 12182292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12192292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12202292SN/A updated = true; 12212292SN/A } 12222292SN/A 12232292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12242292SN/A tid, 12252292SN/A freeEntries[tid].iqEntries, 12262292SN/A freeEntries[tid].robEntries, 12272292SN/A freeEntries[tid].lsqEntries); 12282292SN/A 12292292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12302292SN/A tid, instsInProgress[tid]); 12312292SN/A} 12322292SN/A 12332292SN/Atemplate <class Impl> 12342292SN/Abool 12356221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12362292SN/A{ 12372292SN/A // Check if there's a squash signal, squash if there is 12382292SN/A // Check stall signals, block if necessary. 12392292SN/A // If status was blocked 12402292SN/A // check if stall conditions have passed 12412292SN/A // if so then go to unblocking 12422292SN/A // If status was Squashing 12432292SN/A // check if squashing is not high. Switch to running this cycle. 12442301SN/A // If status was serialize stall 12452292SN/A // check if ROB is empty and no insts are in flight to the ROB 12462292SN/A 12472292SN/A readFreeEntries(tid); 12482292SN/A readStallSignals(tid); 12492292SN/A 12502292SN/A if (fromCommit->commitInfo[tid].squash) { 12512292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12522292SN/A "commit.\n", tid); 12532292SN/A 12544632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12552292SN/A 12562292SN/A return true; 12572292SN/A } 12582292SN/A 12592292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12602292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12612292SN/A 12622292SN/A renameStatus[tid] = Squashing; 12632292SN/A 12642292SN/A return true; 12652292SN/A } 12662292SN/A 12672292SN/A if (checkStall(tid)) { 12682292SN/A return block(tid); 12692292SN/A } 12702292SN/A 12712292SN/A if (renameStatus[tid] == Blocked) { 12722292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12732292SN/A tid); 12742292SN/A 12752292SN/A renameStatus[tid] = Unblocking; 12762292SN/A 12772292SN/A unblock(tid); 12782292SN/A 12792292SN/A return true; 12802292SN/A } 12812292SN/A 12822292SN/A if (renameStatus[tid] == Squashing) { 12832292SN/A // Switch status to running if rename isn't being told to block or 12842292SN/A // squash this cycle. 12853798Sgblack@eecs.umich.edu if (resumeSerialize) { 12863798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12873798Sgblack@eecs.umich.edu tid); 12882292SN/A 12893798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12903798Sgblack@eecs.umich.edu return true; 12913798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12923798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12933798Sgblack@eecs.umich.edu tid); 12943798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12953798Sgblack@eecs.umich.edu return true; 12963798Sgblack@eecs.umich.edu } else { 12973788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12983788Sgblack@eecs.umich.edu tid); 12992292SN/A 13003788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13013788Sgblack@eecs.umich.edu return false; 13023788Sgblack@eecs.umich.edu } 13032292SN/A } 13042292SN/A 13052301SN/A if (renameStatus[tid] == SerializeStall) { 13062292SN/A // Stall ends once the ROB is free. 13072301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13082292SN/A "unblocking.\n", tid); 13092292SN/A 13102301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13112292SN/A 13122292SN/A renameStatus[tid] = Unblocking; 13132292SN/A 13142292SN/A unblock(tid); 13152292SN/A 13162292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13177720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13182292SN/A 13192292SN/A // Put instruction into queue here. 13202301SN/A serial_inst->clearSerializeBefore(); 13212292SN/A 13222292SN/A if (!skidBuffer[tid].empty()) { 13232301SN/A skidBuffer[tid].push_front(serial_inst); 13242292SN/A } else { 13252301SN/A insts[tid].push_front(serial_inst); 13262292SN/A } 13272292SN/A 13282292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13292703Sktlim@umich.edu " Adding to front of list.\n", tid); 13302292SN/A 13312301SN/A serializeInst[tid] = NULL; 13322292SN/A 13332292SN/A return true; 13342292SN/A } 13352292SN/A 13362292SN/A // If we've reached this point, we have not gotten any signals that 13372292SN/A // cause rename to change its status. Rename remains the same as before. 13382292SN/A return false; 13391061SN/A} 13401061SN/A 13411060SN/Atemplate<class Impl> 13421060SN/Avoid 13436221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13441060SN/A{ 13452292SN/A if (inst_list.empty()) { 13462292SN/A // Mark a bit to say that I must serialize on the next instruction. 13472292SN/A serializeOnNextInst[tid] = true; 13481060SN/A return; 13491060SN/A } 13501060SN/A 13512292SN/A // Set the next instruction as serializing. 13522292SN/A inst_list.front()->setSerializeBefore(); 13532292SN/A} 13542292SN/A 13552292SN/Atemplate <class Impl> 13562292SN/Ainline void 13572292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13582292SN/A{ 13592292SN/A switch (source) { 13602292SN/A case ROB: 13612292SN/A ++renameROBFullEvents; 13622292SN/A break; 13632292SN/A case IQ: 13642292SN/A ++renameIQFullEvents; 13652292SN/A break; 13662292SN/A case LSQ: 13672292SN/A ++renameLSQFullEvents; 13682292SN/A break; 13692292SN/A default: 13702292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13712292SN/A break; 13721060SN/A } 13732292SN/A} 13741060SN/A 13752292SN/Atemplate <class Impl> 13762292SN/Avoid 13772292SN/ADefaultRename<Impl>::dumpHistory() 13782292SN/A{ 13792980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13801060SN/A 13816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13821060SN/A 13836221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13841060SN/A 13856221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13862292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13872292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13882292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13891060SN/A 13902292SN/A buf_it++; 13911062SN/A } 13921060SN/A } 13931060SN/A} 1394