rename_impl.hh revision 4329
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A * Korey Sewell 301689SN/A */ 311060SN/A 321060SN/A#include <list> 331858SN/A 341717SN/A#include "arch/isa_traits.hh" 351060SN/A#include "arch/regfile.hh" 362292SN/A#include "config/full_system.hh" 372292SN/A#include "cpu/o3/rename.hh" 381061SN/A 392292SN/Atemplate <class Impl> 402292SN/ADefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params) 412292SN/A : cpu(_cpu), 422292SN/A iewToRenameDelay(params->iewToRenameDelay), 432292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 442292SN/A commitToRenameDelay(params->commitToRenameDelay), 452292SN/A renameWidth(params->renameWidth), 461060SN/A commitWidth(params->commitWidth), 472292SN/A resumeSerialize(false), 482292SN/A resumeUnblocking(false), 492292SN/A numThreads(params->numberOfThreads), 502292SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 512292SN/A{ 522292SN/A _status = Inactive; 532292SN/A 542292SN/A for (int i=0; i< numThreads; i++) { 552292SN/A renameStatus[i] = Idle; 562292SN/A 572292SN/A freeEntries[i].iqEntries = 0; 582301SN/A freeEntries[i].lsqEntries = 0; 592292SN/A freeEntries[i].robEntries = 0; 602292SN/A 612292SN/A stalls[i].iew = false; 622292SN/A stalls[i].commit = false; 632292SN/A serializeInst[i] = NULL; 642292SN/A 652292SN/A instsInProgress[i] = 0; 662292SN/A 672292SN/A emptyROB[i] = true; 682292SN/A 692292SN/A serializeOnNextInst[i] = false; 702292SN/A } 712292SN/A 722292SN/A // @todo: Make into a parameter. 732292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 742292SN/A} 752292SN/A 761060SN/Atemplate <class Impl> 771060SN/Astd::string 781061SN/ADefaultRename<Impl>::name() const 791060SN/A{ 802292SN/A return cpu->name() + ".rename"; 811062SN/A} 821062SN/A 832301SN/Atemplate <class Impl> 841062SN/Avoid 851062SN/ADefaultRename<Impl>::regStats() 861062SN/A{ 872301SN/A renameSquashCycles 881062SN/A .name(name() + ".RENAME:SquashCycles") 891062SN/A .desc("Number of cycles rename is squashing") 901062SN/A .prereq(renameSquashCycles); 912301SN/A renameIdleCycles 921062SN/A .name(name() + ".RENAME:IdleCycles") 931062SN/A .desc("Number of cycles rename is idle") 942301SN/A .prereq(renameIdleCycles); 952301SN/A renameBlockCycles 962301SN/A .name(name() + ".RENAME:BlockCycles") 972301SN/A .desc("Number of cycles rename is blocking") 982292SN/A .prereq(renameBlockCycles); 992301SN/A renameSerializeStallCycles 1002292SN/A .name(name() + ".RENAME:serializeStallCycles") 1012292SN/A .desc("count of cycles rename stalled for serializing inst") 1021062SN/A .flags(Stats::total); 1032301SN/A renameRunCycles 1041062SN/A .name(name() + ".RENAME:RunCycles") 1051062SN/A .desc("Number of cycles rename is running") 1061062SN/A .prereq(renameIdleCycles); 1072301SN/A renameUnblockCycles 1081062SN/A .name(name() + ".RENAME:UnblockCycles") 1091062SN/A .desc("Number of cycles rename is unblocking") 1101062SN/A .prereq(renameUnblockCycles); 1112301SN/A renameRenamedInsts 1121062SN/A .name(name() + ".RENAME:RenamedInsts") 1131062SN/A .desc("Number of instructions processed by rename") 1141062SN/A .prereq(renameRenamedInsts); 1152301SN/A renameSquashedInsts 1162292SN/A .name(name() + ".RENAME:SquashedInsts") 1171062SN/A .desc("Number of squashed instructions processed by rename") 1181062SN/A .prereq(renameSquashedInsts); 1192301SN/A renameROBFullEvents 1202292SN/A .name(name() + ".RENAME:ROBFullEvents") 1211062SN/A .desc("Number of times rename has blocked due to ROB full") 1222292SN/A .prereq(renameROBFullEvents); 1232301SN/A renameIQFullEvents 1242292SN/A .name(name() + ".RENAME:IQFullEvents") 1252292SN/A .desc("Number of times rename has blocked due to IQ full") 1261062SN/A .prereq(renameIQFullEvents); 1272301SN/A renameLSQFullEvents 1281062SN/A .name(name() + ".RENAME:LSQFullEvents") 1291062SN/A .desc("Number of times rename has blocked due to LSQ full") 1301062SN/A .prereq(renameLSQFullEvents); 1312301SN/A renameFullRegistersEvents 1321062SN/A .name(name() + ".RENAME:FullRegisterEvents") 1331062SN/A .desc("Number of times there has been no free registers") 1341062SN/A .prereq(renameFullRegistersEvents); 1352301SN/A renameRenamedOperands 1361062SN/A .name(name() + ".RENAME:RenamedOperands") 1371062SN/A .desc("Number of destination operands rename has renamed") 1381062SN/A .prereq(renameRenamedOperands); 1392301SN/A renameRenameLookups 1401062SN/A .name(name() + ".RENAME:RenameLookups") 1411062SN/A .desc("Number of register rename lookups that rename has made") 1421062SN/A .prereq(renameRenameLookups); 1432301SN/A renameCommittedMaps 1441062SN/A .name(name() + ".RENAME:CommittedMaps") 1451062SN/A .desc("Number of HB maps that are committed") 1462301SN/A .prereq(renameCommittedMaps); 1472301SN/A renameUndoneMaps 1482301SN/A .name(name() + ".RENAME:UndoneMaps") 1492301SN/A .desc("Number of HB maps that are undone due to squashing") 1502301SN/A .prereq(renameUndoneMaps); 1512301SN/A renamedSerializing 1522301SN/A .name(name() + ".RENAME:serializingInsts") 1532301SN/A .desc("count of serializing insts renamed") 1542301SN/A .flags(Stats::total) 1552301SN/A ; 1562307SN/A renamedTempSerializing 1572307SN/A .name(name() + ".RENAME:tempSerializingInsts") 1582307SN/A .desc("count of temporary serializing insts renamed") 1592307SN/A .flags(Stats::total) 1602307SN/A ; 1611062SN/A renameSkidInsts 1621062SN/A .name(name() + ".RENAME:skidInsts") 1631062SN/A .desc("count of insts added to the skid buffer") 1641062SN/A .flags(Stats::total) 1652292SN/A ; 1661060SN/A} 1672292SN/A 1681060SN/Atemplate <class Impl> 1691060SN/Avoid 1701060SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1711061SN/A{ 1721060SN/A timeBuffer = tb_ptr; 1732292SN/A 1741060SN/A // Setup wire to read information from time buffer, from IEW stage. 1752292SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1761060SN/A 1771060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1781060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1791060SN/A 1801060SN/A // Setup wire to write information to previous stages. 1811060SN/A toDecode = timeBuffer->getWire(0); 1821060SN/A} 1831060SN/A 1841060SN/Atemplate <class Impl> 1851060SN/Avoid 1861060SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1871060SN/A{ 1881061SN/A renameQueue = rq_ptr; 1891060SN/A 1902292SN/A // Setup wire to write information to future stages. 1911060SN/A toIEW = renameQueue->getWire(0); 1922292SN/A} 1931060SN/A 1941060SN/Atemplate <class Impl> 1951060SN/Avoid 1961060SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 1971060SN/A{ 1981060SN/A decodeQueue = dq_ptr; 1991061SN/A 2001060SN/A // Setup wire to get information from decode. 2012292SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2021060SN/A} 2032292SN/A 2041060SN/Atemplate <class Impl> 2051060SN/Avoid 2061060SN/ADefaultRename<Impl>::initStage() 2071060SN/A{ 2081060SN/A // Grab the number of free entries directly from the stages. 2091060SN/A for (int tid=0; tid < numThreads; tid++) { 2101061SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2111060SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2122292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2131060SN/A emptyROB[tid] = true; 2142329SN/A } 2152292SN/A} 2162292SN/A 2172292SN/Atemplate<class Impl> 2182292SN/Avoid 2192292SN/ADefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2202292SN/A{ 2211060SN/A activeThreads = at_ptr; 2221060SN/A} 2232292SN/A 2242292SN/A 2252292SN/Atemplate <class Impl> 2262292SN/Avoid 2272292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2282292SN/A{ 2292292SN/A for (int i=0; i<numThreads; i++) { 2302292SN/A renameMap[i] = &rm_ptr[i]; 2312292SN/A } 2321061SN/A} 2331060SN/A 2342292SN/Atemplate <class Impl> 2351060SN/Avoid 2362292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2371060SN/A{ 2382292SN/A freeList = fl_ptr; 2392292SN/A} 2401060SN/A 2411060SN/Atemplate<class Impl> 2421060SN/Avoid 2431061SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2441060SN/A{ 2452292SN/A scoreboard = _scoreboard; 2461060SN/A} 2472292SN/A 2482292SN/Atemplate <class Impl> 2492292SN/Abool 2501060SN/ADefaultRename<Impl>::drain() 2512292SN/A{ 2522292SN/A // Rename is ready to switch out at any time. 2532292SN/A cpu->signalDrained(); 2542292SN/A return true; 2552292SN/A} 2562292SN/A 2571060SN/Atemplate <class Impl> 2581060SN/Avoid 2591061SN/ADefaultRename<Impl>::switchOut() 2602292SN/A{ 2612307SN/A // Clear any state, fix up the rename map. 2621060SN/A for (int i = 0; i < numThreads; i++) { 2632348SN/A typename std::list<RenameHistory>::iterator hb_it = 2642316SN/A historyBuffer[i].begin(); 2652316SN/A 2661060SN/A while (!historyBuffer[i].empty()) { 2672316SN/A assert(hb_it != historyBuffer[i].end()); 2682316SN/A 2692316SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2702316SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2712348SN/A 2722307SN/A // Tell the rename map to set the architected register to the 2732307SN/A // previous physical register that it was renamed to. 2742307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2752307SN/A 2762307SN/A // Put the renamed physical register back on the free list. 2772307SN/A freeList->addReg(hb_it->newPhysReg); 2782307SN/A 2792307SN/A // Be sure to mark its register as ready if it's a misc register. 2802307SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2812307SN/A scoreboard->setReg(hb_it->newPhysReg); 2822307SN/A } 2832307SN/A 2842307SN/A historyBuffer[i].erase(hb_it++); 2852307SN/A } 2862307SN/A insts[i].clear(); 2872307SN/A skidBuffer[i].clear(); 2882307SN/A } 2892307SN/A} 2902307SN/A 2912307SN/Atemplate <class Impl> 2921060SN/Avoid 2931060SN/ADefaultRename<Impl>::takeOverFrom() 2941060SN/A{ 2951061SN/A _status = Inactive; 2961060SN/A initStage(); 2972307SN/A 2981060SN/A // Reset all state prior to taking over from the other CPU. 2992307SN/A for (int i=0; i< numThreads; i++) { 3002307SN/A renameStatus[i] = Idle; 3011060SN/A 3022329SN/A stalls[i].iew = false; 3032307SN/A stalls[i].commit = false; 3042307SN/A serializeInst[i] = NULL; 3051060SN/A 3062307SN/A instsInProgress[i] = 0; 3072307SN/A 3082307SN/A emptyROB[i] = true; 3092307SN/A 3102307SN/A serializeOnNextInst[i] = false; 3112307SN/A } 3122307SN/A} 3132307SN/A 3142307SN/Atemplate <class Impl> 3152307SN/Avoid 3162307SN/ADefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3172307SN/A{ 3182307SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3192307SN/A 3202292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3211858SN/A // If it still needs to block, the blocking should happen the next 3222292SN/A // cycle and there should be space to hold everything due to the squash. 3231858SN/A if (renameStatus[tid] == Blocked || 3242292SN/A renameStatus[tid] == Unblocking) { 3252292SN/A toDecode->renameUnblock[tid] = 1; 3262292SN/A 3272292SN/A resumeSerialize = false; 3282292SN/A serializeInst[tid] = NULL; 3292301SN/A } else if (renameStatus[tid] == SerializeStall) { 3302698Sktlim@umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3312292SN/A DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3322698Sktlim@umich.edu resumeSerialize = true; 3332301SN/A assert(serializeInst[tid]); 3342292SN/A } else { 3352292SN/A resumeSerialize = false; 3362292SN/A toDecode->renameUnblock[tid] = 1; 3372292SN/A 3382292SN/A serializeInst[tid] = NULL; 3392329SN/A } 3402292SN/A } 3412292SN/A 3422292SN/A // Set the status to Squashing. 3432292SN/A renameStatus[tid] = Squashing; 3442292SN/A 3452292SN/A // Squash any instructions from decode. 3462292SN/A unsigned squashCount = 0; 3472292SN/A 3482292SN/A for (int i=0; i<fromDecode->size; i++) { 3492292SN/A if (fromDecode->insts[i]->threadNumber == tid && 3502292SN/A fromDecode->insts[i]->seqNum > squash_seq_num) { 3512292SN/A fromDecode->insts[i]->setSquashed(); 3522292SN/A wroteToTimeBuffer = true; 3532292SN/A squashCount++; 3542292SN/A } 3552292SN/A 3562292SN/A } 3572292SN/A 3582292SN/A // Clear the instruction list and skid buffer in case they have any 3592292SN/A // insts in them. Since we support multiple ISAs, we cant just: 3602292SN/A // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 3612292SN/A // a possible delay slot inst for different architectures 3622292SN/A // insts[tid].clear(); 3632292SN/A#if ISA_HAS_DELAY_SLOT 3642292SN/A DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 3652292SN/A "[sn:%i].\n",tid, squash_seq_num); 3662292SN/A ListIt ilist_it = insts[tid].begin(); 3672292SN/A while (ilist_it != insts[tid].end()) { 3682292SN/A if ((*ilist_it)->seqNum > squash_seq_num) { 3692292SN/A (*ilist_it)->setSquashed(); 3702292SN/A DPRINTF(Rename, "Squashing incoming decode instruction, " 3712292SN/A "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 3722292SN/A } 3732292SN/A ilist_it++; 3742292SN/A } 3752292SN/A#else 3762292SN/A insts[tid].clear(); 3772292SN/A#endif 3782292SN/A 3792292SN/A // Clear the skid buffer in case it has any data in it. 3802292SN/A // See comments above. 3812292SN/A // skidBuffer[tid].clear(); 3822292SN/A#if ISA_HAS_DELAY_SLOT 3832292SN/A DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 3842292SN/A "until [sn:%i].\n", tid, squash_seq_num); 3852292SN/A ListIt slist_it = skidBuffer[tid].begin(); 3862292SN/A while (slist_it != skidBuffer[tid].end()) { 3872292SN/A if ((*slist_it)->seqNum > squash_seq_num) { 3882292SN/A (*slist_it)->setSquashed(); 3892292SN/A DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 3902292SN/A "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 3912292SN/A } 3922292SN/A slist_it++; 3932292SN/A } 3942292SN/A resumeUnblocking = (skidBuffer[tid].size() != 0); 3952292SN/A DPRINTF(Rename, "Resume unblocking set to %s\n", 3962292SN/A resumeUnblocking ? "true" : "false"); 3972292SN/A#else 3982292SN/A skidBuffer[tid].clear(); 3992292SN/A#endif 4002292SN/A doSquash(squash_seq_num, tid); 4012292SN/A} 4022292SN/A 4032292SN/Atemplate <class Impl> 4042292SN/Avoid 4052292SN/ADefaultRename<Impl>::tick() 4062292SN/A{ 4072292SN/A wroteToTimeBuffer = false; 4082292SN/A 4092292SN/A blockThisCycle = false; 4102292SN/A 4112292SN/A bool status_change = false; 4122292SN/A 4132292SN/A toIEWIndex = 0; 4142292SN/A 4152292SN/A sortInsts(); 4162292SN/A 4172292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 4182292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 4192292SN/A 4202292SN/A // Check stall and squash signals. 4212292SN/A while (threads != end) { 4222292SN/A unsigned tid = *threads++; 4232292SN/A 4242292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4252292SN/A 4262292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4272292SN/A 4282292SN/A rename(status_change, tid); 4292292SN/A } 4302292SN/A 4312292SN/A if (status_change) { 4322292SN/A updateStatus(); 4332301SN/A } 4342301SN/A 4352292SN/A if (wroteToTimeBuffer) { 4362292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4372292SN/A cpu->activityThisCycle(); 4382292SN/A } 4392292SN/A 4402292SN/A threads = activeThreads->begin(); 4412292SN/A 4422292SN/A while (threads != end) { 4432292SN/A unsigned tid = *threads++; 4442292SN/A 4452292SN/A // If we committed this cycle then doneSeqNum will be > 0 4462292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4472292SN/A !fromCommit->commitInfo[tid].squash && 4482292SN/A renameStatus[tid] != Squashing) { 4492292SN/A 4502292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4512292SN/A tid); 4522292SN/A } 4532292SN/A } 4542292SN/A 4551858SN/A // @todo: make into updateProgress function 4561858SN/A for (int tid=0; tid < numThreads; tid++) { 4571858SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4581858SN/A 4591858SN/A assert(instsInProgress[tid] >=0); 4602292SN/A } 4611858SN/A 4622292SN/A} 4632292SN/A 4642292SN/Atemplate<class Impl> 4652292SN/Avoid 4661858SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4672292SN/A{ 4682292SN/A // If status is Running or idle, 4692292SN/A // call renameInsts() 4702292SN/A // If status is Unblocking, 4712292SN/A // buffer any instructions coming from decode 4722292SN/A // continue trying to empty skid buffer 4732292SN/A // check if stall conditions have passed 4742292SN/A 4752292SN/A if (renameStatus[tid] == Blocked) { 4762292SN/A ++renameBlockCycles; 4772292SN/A } else if (renameStatus[tid] == Squashing) { 4782292SN/A ++renameSquashCycles; 4792292SN/A } else if (renameStatus[tid] == SerializeStall) { 4801858SN/A ++renameSerializeStallCycles; 4812292SN/A // If we are currently in SerializeStall and resumeSerialize 4822292SN/A // was set, then that means that we are resuming serializing 4832292SN/A // this cycle. Tell the previous stages to block. 4842292SN/A if (resumeSerialize) { 4852292SN/A resumeSerialize = false; 4862292SN/A block(tid); 4872292SN/A toDecode->renameUnblock[tid] = false; 4882292SN/A } 4892292SN/A } else if (renameStatus[tid] == Unblocking) { 4902292SN/A if (resumeUnblocking) { 4912292SN/A block(tid); 4922292SN/A resumeUnblocking = false; 4932292SN/A toDecode->renameUnblock[tid] = false; 4942292SN/A } 4952292SN/A } 4962292SN/A 4972292SN/A if (renameStatus[tid] == Running || 4982292SN/A renameStatus[tid] == Idle) { 4992292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 5002292SN/A "stage.\n", tid); 5012292SN/A 5022292SN/A renameInsts(tid); 5032292SN/A } else if (renameStatus[tid] == Unblocking) { 5042292SN/A renameInsts(tid); 5052292SN/A 5062292SN/A if (validInsts()) { 5072292SN/A // Add the current inputs to the skid buffer so they can be 5082292SN/A // reprocessed when this stage unblocks. 5092292SN/A skidInsert(tid); 5102292SN/A } 5112292SN/A 5122292SN/A // If we switched over to blocking, then there's a potential for 5132292SN/A // an overall status change. 5142292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5152292SN/A } 5162292SN/A} 5172292SN/A 5182292SN/Atemplate <class Impl> 5192292SN/Avoid 5202292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 5212292SN/A{ 5222292SN/A // Instructions can be either in the skid buffer or the queue of 5232292SN/A // instructions coming from decode, depending on the status. 5242292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5252292SN/A skidBuffer[tid].size() : insts[tid].size(); 5262292SN/A 5272292SN/A // Check the decode queue to see if instructions are available. 5282292SN/A // If there are no available instructions to rename, then do nothing. 5292292SN/A if (insts_available == 0) { 5302292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5312292SN/A tid); 5322292SN/A // Should I change status to idle? 5332292SN/A ++renameIdleCycles; 5342292SN/A return; 5352292SN/A } else if (renameStatus[tid] == Unblocking) { 5362292SN/A ++renameUnblockCycles; 5372292SN/A } else if (renameStatus[tid] == Running) { 5382292SN/A ++renameRunCycles; 5392292SN/A } 5402292SN/A 5412292SN/A DynInstPtr inst; 5422292SN/A 5432292SN/A // Will have to do a different calculation for the number of free 5442292SN/A // entries. 5452292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5462292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5472292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5482292SN/A int min_free_entries = free_rob_entries; 5492292SN/A 5502292SN/A FullSource source = ROB; 5512292SN/A 5522292SN/A if (free_iq_entries < min_free_entries) { 5532292SN/A min_free_entries = free_iq_entries; 5542292SN/A source = IQ; 5552292SN/A } 5562292SN/A 5572292SN/A if (free_lsq_entries < min_free_entries) { 5582292SN/A min_free_entries = free_lsq_entries; 5592292SN/A source = LSQ; 5602292SN/A } 5612292SN/A 5622292SN/A // Check if there's any space left. 5632292SN/A if (min_free_entries <= 0) { 5642292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5652292SN/A "entries.\n" 5662292SN/A "ROB has %i free entries.\n" 5672292SN/A "IQ has %i free entries.\n" 5682292SN/A "LSQ has %i free entries.\n", 5692292SN/A tid, 5702292SN/A free_rob_entries, 5712292SN/A free_iq_entries, 5722292SN/A free_lsq_entries); 5732292SN/A 5742292SN/A blockThisCycle = true; 5752292SN/A 5762292SN/A block(tid); 5772292SN/A 5782292SN/A incrFullStat(source); 5792292SN/A 5802292SN/A return; 5812292SN/A } else if (min_free_entries < insts_available) { 5822292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5832292SN/A "%i insts available, but only %i insts can be " 5842292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5852292SN/A tid, insts_available, min_free_entries); 5862292SN/A 5872292SN/A insts_available = min_free_entries; 5882292SN/A 5892292SN/A blockThisCycle = true; 5902292SN/A 5912292SN/A incrFullStat(source); 5922336SN/A } 5932336SN/A 5942336SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5952336SN/A skidBuffer[tid] : insts[tid]; 5962336SN/A 5972336SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5982336SN/A "send iew.\n", tid, insts_available); 5992336SN/A 6002292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 6012292SN/A "dispatched to IQ last cycle.\n", 6022301SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 6032301SN/A 6042292SN/A // Handle serializing the next instruction if necessary. 6052301SN/A if (serializeOnNextInst[tid]) { 6062301SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 6072301SN/A // ROB already empty; no need to serialize. 6082292SN/A serializeOnNextInst[tid] = false; 6092301SN/A } else if (!insts_to_rename.empty()) { 6102292SN/A insts_to_rename.front()->setSerializeBefore(); 6112301SN/A } 6122292SN/A } 6132301SN/A 6142292SN/A int renamed_insts = 0; 6152292SN/A 6162292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6172292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6182336SN/A 6192336SN/A assert(!insts_to_rename.empty()); 6202292SN/A 6212292SN/A inst = insts_to_rename.front(); 6222307SN/A 6232307SN/A insts_to_rename.pop_front(); 6242292SN/A 6252292SN/A if (renameStatus[tid] == Unblocking) { 6262292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 6272292SN/A "skidBuffer\n", 6282292SN/A tid, inst->seqNum, inst->readPC()); 6292292SN/A } 6302292SN/A 6312292SN/A if (inst->isSquashed()) { 6322292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 6332292SN/A "squashed, skipping.\n", 6342292SN/A tid, inst->seqNum, inst->readPC()); 6352292SN/A 6362292SN/A ++renameSquashedInsts; 6372292SN/A 6382292SN/A // Decrement how many instructions are available. 6392292SN/A --insts_available; 6402292SN/A 6412292SN/A continue; 6422292SN/A } 6432292SN/A 6442292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6452292SN/A "PC %#x.\n", 6462292SN/A tid, inst->seqNum, inst->readPC()); 6472292SN/A 6482292SN/A // Handle serializeAfter/serializeBefore instructions. 6492292SN/A // serializeAfter marks the next instruction as serializeBefore. 6502292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6512292SN/A // is empty. 6522292SN/A 6532292SN/A // In this model, IPR accesses are serialize before 6542292SN/A // instructions, and store conditionals are serialize after 6552292SN/A // instructions. This is mainly due to lack of support for 6562292SN/A // out-of-order operations of either of those classes of 6572292SN/A // instructions. 6582292SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6592307SN/A !inst->isSerializeHandled()) { 6602292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6612292SN/A 6622292SN/A if (!inst->isTempSerializeBefore()) { 6632292SN/A renamedSerializing++; 6642292SN/A inst->setSerializeHandled(); 6652292SN/A } else { 6662292SN/A renamedTempSerializing++; 6672292SN/A } 6682292SN/A 6692292SN/A // Change status over to SerializeStall so that other stages know 6702292SN/A // what this is blocked on. 6712292SN/A renameStatus[tid] = SerializeStall; 6722292SN/A 6732292SN/A serializeInst[tid] = inst; 6742292SN/A 6752292SN/A blockThisCycle = true; 6762292SN/A 6772292SN/A break; 6782292SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6792292SN/A !inst->isSerializeHandled()) { 6802292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6812292SN/A 6822292SN/A renamedSerializing++; 6832292SN/A 6842292SN/A inst->setSerializeHandled(); 6852292SN/A 6862292SN/A serializeAfter(insts_to_rename, tid); 6872292SN/A } 6882292SN/A 6892292SN/A // Check here to make sure there are enough destination registers 6902292SN/A // to rename to. Otherwise block. 6912292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6922292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6932292SN/A "physical registers to rename to.\n"); 6942307SN/A blockThisCycle = true; 6952307SN/A 6962292SN/A ++renameFullRegistersEvents; 6972292SN/A 6982292SN/A break; 6992292SN/A } 7002292SN/A 7012292SN/A renameSrcRegs(inst, inst->threadNumber); 7022292SN/A 7032292SN/A renameDestRegs(inst, inst->threadNumber); 7042292SN/A 7052292SN/A ++renamed_insts; 7062292SN/A 7072292SN/A // Put instruction in rename queue. 7082329SN/A toIEW->insts[toIEWIndex] = inst; 7092292SN/A ++(toIEW->size); 7102292SN/A 7112329SN/A // Increment which instruction we're on. 7122292SN/A ++toIEWIndex; 7132292SN/A 7142292SN/A // Decrement how many instructions are available. 7152292SN/A --insts_available; 7162292SN/A } 7172292SN/A 7182292SN/A instsInProgress[tid] += renamed_insts; 7192292SN/A renameRenamedInsts += renamed_insts; 7202292SN/A 7212292SN/A // If we wrote to the time buffer, record this. 7222292SN/A if (toIEWIndex) { 7232292SN/A wroteToTimeBuffer = true; 7242292SN/A } 7252292SN/A 7262292SN/A // Check if there's any instructions left that haven't yet been renamed. 7272292SN/A // If so then block. 7282292SN/A if (insts_available) { 7292292SN/A blockThisCycle = true; 7302292SN/A } 7312292SN/A 7322292SN/A if (blockThisCycle) { 7332292SN/A block(tid); 7342292SN/A toDecode->renameUnblock[tid] = false; 7352292SN/A } 7362292SN/A} 7372292SN/A 7382292SN/Atemplate<class Impl> 7392292SN/Avoid 7402292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7412292SN/A{ 7422292SN/A DynInstPtr inst = NULL; 7432292SN/A 7442292SN/A while (!insts[tid].empty()) { 7452292SN/A inst = insts[tid].front(); 7462292SN/A 7472292SN/A insts[tid].pop_front(); 7482292SN/A 7492292SN/A assert(tid == inst->threadNumber); 7502292SN/A 7512292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7522292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7532292SN/A 7542292SN/A ++renameSkidInsts; 7552292SN/A 7562292SN/A skidBuffer[tid].push_back(inst); 7572292SN/A } 7582292SN/A 7592292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7602292SN/A { 7612292SN/A typename InstQueue::iterator it; 7622292SN/A warn("Skidbuffer contents:\n"); 7632292SN/A for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7642292SN/A { 7652292SN/A warn("[tid:%u]: %s [sn:%i].\n", tid, 7662292SN/A (*it)->staticInst->disassemble(inst->readPC()), 7672292SN/A (*it)->seqNum); 7682292SN/A } 7692292SN/A panic("Skidbuffer Exceeded Max Size"); 7702292SN/A } 7712292SN/A} 7722292SN/A 7732292SN/Atemplate <class Impl> 7742292SN/Avoid 7752292SN/ADefaultRename<Impl>::sortInsts() 7762292SN/A{ 7772292SN/A int insts_from_decode = fromDecode->size; 7782292SN/A#ifdef DEBUG 7792292SN/A#if !ISA_HAS_DELAY_SLOT 7802292SN/A for (int i=0; i < numThreads; i++) 7812292SN/A assert(insts[i].empty()); 7822292SN/A#endif 7832292SN/A#endif 7842292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7852292SN/A DynInstPtr inst = fromDecode->insts[i]; 7862292SN/A insts[inst->threadNumber].push_back(inst); 7872292SN/A } 7882292SN/A} 7892292SN/A 7902292SN/Atemplate<class Impl> 7912329SN/Abool 7922329SN/ADefaultRename<Impl>::skidsEmpty() 7932301SN/A{ 7942292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 7952292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 7962292SN/A 7972292SN/A while (threads != end) { 7982292SN/A unsigned tid = *threads++; 7992292SN/A 8002292SN/A if (!skidBuffer[tid].empty()) 8012292SN/A return false; 8022292SN/A } 8032292SN/A 8042292SN/A return true; 8052292SN/A} 8062292SN/A 8072292SN/Atemplate<class Impl> 8082292SN/Avoid 8092292SN/ADefaultRename<Impl>::updateStatus() 8102301SN/A{ 8112292SN/A bool any_unblocking = false; 8122292SN/A 8132292SN/A std::list<unsigned>::iterator threads = activeThreads->begin(); 8142292SN/A std::list<unsigned>::iterator end = activeThreads->end(); 8152292SN/A 8162292SN/A while (threads != end) { 8172292SN/A unsigned tid = *threads++; 8182292SN/A 8192292SN/A if (renameStatus[tid] == Unblocking) { 8202292SN/A any_unblocking = true; 8212292SN/A break; 8222292SN/A } 8232292SN/A } 8242292SN/A 8252292SN/A // Rename will have activity if it's unblocking. 8262292SN/A if (any_unblocking) { 8272292SN/A if (_status == Inactive) { 8282292SN/A _status = Active; 8292292SN/A 8302292SN/A DPRINTF(Activity, "Activating stage.\n"); 8312292SN/A 8321060SN/A cpu->activateStage(O3CPU::RenameIdx); 8331060SN/A } 8342292SN/A } else { 8351060SN/A // If it's not unblocking, then rename will not have any internal 8361060SN/A // activity. Switch it to inactive. 8371060SN/A if (_status == Active) { 8381060SN/A _status = Inactive; 8391060SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8402292SN/A 8412292SN/A cpu->deactivateStage(O3CPU::RenameIdx); 8422292SN/A } 8431062SN/A } 8442292SN/A} 8452292SN/A 8461060SN/Atemplate <class Impl> 8472292SN/Abool 8482292SN/ADefaultRename<Impl>::block(unsigned tid) 8492292SN/A{ 8501060SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8512292SN/A 8522292SN/A // Add the current inputs onto the skid buffer, so they can be 8531062SN/A // reprocessed when this stage unblocks. 8542292SN/A skidInsert(tid); 8551061SN/A 8561062SN/A // Only signal backwards to block if the previous stages do not think 8571060SN/A // rename is already blocked. 8581060SN/A if (renameStatus[tid] != Blocked) { 8591060SN/A // If resumeUnblocking is set, we unblocked during the squash, 8601060SN/A // but now we're have unblocking status. We need to tell earlier 8611060SN/A // stages to block. 8622292SN/A if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8631060SN/A toDecode->renameBlock[tid] = true; 8642292SN/A toDecode->renameUnblock[tid] = false; 8652292SN/A wroteToTimeBuffer = true; 8662292SN/A } 8672292SN/A 8682292SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8691060SN/A // it would not know to complete the serialize stall. 8701061SN/A if (renameStatus[tid] != SerializeStall) { 8711060SN/A // Set status to Blocked. 8722292SN/A renameStatus[tid] = Blocked; 8732292SN/A return true; 8742292SN/A } 8752292SN/A } 8762292SN/A 8772292SN/A return false; 8781060SN/A} 8791060SN/A 8801060SN/Atemplate <class Impl> 8812292SN/Abool 8822292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8832292SN/A{ 8842292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8852292SN/A 8862292SN/A // Rename is done unblocking if the skid buffer is empty. 8872292SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8881060SN/A 8892329SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8902329SN/A 8912292SN/A toDecode->renameUnblock[tid] = true; 8921061SN/A wroteToTimeBuffer = true; 8932292SN/A 8942292SN/A renameStatus[tid] = Running; 8951061SN/A return true; 8962292SN/A } 8971060SN/A 8981060SN/A return false; 8991060SN/A} 9001061SN/A 9011061SN/Atemplate <class Impl> 9022292SN/Avoid 9031061SN/ADefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 9042292SN/A{ 9052292SN/A typename std::list<RenameHistory>::iterator hb_it = 9061061SN/A historyBuffer[tid].begin(); 9071061SN/A 9081061SN/A // After a syscall squashes everything, the history buffer may be empty 9091061SN/A // but the ROB may still be squashing instructions. 9101061SN/A if (historyBuffer[tid].empty()) { 9112292SN/A return; 9121061SN/A } 9131061SN/A 9141061SN/A // Go through the most recent instructions, undoing the mappings 9151061SN/A // they did and freeing up the registers. 9162292SN/A while (!historyBuffer[tid].empty() && 9171061SN/A (*hb_it).instSeqNum > squashed_seq_num) { 9182292SN/A assert(hb_it != historyBuffer[tid].end()); 9192292SN/A 9202292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9211061SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 9221061SN/A 9231061SN/A // Tell the rename map to set the architected register to the 9242292SN/A // previous physical register that it was renamed to. 9252292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9262292SN/A 9271061SN/A // Put the renamed physical register back on the free list. 9281061SN/A freeList->addReg(hb_it->newPhysReg); 9291061SN/A 9301062SN/A // Be sure to mark its register as ready if it's a misc register. 9311062SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9321061SN/A scoreboard->setReg(hb_it->newPhysReg); 9331061SN/A } 9341061SN/A 9351061SN/A historyBuffer[tid].erase(hb_it++); 9361061SN/A 9372292SN/A ++renameUndoneMaps; 9381061SN/A } 9392292SN/A} 9401061SN/A 9411061SN/Atemplate<class Impl> 9421061SN/Avoid 9432292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9442292SN/A{ 9452292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9461061SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9472292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9482292SN/A 9492292SN/A typename std::list<RenameHistory>::iterator hb_it = 9501061SN/A historyBuffer[tid].end(); 9512292SN/A 9522292SN/A --hb_it; 9531062SN/A 9542292SN/A if (historyBuffer[tid].empty()) { 9552292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9562292SN/A return; 9571062SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9582292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9592292SN/A "that a syscall happened recently.\n", tid); 9602292SN/A return; 9612292SN/A } 9621062SN/A 9632292SN/A // Commit all the renames up until (and including) the committed sequence 9641062SN/A // number. Some or even all of the committed instructions may not have 9652292SN/A // rename histories if they did not have destination registers that were 9662292SN/A // renamed. 9672292SN/A while (!historyBuffer[tid].empty() && 9681062SN/A hb_it != historyBuffer[tid].end() && 9692292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9702292SN/A 9712292SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9722292SN/A "[sn:%lli].\n", 9732292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9742292SN/A 9752292SN/A freeList->addReg((*hb_it).prevPhysReg); 9762292SN/A ++renameCommittedMaps; 9771062SN/A 9782292SN/A historyBuffer[tid].erase(hb_it--); 9791061SN/A } 9801061SN/A} 9811061SN/A 9821061SN/Atemplate <class Impl> 9831061SN/Ainline void 9842292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9851061SN/A{ 9862292SN/A assert(renameMap[tid] != 0); 9872292SN/A 9882292SN/A unsigned num_src_regs = inst->numSrcRegs(); 9892292SN/A 9902292SN/A // Get the architectual register numbers from the source and 9912292SN/A // destination operands, and redirect them to the right register. 9921061SN/A // Will need to mark dependencies though. 9931061SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9941061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9951061SN/A RegIndex flat_src_reg = src_reg; 9962292SN/A if (src_reg < TheISA::FP_Base_DepTag) { 9971061SN/A flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 9982292SN/A DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 9992292SN/A } 10002292SN/A inst->flattenSrcReg(src_idx, flat_src_reg); 10012292SN/A 10022292SN/A // Look up the source registers to get the phys. register they've 10032292SN/A // been renamed to, and set the sources to those registers. 10042292SN/A PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 10052292SN/A 10062292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 10072292SN/A "physical reg %i.\n", tid, (int)flat_src_reg, 10082292SN/A (int)renamed_reg); 10092292SN/A 10102292SN/A inst->renameSrcReg(src_idx, renamed_reg); 10112292SN/A 10122292SN/A // See if the register is ready or not. 10132292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10142292SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 10152292SN/A 10162292SN/A inst->markSrcRegReady(src_idx); 10172292SN/A } 10182292SN/A 10192292SN/A ++renameRenameLookups; 10202292SN/A } 10212292SN/A} 10222292SN/A 10232292SN/Atemplate <class Impl> 10242292SN/Ainline void 10252292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 10262292SN/A{ 10272292SN/A typename RenameMap::RenameInfo rename_result; 10282292SN/A 10292292SN/A unsigned num_dest_regs = inst->numDestRegs(); 10302292SN/A 10312292SN/A // Rename the destination registers. 10322292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10332292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10342292SN/A RegIndex flat_dest_reg = dest_reg; 10352292SN/A if (dest_reg < TheISA::FP_Base_DepTag) { 10362292SN/A flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 10372292SN/A DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10382292SN/A } 10392292SN/A 10402292SN/A inst->flattenDestReg(dest_idx, flat_dest_reg); 10412292SN/A 10422292SN/A // Get the physical register that the destination will be 10432292SN/A // renamed to. 10442292SN/A rename_result = renameMap[tid]->rename(flat_dest_reg); 10452292SN/A 10462292SN/A //Mark Scoreboard entry as not ready 10472292SN/A scoreboard->unsetReg(rename_result.first); 10482292SN/A 10492292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10502292SN/A "reg %i.\n", tid, (int)flat_dest_reg, 10512292SN/A (int)rename_result.first); 10522292SN/A 10532292SN/A // Record the rename information so that a history can be kept. 10542292SN/A RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10552292SN/A rename_result.first, 10562292SN/A rename_result.second); 10572292SN/A 10582292SN/A historyBuffer[tid].push_front(hb_entry); 10592292SN/A 10602292SN/A DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10612292SN/A "(size=%i), [sn:%lli].\n",tid, 10622292SN/A historyBuffer[tid].size(), 10632292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10642292SN/A 10652292SN/A // Tell the instruction to rename the appropriate destination 10662292SN/A // register (dest_idx) to the new physical register 10672292SN/A // (rename_result.first), and record the previous physical 10682292SN/A // register that the same logical register was renamed to 10692292SN/A // (rename_result.second). 10702292SN/A inst->renameDestReg(dest_idx, 10712292SN/A rename_result.first, 10722292SN/A rename_result.second); 10732292SN/A 10742292SN/A ++renameRenamedOperands; 10752292SN/A } 10762292SN/A} 10772292SN/A 10782292SN/Atemplate <class Impl> 10792301SN/Ainline int 10802292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10812301SN/A{ 10822292SN/A int num_free = freeEntries[tid].robEntries - 10832292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10842292SN/A 10852292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10862292SN/A 10872292SN/A return num_free; 10882292SN/A} 10892292SN/A 10902292SN/Atemplate <class Impl> 10912292SN/Ainline int 10922292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 10932292SN/A{ 10942292SN/A int num_free = freeEntries[tid].iqEntries - 10952292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10962292SN/A 10972292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10982292SN/A 10992292SN/A return num_free; 11002292SN/A} 11012292SN/A 11022292SN/Atemplate <class Impl> 11032292SN/Ainline int 11042292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 11052292SN/A{ 11062292SN/A int num_free = freeEntries[tid].lsqEntries - 11072292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11082292SN/A 11092292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11102292SN/A 11112292SN/A return num_free; 11122292SN/A} 11132292SN/A 11142292SN/Atemplate <class Impl> 11152292SN/Aunsigned 11162292SN/ADefaultRename<Impl>::validInsts() 11172292SN/A{ 11182292SN/A unsigned inst_count = 0; 11192292SN/A 11202292SN/A for (int i=0; i<fromDecode->size; i++) { 11212292SN/A if (!fromDecode->insts[i]->isSquashed()) 11222292SN/A inst_count++; 11232292SN/A } 11242292SN/A 11252292SN/A return inst_count; 11262292SN/A} 11272292SN/A 11282292SN/Atemplate <class Impl> 11292292SN/Avoid 11302292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 11312292SN/A{ 11322292SN/A if (fromIEW->iewBlock[tid]) { 11332292SN/A stalls[tid].iew = true; 11342292SN/A } 11352301SN/A 11362292SN/A if (fromIEW->iewUnblock[tid]) { 11372292SN/A assert(stalls[tid].iew); 11382292SN/A stalls[tid].iew = false; 11392292SN/A } 11402292SN/A 11412292SN/A if (fromCommit->commitBlock[tid]) { 11422292SN/A stalls[tid].commit = true; 11432292SN/A } 11442292SN/A 11452292SN/A if (fromCommit->commitUnblock[tid]) { 11462292SN/A assert(stalls[tid].commit); 11472292SN/A stalls[tid].commit = false; 11482292SN/A } 11492292SN/A} 11502292SN/A 11512292SN/Atemplate <class Impl> 11522292SN/Abool 11532292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11542292SN/A{ 11552292SN/A bool ret_val = false; 11562292SN/A 11572292SN/A if (stalls[tid].iew) { 11582292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11592292SN/A ret_val = true; 11602292SN/A } else if (stalls[tid].commit) { 11612292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11622292SN/A ret_val = true; 11632292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11642292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11652292SN/A ret_val = true; 11662292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11672292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11682292SN/A ret_val = true; 11692292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11702292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11712292SN/A ret_val = true; 11722292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11732292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11742292SN/A ret_val = true; 11752292SN/A } else if (renameStatus[tid] == SerializeStall && 11762292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11772292SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11782292SN/A "empty.\n", 11792292SN/A tid); 11802292SN/A ret_val = true; 11812292SN/A } 11822292SN/A 11832292SN/A return ret_val; 11842301SN/A} 11852292SN/A 11862301SN/Atemplate <class Impl> 11872292SN/Avoid 11882292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 11892301SN/A{ 11902292SN/A bool updated = false; 11912292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 11922292SN/A freeEntries[tid].iqEntries = 11932292SN/A fromIEW->iewInfo[tid].freeIQEntries; 11942292SN/A updated = true; 11952292SN/A } 11962292SN/A 11972301SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11982292SN/A freeEntries[tid].lsqEntries = 11992292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 12002301SN/A updated = true; 12012292SN/A } 12022292SN/A 12032301SN/A if (fromCommit->commitInfo[tid].usedROB) { 12042292SN/A freeEntries[tid].robEntries = 12052301SN/A fromCommit->commitInfo[tid].freeROBEntries; 12062292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12072292SN/A updated = true; 12082292SN/A } 12092703Sktlim@umich.edu 12102292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12112301SN/A tid, 12122292SN/A freeEntries[tid].iqEntries, 12132292SN/A freeEntries[tid].robEntries, 12142292SN/A freeEntries[tid].lsqEntries); 12152292SN/A 12162292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12172292SN/A tid, instsInProgress[tid]); 12182292SN/A} 12191061SN/A 12201061SN/Atemplate <class Impl> 12211060SN/Abool 12221060SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 12232292SN/A{ 12242292SN/A // Check if there's a squash signal, squash if there is 12251060SN/A // Check stall signals, block if necessary. 12262292SN/A // If status was blocked 12272292SN/A // check if stall conditions have passed 12282292SN/A // if so then go to unblocking 12291060SN/A // If status was Squashing 12301060SN/A // check if squashing is not high. Switch to running this cycle. 12311060SN/A // If status was serialize stall 12322292SN/A // check if ROB is empty and no insts are in flight to the ROB 12332292SN/A 12342292SN/A readFreeEntries(tid); 12352292SN/A readStallSignals(tid); 12362292SN/A 12372292SN/A if (fromCommit->commitInfo[tid].squash) { 12382292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12392292SN/A "commit.\n", tid); 12402292SN/A 12412292SN/A#if ISA_HAS_DELAY_SLOT 12422292SN/A InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 12432292SN/A#else 12442292SN/A InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 12452292SN/A#endif 12462292SN/A 12472292SN/A squash(squashed_seq_num, tid); 12482292SN/A 12492292SN/A return true; 12502292SN/A } 12512292SN/A 12522292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12531060SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12542292SN/A 12551060SN/A renameStatus[tid] = Squashing; 12562292SN/A 12572292SN/A return true; 12582292SN/A } 12592292SN/A 12602292SN/A if (checkStall(tid)) { 12611060SN/A return block(tid); 12622292SN/A } 12631060SN/A 12642292SN/A if (renameStatus[tid] == Blocked) { 12651060SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12662292SN/A tid); 12672292SN/A 12682292SN/A renameStatus[tid] = Unblocking; 12692292SN/A 12701060SN/A unblock(tid); 12712292SN/A 12721062SN/A return true; 12731060SN/A } 12741060SN/A 1275 if (renameStatus[tid] == Squashing) { 1276 // Switch status to running if rename isn't being told to block or 1277 // squash this cycle. 1278 if (resumeSerialize) { 1279 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 1280 tid); 1281 1282 renameStatus[tid] = SerializeStall; 1283 return true; 1284 } else if (resumeUnblocking) { 1285 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 1286 tid); 1287 renameStatus[tid] = Unblocking; 1288 return true; 1289 } else { 1290 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1291 tid); 1292 1293 renameStatus[tid] = Running; 1294 return false; 1295 } 1296 } 1297 1298 if (renameStatus[tid] == SerializeStall) { 1299 // Stall ends once the ROB is free. 1300 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1301 "unblocking.\n", tid); 1302 1303 DynInstPtr serial_inst = serializeInst[tid]; 1304 1305 renameStatus[tid] = Unblocking; 1306 1307 unblock(tid); 1308 1309 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1310 "PC %#x.\n", 1311 tid, serial_inst->seqNum, serial_inst->readPC()); 1312 1313 // Put instruction into queue here. 1314 serial_inst->clearSerializeBefore(); 1315 1316 if (!skidBuffer[tid].empty()) { 1317 skidBuffer[tid].push_front(serial_inst); 1318 } else { 1319 insts[tid].push_front(serial_inst); 1320 } 1321 1322 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1323 " Adding to front of list.\n", tid); 1324 1325 serializeInst[tid] = NULL; 1326 1327 return true; 1328 } 1329 1330 // If we've reached this point, we have not gotten any signals that 1331 // cause rename to change its status. Rename remains the same as before. 1332 return false; 1333} 1334 1335template<class Impl> 1336void 1337DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1338 unsigned tid) 1339{ 1340 if (inst_list.empty()) { 1341 // Mark a bit to say that I must serialize on the next instruction. 1342 serializeOnNextInst[tid] = true; 1343 return; 1344 } 1345 1346 // Set the next instruction as serializing. 1347 inst_list.front()->setSerializeBefore(); 1348} 1349 1350template <class Impl> 1351inline void 1352DefaultRename<Impl>::incrFullStat(const FullSource &source) 1353{ 1354 switch (source) { 1355 case ROB: 1356 ++renameROBFullEvents; 1357 break; 1358 case IQ: 1359 ++renameIQFullEvents; 1360 break; 1361 case LSQ: 1362 ++renameLSQFullEvents; 1363 break; 1364 default: 1365 panic("Rename full stall stat should be incremented for a reason!"); 1366 break; 1367 } 1368} 1369 1370template <class Impl> 1371void 1372DefaultRename<Impl>::dumpHistory() 1373{ 1374 typename std::list<RenameHistory>::iterator buf_it; 1375 1376 for (int i = 0; i < numThreads; i++) { 1377 1378 buf_it = historyBuffer[i].begin(); 1379 1380 while (buf_it != historyBuffer[i].end()) { 1381 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1382 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1383 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1384 1385 buf_it++; 1386 } 1387 } 1388} 1389