rename_impl.hh revision 3798
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 321060SN/A#include <list> 331060SN/A 343773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 353773Sgblack@eecs.umich.edu#include "arch/regfile.hh" 361858SN/A#include "config/full_system.hh" 371717SN/A#include "cpu/o3/rename.hh" 381060SN/A 391061SN/Atemplate <class Impl> 402292SN/ADefaultRename<Impl>::DefaultRename(Params *params) 412292SN/A : iewToRenameDelay(params->iewToRenameDelay), 422292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 432292SN/A commitToRenameDelay(params->commitToRenameDelay), 442292SN/A renameWidth(params->renameWidth), 452292SN/A commitWidth(params->commitWidth), 463788Sgblack@eecs.umich.edu resumeSerialize(false), 473798Sgblack@eecs.umich.edu resumeUnblocking(false), 482361SN/A numThreads(params->numberOfThreads), 492361SN/A maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) 501060SN/A{ 512292SN/A _status = Inactive; 522292SN/A 532292SN/A for (int i=0; i< numThreads; i++) { 542292SN/A renameStatus[i] = Idle; 552292SN/A 562292SN/A freeEntries[i].iqEntries = 0; 572292SN/A freeEntries[i].lsqEntries = 0; 582292SN/A freeEntries[i].robEntries = 0; 592292SN/A 602292SN/A stalls[i].iew = false; 612292SN/A stalls[i].commit = false; 622301SN/A serializeInst[i] = NULL; 632292SN/A 642292SN/A instsInProgress[i] = 0; 652292SN/A 662292SN/A emptyROB[i] = true; 672292SN/A 682292SN/A serializeOnNextInst[i] = false; 692292SN/A } 702292SN/A 712292SN/A // @todo: Make into a parameter. 722292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 732292SN/A} 742292SN/A 752292SN/Atemplate <class Impl> 762292SN/Astd::string 772292SN/ADefaultRename<Impl>::name() const 782292SN/A{ 792292SN/A return cpu->name() + ".rename"; 801060SN/A} 811060SN/A 821061SN/Atemplate <class Impl> 831060SN/Avoid 842292SN/ADefaultRename<Impl>::regStats() 851062SN/A{ 861062SN/A renameSquashCycles 872301SN/A .name(name() + ".RENAME:SquashCycles") 881062SN/A .desc("Number of cycles rename is squashing") 891062SN/A .prereq(renameSquashCycles); 901062SN/A renameIdleCycles 912301SN/A .name(name() + ".RENAME:IdleCycles") 921062SN/A .desc("Number of cycles rename is idle") 931062SN/A .prereq(renameIdleCycles); 941062SN/A renameBlockCycles 952301SN/A .name(name() + ".RENAME:BlockCycles") 961062SN/A .desc("Number of cycles rename is blocking") 971062SN/A .prereq(renameBlockCycles); 982301SN/A renameSerializeStallCycles 992301SN/A .name(name() + ".RENAME:serializeStallCycles") 1002301SN/A .desc("count of cycles rename stalled for serializing inst") 1012301SN/A .flags(Stats::total); 1022292SN/A renameRunCycles 1032301SN/A .name(name() + ".RENAME:RunCycles") 1042292SN/A .desc("Number of cycles rename is running") 1052292SN/A .prereq(renameIdleCycles); 1061062SN/A renameUnblockCycles 1072301SN/A .name(name() + ".RENAME:UnblockCycles") 1081062SN/A .desc("Number of cycles rename is unblocking") 1091062SN/A .prereq(renameUnblockCycles); 1101062SN/A renameRenamedInsts 1112301SN/A .name(name() + ".RENAME:RenamedInsts") 1121062SN/A .desc("Number of instructions processed by rename") 1131062SN/A .prereq(renameRenamedInsts); 1141062SN/A renameSquashedInsts 1152301SN/A .name(name() + ".RENAME:SquashedInsts") 1161062SN/A .desc("Number of squashed instructions processed by rename") 1171062SN/A .prereq(renameSquashedInsts); 1181062SN/A renameROBFullEvents 1192301SN/A .name(name() + ".RENAME:ROBFullEvents") 1202292SN/A .desc("Number of times rename has blocked due to ROB full") 1211062SN/A .prereq(renameROBFullEvents); 1221062SN/A renameIQFullEvents 1232301SN/A .name(name() + ".RENAME:IQFullEvents") 1242292SN/A .desc("Number of times rename has blocked due to IQ full") 1251062SN/A .prereq(renameIQFullEvents); 1262292SN/A renameLSQFullEvents 1272301SN/A .name(name() + ".RENAME:LSQFullEvents") 1282292SN/A .desc("Number of times rename has blocked due to LSQ full") 1292292SN/A .prereq(renameLSQFullEvents); 1301062SN/A renameFullRegistersEvents 1312301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1321062SN/A .desc("Number of times there has been no free registers") 1331062SN/A .prereq(renameFullRegistersEvents); 1341062SN/A renameRenamedOperands 1352301SN/A .name(name() + ".RENAME:RenamedOperands") 1361062SN/A .desc("Number of destination operands rename has renamed") 1371062SN/A .prereq(renameRenamedOperands); 1381062SN/A renameRenameLookups 1392301SN/A .name(name() + ".RENAME:RenameLookups") 1401062SN/A .desc("Number of register rename lookups that rename has made") 1411062SN/A .prereq(renameRenameLookups); 1421062SN/A renameCommittedMaps 1432301SN/A .name(name() + ".RENAME:CommittedMaps") 1441062SN/A .desc("Number of HB maps that are committed") 1451062SN/A .prereq(renameCommittedMaps); 1461062SN/A renameUndoneMaps 1472301SN/A .name(name() + ".RENAME:UndoneMaps") 1481062SN/A .desc("Number of HB maps that are undone due to squashing") 1491062SN/A .prereq(renameUndoneMaps); 1502301SN/A renamedSerializing 1512301SN/A .name(name() + ".RENAME:serializingInsts") 1522301SN/A .desc("count of serializing insts renamed") 1532301SN/A .flags(Stats::total) 1542301SN/A ; 1552301SN/A renamedTempSerializing 1562301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1572301SN/A .desc("count of temporary serializing insts renamed") 1582301SN/A .flags(Stats::total) 1592301SN/A ; 1602307SN/A renameSkidInsts 1612307SN/A .name(name() + ".RENAME:skidInsts") 1622307SN/A .desc("count of insts added to the skid buffer") 1632307SN/A .flags(Stats::total) 1642307SN/A ; 1651062SN/A} 1661062SN/A 1671062SN/Atemplate <class Impl> 1681062SN/Avoid 1692733Sktlim@umich.eduDefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 1701060SN/A{ 1712292SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1721060SN/A cpu = cpu_ptr; 1731060SN/A} 1741060SN/A 1751061SN/Atemplate <class Impl> 1761060SN/Avoid 1772292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1781060SN/A{ 1792292SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1801060SN/A timeBuffer = tb_ptr; 1811060SN/A 1821060SN/A // Setup wire to read information from time buffer, from IEW stage. 1831060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1841060SN/A 1851060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1861060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1871060SN/A 1881060SN/A // Setup wire to write information to previous stages. 1891060SN/A toDecode = timeBuffer->getWire(0); 1901060SN/A} 1911060SN/A 1921061SN/Atemplate <class Impl> 1931060SN/Avoid 1942292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1951060SN/A{ 1962292SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1971060SN/A renameQueue = rq_ptr; 1981060SN/A 1991060SN/A // Setup wire to write information to future stages. 2001060SN/A toIEW = renameQueue->getWire(0); 2011060SN/A} 2021060SN/A 2031061SN/Atemplate <class Impl> 2041060SN/Avoid 2052292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2061060SN/A{ 2072292SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2081060SN/A decodeQueue = dq_ptr; 2091060SN/A 2101060SN/A // Setup wire to get information from decode. 2111060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2121060SN/A} 2131060SN/A 2141061SN/Atemplate <class Impl> 2151060SN/Avoid 2162292SN/ADefaultRename<Impl>::initStage() 2171060SN/A{ 2182329SN/A // Grab the number of free entries directly from the stages. 2192292SN/A for (int tid=0; tid < numThreads; tid++) { 2202292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2212292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2222292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2232292SN/A emptyROB[tid] = true; 2242292SN/A } 2251060SN/A} 2261060SN/A 2272292SN/Atemplate<class Impl> 2282292SN/Avoid 2292980Sgblack@eecs.umich.eduDefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 2302292SN/A{ 2312292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2322292SN/A activeThreads = at_ptr; 2332292SN/A} 2342292SN/A 2352292SN/A 2361061SN/Atemplate <class Impl> 2371060SN/Avoid 2382292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2391060SN/A{ 2402292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2411060SN/A 2422292SN/A for (int i=0; i<numThreads; i++) { 2432292SN/A renameMap[i] = &rm_ptr[i]; 2441060SN/A } 2451060SN/A} 2461060SN/A 2471061SN/Atemplate <class Impl> 2481060SN/Avoid 2492292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2501060SN/A{ 2512292SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2522292SN/A freeList = fl_ptr; 2532292SN/A} 2541060SN/A 2552292SN/Atemplate<class Impl> 2562292SN/Avoid 2572292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2582292SN/A{ 2592292SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2602292SN/A scoreboard = _scoreboard; 2611060SN/A} 2621060SN/A 2631061SN/Atemplate <class Impl> 2642863Sktlim@umich.edubool 2652843Sktlim@umich.eduDefaultRename<Impl>::drain() 2661060SN/A{ 2672348SN/A // Rename is ready to switch out at any time. 2682843Sktlim@umich.edu cpu->signalDrained(); 2692863Sktlim@umich.edu return true; 2702316SN/A} 2711060SN/A 2722316SN/Atemplate <class Impl> 2732316SN/Avoid 2742843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2752316SN/A{ 2762348SN/A // Clear any state, fix up the rename map. 2772307SN/A for (int i = 0; i < numThreads; i++) { 2782980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 2792980Sgblack@eecs.umich.edu historyBuffer[i].begin(); 2802307SN/A 2812307SN/A while (!historyBuffer[i].empty()) { 2822307SN/A assert(hb_it != historyBuffer[i].end()); 2832307SN/A 2842307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2852307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2862307SN/A 2872307SN/A // Tell the rename map to set the architected register to the 2882307SN/A // previous physical register that it was renamed to. 2892307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2902307SN/A 2912307SN/A // Put the renamed physical register back on the free list. 2922307SN/A freeList->addReg(hb_it->newPhysReg); 2932307SN/A 2942361SN/A // Be sure to mark its register as ready if it's a misc register. 2952361SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 2962361SN/A scoreboard->setReg(hb_it->newPhysReg); 2972361SN/A } 2982361SN/A 2992307SN/A historyBuffer[i].erase(hb_it++); 3002307SN/A } 3012307SN/A insts[i].clear(); 3022307SN/A skidBuffer[i].clear(); 3031060SN/A } 3041060SN/A} 3051060SN/A 3061061SN/Atemplate <class Impl> 3071060SN/Avoid 3082307SN/ADefaultRename<Impl>::takeOverFrom() 3091060SN/A{ 3102307SN/A _status = Inactive; 3112307SN/A initStage(); 3121060SN/A 3132329SN/A // Reset all state prior to taking over from the other CPU. 3142307SN/A for (int i=0; i< numThreads; i++) { 3152307SN/A renameStatus[i] = Idle; 3161060SN/A 3172307SN/A stalls[i].iew = false; 3182307SN/A stalls[i].commit = false; 3192307SN/A serializeInst[i] = NULL; 3202307SN/A 3212307SN/A instsInProgress[i] = 0; 3222307SN/A 3232307SN/A emptyROB[i] = true; 3242307SN/A 3252307SN/A serializeOnNextInst[i] = false; 3262307SN/A } 3272307SN/A} 3282307SN/A 3292307SN/Atemplate <class Impl> 3302307SN/Avoid 3312935Sksewell@umich.eduDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid) 3321858SN/A{ 3332292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3341858SN/A 3352292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3362292SN/A // If it still needs to block, the blocking should happen the next 3372292SN/A // cycle and there should be space to hold everything due to the squash. 3382292SN/A if (renameStatus[tid] == Blocked || 3393788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3402292SN/A toDecode->renameUnblock[tid] = 1; 3412698Sktlim@umich.edu 3423788Sgblack@eecs.umich.edu resumeSerialize = false; 3432301SN/A serializeInst[tid] = NULL; 3443788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3453788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3463788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3473788Sgblack@eecs.umich.edu resumeSerialize = true; 3483788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3493788Sgblack@eecs.umich.edu } else { 3503788Sgblack@eecs.umich.edu resumeSerialize = false; 3513788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3523788Sgblack@eecs.umich.edu 3533788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3543788Sgblack@eecs.umich.edu } 3552292SN/A } 3562292SN/A 3572292SN/A // Set the status to Squashing. 3582292SN/A renameStatus[tid] = Squashing; 3592292SN/A 3602329SN/A // Squash any instructions from decode. 3612292SN/A unsigned squashCount = 0; 3622292SN/A 3632292SN/A for (int i=0; i<fromDecode->size; i++) { 3642935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3652935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3662731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3672292SN/A wroteToTimeBuffer = true; 3682292SN/A squashCount++; 3692292SN/A } 3702935Sksewell@umich.edu 3712292SN/A } 3722292SN/A 3732935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3742935Sksewell@umich.edu // insts in them. Since we support multiple ISAs, we cant just: 3752935Sksewell@umich.edu // "insts[tid].clear();" or "skidBuffer[tid].clear()" since there is 3762935Sksewell@umich.edu // a possible delay slot inst for different architectures 3772935Sksewell@umich.edu // insts[tid].clear(); 3783093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3792935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming decode instructions until " 3802935Sksewell@umich.edu "[sn:%i].\n",tid, squash_seq_num); 3812935Sksewell@umich.edu ListIt ilist_it = insts[tid].begin(); 3822935Sksewell@umich.edu while (ilist_it != insts[tid].end()) { 3832935Sksewell@umich.edu if ((*ilist_it)->seqNum > squash_seq_num) { 3842935Sksewell@umich.edu (*ilist_it)->setSquashed(); 3852935Sksewell@umich.edu DPRINTF(Rename, "Squashing incoming decode instruction, " 3862935Sksewell@umich.edu "[tid:%i] [sn:%i] PC %08p.\n", tid, (*ilist_it)->seqNum, (*ilist_it)->PC); 3872935Sksewell@umich.edu } 3882935Sksewell@umich.edu ilist_it++; 3892935Sksewell@umich.edu } 3903093Sksewell@umich.edu#else 3913093Sksewell@umich.edu insts[tid].clear(); 3922935Sksewell@umich.edu#endif 3932292SN/A 3942292SN/A // Clear the skid buffer in case it has any data in it. 3952935Sksewell@umich.edu // See comments above. 3962935Sksewell@umich.edu // skidBuffer[tid].clear(); 3973093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 3982935Sksewell@umich.edu DPRINTF(Rename, "[tid:%i] Squashing incoming skidbuffer instructions " 3992935Sksewell@umich.edu "until [sn:%i].\n", tid, squash_seq_num); 4002935Sksewell@umich.edu ListIt slist_it = skidBuffer[tid].begin(); 4012935Sksewell@umich.edu while (slist_it != skidBuffer[tid].end()) { 4022935Sksewell@umich.edu if ((*slist_it)->seqNum > squash_seq_num) { 4032935Sksewell@umich.edu (*slist_it)->setSquashed(); 4042935Sksewell@umich.edu DPRINTF(Rename, "Squashing skidbuffer instruction, [tid:%i] [sn:%i]" 4052935Sksewell@umich.edu "PC %08p.\n", tid, (*slist_it)->seqNum, (*slist_it)->PC); 4062935Sksewell@umich.edu } 4072935Sksewell@umich.edu slist_it++; 4082935Sksewell@umich.edu } 4093798Sgblack@eecs.umich.edu resumeUnblocking = (skidBuffer[tid].size() != 0); 4103798Sgblack@eecs.umich.edu DPRINTF(Rename, "Resume unblocking set to %s\n", 4113798Sgblack@eecs.umich.edu resumeUnblocking ? "true" : "false"); 4123093Sksewell@umich.edu#else 4133093Sksewell@umich.edu skidBuffer[tid].clear(); 4142935Sksewell@umich.edu#endif 4152935Sksewell@umich.edu doSquash(squash_seq_num, tid); 4162292SN/A} 4172292SN/A 4182292SN/Atemplate <class Impl> 4192292SN/Avoid 4202292SN/ADefaultRename<Impl>::tick() 4212292SN/A{ 4222292SN/A wroteToTimeBuffer = false; 4232292SN/A 4242292SN/A blockThisCycle = false; 4252292SN/A 4262292SN/A bool status_change = false; 4272292SN/A 4282292SN/A toIEWIndex = 0; 4292292SN/A 4302292SN/A sortInsts(); 4312292SN/A 4322980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 4332292SN/A 4342292SN/A // Check stall and squash signals. 4352292SN/A while (threads != (*activeThreads).end()) { 4362292SN/A unsigned tid = *threads++; 4372292SN/A 4382292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4392292SN/A 4402292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4412292SN/A 4422292SN/A rename(status_change, tid); 4432292SN/A } 4442292SN/A 4452292SN/A if (status_change) { 4462292SN/A updateStatus(); 4472292SN/A } 4482292SN/A 4492292SN/A if (wroteToTimeBuffer) { 4502292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4512292SN/A cpu->activityThisCycle(); 4522292SN/A } 4532292SN/A 4542292SN/A threads = (*activeThreads).begin(); 4552292SN/A 4562292SN/A while (threads != (*activeThreads).end()) { 4572292SN/A unsigned tid = *threads++; 4582292SN/A 4592292SN/A // If we committed this cycle then doneSeqNum will be > 0 4602292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4612292SN/A !fromCommit->commitInfo[tid].squash && 4622292SN/A renameStatus[tid] != Squashing) { 4632292SN/A 4642292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4652292SN/A tid); 4662292SN/A } 4672292SN/A } 4682292SN/A 4692292SN/A // @todo: make into updateProgress function 4702292SN/A for (int tid=0; tid < numThreads; tid++) { 4712292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4722292SN/A 4732292SN/A assert(instsInProgress[tid] >=0); 4742292SN/A } 4752292SN/A 4762292SN/A} 4772292SN/A 4782292SN/Atemplate<class Impl> 4792292SN/Avoid 4802292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4812292SN/A{ 4822292SN/A // If status is Running or idle, 4832292SN/A // call renameInsts() 4842292SN/A // If status is Unblocking, 4852292SN/A // buffer any instructions coming from decode 4862292SN/A // continue trying to empty skid buffer 4872292SN/A // check if stall conditions have passed 4882292SN/A 4892292SN/A if (renameStatus[tid] == Blocked) { 4902292SN/A ++renameBlockCycles; 4912292SN/A } else if (renameStatus[tid] == Squashing) { 4922292SN/A ++renameSquashCycles; 4932301SN/A } else if (renameStatus[tid] == SerializeStall) { 4942301SN/A ++renameSerializeStallCycles; 4953788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4963788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4973788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4983788Sgblack@eecs.umich.edu if (resumeSerialize) { 4993788Sgblack@eecs.umich.edu resumeSerialize = false; 5003788Sgblack@eecs.umich.edu block(tid); 5013788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5023788Sgblack@eecs.umich.edu } 5033798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 5043798Sgblack@eecs.umich.edu if (resumeUnblocking) { 5053798Sgblack@eecs.umich.edu block(tid); 5063798Sgblack@eecs.umich.edu resumeUnblocking = false; 5073798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5083798Sgblack@eecs.umich.edu } 5092292SN/A } 5102292SN/A 5112292SN/A if (renameStatus[tid] == Running || 5122292SN/A renameStatus[tid] == Idle) { 5132292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 5142292SN/A "stage.\n", tid); 5152292SN/A 5162292SN/A renameInsts(tid); 5172292SN/A } else if (renameStatus[tid] == Unblocking) { 5182292SN/A renameInsts(tid); 5192292SN/A 5202292SN/A if (validInsts()) { 5212292SN/A // Add the current inputs to the skid buffer so they can be 5222292SN/A // reprocessed when this stage unblocks. 5232292SN/A skidInsert(tid); 5242292SN/A } 5252292SN/A 5262292SN/A // If we switched over to blocking, then there's a potential for 5272292SN/A // an overall status change. 5282292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5291858SN/A } 5301858SN/A} 5311858SN/A 5321858SN/Atemplate <class Impl> 5331858SN/Avoid 5342292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 5351858SN/A{ 5362292SN/A // Instructions can be either in the skid buffer or the queue of 5372292SN/A // instructions coming from decode, depending on the status. 5382292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5392292SN/A skidBuffer[tid].size() : insts[tid].size(); 5401858SN/A 5412292SN/A // Check the decode queue to see if instructions are available. 5422292SN/A // If there are no available instructions to rename, then do nothing. 5432292SN/A if (insts_available == 0) { 5442292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5452292SN/A tid); 5462292SN/A // Should I change status to idle? 5472292SN/A ++renameIdleCycles; 5482292SN/A return; 5492292SN/A } else if (renameStatus[tid] == Unblocking) { 5502292SN/A ++renameUnblockCycles; 5512292SN/A } else if (renameStatus[tid] == Running) { 5522292SN/A ++renameRunCycles; 5532292SN/A } 5541858SN/A 5552292SN/A DynInstPtr inst; 5562292SN/A 5572292SN/A // Will have to do a different calculation for the number of free 5582292SN/A // entries. 5592292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5602292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5612292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5622292SN/A int min_free_entries = free_rob_entries; 5632292SN/A 5642292SN/A FullSource source = ROB; 5652292SN/A 5662292SN/A if (free_iq_entries < min_free_entries) { 5672292SN/A min_free_entries = free_iq_entries; 5682292SN/A source = IQ; 5692292SN/A } 5702292SN/A 5712292SN/A if (free_lsq_entries < min_free_entries) { 5722292SN/A min_free_entries = free_lsq_entries; 5732292SN/A source = LSQ; 5742292SN/A } 5752292SN/A 5762292SN/A // Check if there's any space left. 5772292SN/A if (min_free_entries <= 0) { 5782292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5792292SN/A "entries.\n" 5802292SN/A "ROB has %i free entries.\n" 5812292SN/A "IQ has %i free entries.\n" 5822292SN/A "LSQ has %i free entries.\n", 5832292SN/A tid, 5842292SN/A free_rob_entries, 5852292SN/A free_iq_entries, 5862292SN/A free_lsq_entries); 5872292SN/A 5882292SN/A blockThisCycle = true; 5892292SN/A 5902292SN/A block(tid); 5912292SN/A 5922292SN/A incrFullStat(source); 5932292SN/A 5942292SN/A return; 5952292SN/A } else if (min_free_entries < insts_available) { 5962292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5972292SN/A "%i insts available, but only %i insts can be " 5982292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5992292SN/A tid, insts_available, min_free_entries); 6002292SN/A 6012292SN/A insts_available = min_free_entries; 6022292SN/A 6032292SN/A blockThisCycle = true; 6042292SN/A 6052292SN/A incrFullStat(source); 6062292SN/A } 6072292SN/A 6082292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 6092292SN/A skidBuffer[tid] : insts[tid]; 6102292SN/A 6112292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 6122292SN/A "send iew.\n", tid, insts_available); 6132292SN/A 6142292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 6152292SN/A "dispatched to IQ last cycle.\n", 6162292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 6172292SN/A 6182292SN/A // Handle serializing the next instruction if necessary. 6192292SN/A if (serializeOnNextInst[tid]) { 6202292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 6212292SN/A // ROB already empty; no need to serialize. 6222292SN/A serializeOnNextInst[tid] = false; 6232292SN/A } else if (!insts_to_rename.empty()) { 6242292SN/A insts_to_rename.front()->setSerializeBefore(); 6252292SN/A } 6262292SN/A } 6272292SN/A 6282292SN/A int renamed_insts = 0; 6292292SN/A 6302292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6312292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6322292SN/A 6332292SN/A assert(!insts_to_rename.empty()); 6342292SN/A 6352292SN/A inst = insts_to_rename.front(); 6362292SN/A 6372292SN/A insts_to_rename.pop_front(); 6382292SN/A 6392292SN/A if (renameStatus[tid] == Unblocking) { 6402292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 6412292SN/A "skidBuffer\n", 6422292SN/A tid, inst->seqNum, inst->readPC()); 6432292SN/A } 6442292SN/A 6452292SN/A if (inst->isSquashed()) { 6462292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 6472292SN/A "squashed, skipping.\n", 6482935Sksewell@umich.edu tid, inst->seqNum, inst->readPC()); 6492292SN/A 6502292SN/A ++renameSquashedInsts; 6512292SN/A 6522292SN/A // Decrement how many instructions are available. 6532292SN/A --insts_available; 6542292SN/A 6552292SN/A continue; 6562292SN/A } 6572292SN/A 6582292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6592292SN/A "PC %#x.\n", 6602292SN/A tid, inst->seqNum, inst->readPC()); 6612292SN/A 6622292SN/A // Handle serializeAfter/serializeBefore instructions. 6632292SN/A // serializeAfter marks the next instruction as serializeBefore. 6642292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6652292SN/A // is empty. 6662336SN/A 6672336SN/A // In this model, IPR accesses are serialize before 6682336SN/A // instructions, and store conditionals are serialize after 6692336SN/A // instructions. This is mainly due to lack of support for 6702336SN/A // out-of-order operations of either of those classes of 6712336SN/A // instructions. 6722336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6732336SN/A !inst->isSerializeHandled()) { 6742292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6752292SN/A 6762301SN/A if (!inst->isTempSerializeBefore()) { 6772301SN/A renamedSerializing++; 6782292SN/A inst->setSerializeHandled(); 6792301SN/A } else { 6802301SN/A renamedTempSerializing++; 6812301SN/A } 6822292SN/A 6832301SN/A // Change status over to SerializeStall so that other stages know 6842292SN/A // what this is blocked on. 6852301SN/A renameStatus[tid] = SerializeStall; 6862292SN/A 6872301SN/A serializeInst[tid] = inst; 6882292SN/A 6892292SN/A blockThisCycle = true; 6902292SN/A 6912292SN/A break; 6922336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6932336SN/A !inst->isSerializeHandled()) { 6942292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6952292SN/A 6962307SN/A renamedSerializing++; 6972307SN/A 6982292SN/A inst->setSerializeHandled(); 6992292SN/A 7002292SN/A serializeAfter(insts_to_rename, tid); 7012292SN/A } 7022292SN/A 7032292SN/A // Check here to make sure there are enough destination registers 7042292SN/A // to rename to. Otherwise block. 7052292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 7062292SN/A DPRINTF(Rename, "Blocking due to lack of free " 7072292SN/A "physical registers to rename to.\n"); 7082292SN/A blockThisCycle = true; 7092292SN/A 7102292SN/A ++renameFullRegistersEvents; 7112292SN/A 7122292SN/A break; 7132292SN/A } 7142292SN/A 7152292SN/A renameSrcRegs(inst, inst->threadNumber); 7162292SN/A 7172292SN/A renameDestRegs(inst, inst->threadNumber); 7182292SN/A 7192292SN/A ++renamed_insts; 7202292SN/A 7212292SN/A // Put instruction in rename queue. 7222292SN/A toIEW->insts[toIEWIndex] = inst; 7232292SN/A ++(toIEW->size); 7242292SN/A 7252292SN/A // Increment which instruction we're on. 7262292SN/A ++toIEWIndex; 7272292SN/A 7282292SN/A // Decrement how many instructions are available. 7292292SN/A --insts_available; 7302292SN/A } 7312292SN/A 7322292SN/A instsInProgress[tid] += renamed_insts; 7332307SN/A renameRenamedInsts += renamed_insts; 7342292SN/A 7352292SN/A // If we wrote to the time buffer, record this. 7362292SN/A if (toIEWIndex) { 7372292SN/A wroteToTimeBuffer = true; 7382292SN/A } 7392292SN/A 7402292SN/A // Check if there's any instructions left that haven't yet been renamed. 7412292SN/A // If so then block. 7422292SN/A if (insts_available) { 7432292SN/A blockThisCycle = true; 7442292SN/A } 7452292SN/A 7462292SN/A if (blockThisCycle) { 7472292SN/A block(tid); 7482292SN/A toDecode->renameUnblock[tid] = false; 7492292SN/A } 7502292SN/A} 7512292SN/A 7522292SN/Atemplate<class Impl> 7532292SN/Avoid 7542292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 7552292SN/A{ 7562292SN/A DynInstPtr inst = NULL; 7572292SN/A 7582292SN/A while (!insts[tid].empty()) { 7592292SN/A inst = insts[tid].front(); 7602292SN/A 7612292SN/A insts[tid].pop_front(); 7622292SN/A 7632292SN/A assert(tid == inst->threadNumber); 7642292SN/A 7652292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 7662292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 7672292SN/A 7682307SN/A ++renameSkidInsts; 7692307SN/A 7702292SN/A skidBuffer[tid].push_back(inst); 7712292SN/A } 7722292SN/A 7732292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7743798Sgblack@eecs.umich.edu { 7753798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7763798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7773798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7783798Sgblack@eecs.umich.edu { 7793798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7803798Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->readPC()), 7813798Sgblack@eecs.umich.edu (*it)->seqNum); 7823798Sgblack@eecs.umich.edu } 7832292SN/A panic("Skidbuffer Exceeded Max Size"); 7843798Sgblack@eecs.umich.edu } 7852292SN/A} 7862292SN/A 7872292SN/Atemplate <class Impl> 7882292SN/Avoid 7892292SN/ADefaultRename<Impl>::sortInsts() 7902292SN/A{ 7912292SN/A int insts_from_decode = fromDecode->size; 7922329SN/A#ifdef DEBUG 7933093Sksewell@umich.edu#if !ISA_HAS_DELAY_SLOT 7942292SN/A for (int i=0; i < numThreads; i++) 7952292SN/A assert(insts[i].empty()); 7962329SN/A#endif 7972935Sksewell@umich.edu#endif 7982292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7992292SN/A DynInstPtr inst = fromDecode->insts[i]; 8002292SN/A insts[inst->threadNumber].push_back(inst); 8012292SN/A } 8022292SN/A} 8032292SN/A 8042292SN/Atemplate<class Impl> 8052292SN/Abool 8062292SN/ADefaultRename<Impl>::skidsEmpty() 8072292SN/A{ 8082980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 8092292SN/A 8102292SN/A while (threads != (*activeThreads).end()) { 8112292SN/A if (!skidBuffer[*threads++].empty()) 8122292SN/A return false; 8132292SN/A } 8142292SN/A 8152292SN/A return true; 8162292SN/A} 8172292SN/A 8182292SN/Atemplate<class Impl> 8192292SN/Avoid 8202292SN/ADefaultRename<Impl>::updateStatus() 8212292SN/A{ 8222292SN/A bool any_unblocking = false; 8232292SN/A 8242980Sgblack@eecs.umich.edu std::list<unsigned>::iterator threads = (*activeThreads).begin(); 8252292SN/A 8262292SN/A threads = (*activeThreads).begin(); 8272292SN/A 8282292SN/A while (threads != (*activeThreads).end()) { 8292292SN/A unsigned tid = *threads++; 8302292SN/A 8312292SN/A if (renameStatus[tid] == Unblocking) { 8322292SN/A any_unblocking = true; 8332292SN/A break; 8342292SN/A } 8352292SN/A } 8362292SN/A 8372292SN/A // Rename will have activity if it's unblocking. 8382292SN/A if (any_unblocking) { 8392292SN/A if (_status == Inactive) { 8402292SN/A _status = Active; 8412292SN/A 8422292SN/A DPRINTF(Activity, "Activating stage.\n"); 8432292SN/A 8442733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8452292SN/A } 8462292SN/A } else { 8472292SN/A // If it's not unblocking, then rename will not have any internal 8482292SN/A // activity. Switch it to inactive. 8492292SN/A if (_status == Active) { 8502292SN/A _status = Inactive; 8512292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8522292SN/A 8532733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8542292SN/A } 8552292SN/A } 8562292SN/A} 8572292SN/A 8582292SN/Atemplate <class Impl> 8592292SN/Abool 8602292SN/ADefaultRename<Impl>::block(unsigned tid) 8612292SN/A{ 8622292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8632292SN/A 8642292SN/A // Add the current inputs onto the skid buffer, so they can be 8652292SN/A // reprocessed when this stage unblocks. 8662292SN/A skidInsert(tid); 8672292SN/A 8682292SN/A // Only signal backwards to block if the previous stages do not think 8692292SN/A // rename is already blocked. 8702292SN/A if (renameStatus[tid] != Blocked) { 8713798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8723798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8733798Sgblack@eecs.umich.edu // stages to block. 8743798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8752292SN/A toDecode->renameBlock[tid] = true; 8762292SN/A toDecode->renameUnblock[tid] = false; 8772292SN/A wroteToTimeBuffer = true; 8782292SN/A } 8792292SN/A 8802329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8812329SN/A // it would not know to complete the serialize stall. 8822301SN/A if (renameStatus[tid] != SerializeStall) { 8832292SN/A // Set status to Blocked. 8842292SN/A renameStatus[tid] = Blocked; 8852292SN/A return true; 8862292SN/A } 8872292SN/A } 8882292SN/A 8892292SN/A return false; 8902292SN/A} 8912292SN/A 8922292SN/Atemplate <class Impl> 8932292SN/Abool 8942292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8952292SN/A{ 8962292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8972292SN/A 8982292SN/A // Rename is done unblocking if the skid buffer is empty. 8992301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 9002292SN/A 9012292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 9022292SN/A 9032292SN/A toDecode->renameUnblock[tid] = true; 9042292SN/A wroteToTimeBuffer = true; 9052292SN/A 9062292SN/A renameStatus[tid] = Running; 9072292SN/A return true; 9082292SN/A } 9092292SN/A 9102292SN/A return false; 9112292SN/A} 9122292SN/A 9132292SN/Atemplate <class Impl> 9142292SN/Avoid 9152935Sksewell@umich.eduDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid) 9162292SN/A{ 9172980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9182980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9192292SN/A 9201060SN/A // After a syscall squashes everything, the history buffer may be empty 9211060SN/A // but the ROB may still be squashing instructions. 9222292SN/A if (historyBuffer[tid].empty()) { 9231060SN/A return; 9241060SN/A } 9251060SN/A 9261060SN/A // Go through the most recent instructions, undoing the mappings 9271060SN/A // they did and freeing up the registers. 9282292SN/A while (!historyBuffer[tid].empty() && 9292292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 9302292SN/A assert(hb_it != historyBuffer[tid].end()); 9311062SN/A 9322292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9332292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 9341060SN/A 9352292SN/A // Tell the rename map to set the architected register to the 9362292SN/A // previous physical register that it was renamed to. 9372292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9381060SN/A 9392292SN/A // Put the renamed physical register back on the free list. 9402292SN/A freeList->addReg(hb_it->newPhysReg); 9411062SN/A 9422367SN/A // Be sure to mark its register as ready if it's a misc register. 9432367SN/A if (hb_it->newPhysReg >= maxPhysicalRegs) { 9442367SN/A scoreboard->setReg(hb_it->newPhysReg); 9452367SN/A } 9462367SN/A 9472292SN/A historyBuffer[tid].erase(hb_it++); 9481061SN/A 9491062SN/A ++renameUndoneMaps; 9501060SN/A } 9511060SN/A} 9521060SN/A 9531060SN/Atemplate<class Impl> 9541060SN/Avoid 9552292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 9561060SN/A{ 9572292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9582292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9592292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9602292SN/A 9612980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9622980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9631060SN/A 9641061SN/A --hb_it; 9651060SN/A 9662292SN/A if (historyBuffer[tid].empty()) { 9672292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9682292SN/A return; 9692292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9702292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9712292SN/A "that a syscall happened recently.\n", tid); 9721060SN/A return; 9731060SN/A } 9741060SN/A 9752292SN/A // Commit all the renames up until (and including) the committed sequence 9762292SN/A // number. Some or even all of the committed instructions may not have 9772292SN/A // rename histories if they did not have destination registers that were 9782292SN/A // renamed. 9792292SN/A while (!historyBuffer[tid].empty() && 9802292SN/A hb_it != historyBuffer[tid].end() && 9812292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 9821060SN/A 9832329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9842329SN/A "[sn:%lli].\n", 9852292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 9861061SN/A 9872292SN/A freeList->addReg((*hb_it).prevPhysReg); 9882292SN/A ++renameCommittedMaps; 9891061SN/A 9902292SN/A historyBuffer[tid].erase(hb_it--); 9911060SN/A } 9921060SN/A} 9931060SN/A 9941061SN/Atemplate <class Impl> 9951061SN/Ainline void 9962292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9971061SN/A{ 9982292SN/A assert(renameMap[tid] != 0); 9992292SN/A 10001061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10011061SN/A 10021061SN/A // Get the architectual register numbers from the source and 10031061SN/A // destination operands, and redirect them to the right register. 10041061SN/A // Will need to mark dependencies though. 10052292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 10061061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 10073773Sgblack@eecs.umich.edu RegIndex flat_src_reg = src_reg; 10083773Sgblack@eecs.umich.edu if (src_reg < TheISA::FP_Base_DepTag) { 10093773Sgblack@eecs.umich.edu flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); 10103773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); 10113773Sgblack@eecs.umich.edu } 10123773Sgblack@eecs.umich.edu inst->flattenSrcReg(src_idx, flat_src_reg); 10131061SN/A 10141061SN/A // Look up the source registers to get the phys. register they've 10151061SN/A // been renamed to, and set the sources to those registers. 10163773Sgblack@eecs.umich.edu PhysRegIndex renamed_reg = renameMap[tid]->lookup(flat_src_reg); 10171061SN/A 10182292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 10193773Sgblack@eecs.umich.edu "physical reg %i.\n", tid, (int)flat_src_reg, 10202292SN/A (int)renamed_reg); 10211061SN/A 10221061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10231061SN/A 10242292SN/A // See if the register is ready or not. 10252292SN/A if (scoreboard->getReg(renamed_reg) == true) { 10262292SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 10271061SN/A 10281061SN/A inst->markSrcRegReady(src_idx); 10291061SN/A } 10301062SN/A 10311062SN/A ++renameRenameLookups; 10321061SN/A } 10331061SN/A} 10341061SN/A 10351061SN/Atemplate <class Impl> 10361061SN/Ainline void 10372292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 10381061SN/A{ 10392292SN/A typename RenameMap::RenameInfo rename_result; 10401061SN/A 10411061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10421061SN/A 10432292SN/A // Rename the destination registers. 10442292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10452292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10463773Sgblack@eecs.umich.edu RegIndex flat_dest_reg = dest_reg; 10473773Sgblack@eecs.umich.edu if (dest_reg < TheISA::FP_Base_DepTag) { 10483773Sgblack@eecs.umich.edu flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); 10493773Sgblack@eecs.umich.edu DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); 10503773Sgblack@eecs.umich.edu } 10513773Sgblack@eecs.umich.edu 10523773Sgblack@eecs.umich.edu inst->flattenDestReg(dest_idx, flat_dest_reg); 10531061SN/A 10542292SN/A // Get the physical register that the destination will be 10552292SN/A // renamed to. 10563773Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(flat_dest_reg); 10571061SN/A 10582292SN/A //Mark Scoreboard entry as not ready 10592292SN/A scoreboard->unsetReg(rename_result.first); 10601062SN/A 10612292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10623773Sgblack@eecs.umich.edu "reg %i.\n", tid, (int)flat_dest_reg, 10632292SN/A (int)rename_result.first); 10641062SN/A 10652292SN/A // Record the rename information so that a history can be kept. 10663773Sgblack@eecs.umich.edu RenameHistory hb_entry(inst->seqNum, flat_dest_reg, 10672292SN/A rename_result.first, 10682292SN/A rename_result.second); 10691062SN/A 10702292SN/A historyBuffer[tid].push_front(hb_entry); 10711062SN/A 10722935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10732935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10742935Sksewell@umich.edu historyBuffer[tid].size(), 10752292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10761062SN/A 10772292SN/A // Tell the instruction to rename the appropriate destination 10782292SN/A // register (dest_idx) to the new physical register 10792292SN/A // (rename_result.first), and record the previous physical 10802292SN/A // register that the same logical register was renamed to 10812292SN/A // (rename_result.second). 10822292SN/A inst->renameDestReg(dest_idx, 10832292SN/A rename_result.first, 10842292SN/A rename_result.second); 10851062SN/A 10862292SN/A ++renameRenamedOperands; 10871061SN/A } 10881061SN/A} 10891061SN/A 10901061SN/Atemplate <class Impl> 10911061SN/Ainline int 10922292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 10931061SN/A{ 10942292SN/A int num_free = freeEntries[tid].robEntries - 10952292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10962292SN/A 10972292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 10982292SN/A 10992292SN/A return num_free; 11001061SN/A} 11011061SN/A 11021061SN/Atemplate <class Impl> 11031061SN/Ainline int 11042292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 11051061SN/A{ 11062292SN/A int num_free = freeEntries[tid].iqEntries - 11072292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11082292SN/A 11092292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11102292SN/A 11112292SN/A return num_free; 11122292SN/A} 11132292SN/A 11142292SN/Atemplate <class Impl> 11152292SN/Ainline int 11162292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 11172292SN/A{ 11182292SN/A int num_free = freeEntries[tid].lsqEntries - 11192292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11202292SN/A 11212292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11222292SN/A 11232292SN/A return num_free; 11242292SN/A} 11252292SN/A 11262292SN/Atemplate <class Impl> 11272292SN/Aunsigned 11282292SN/ADefaultRename<Impl>::validInsts() 11292292SN/A{ 11302292SN/A unsigned inst_count = 0; 11312292SN/A 11322292SN/A for (int i=0; i<fromDecode->size; i++) { 11332731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11342292SN/A inst_count++; 11352292SN/A } 11362292SN/A 11372292SN/A return inst_count; 11382292SN/A} 11392292SN/A 11402292SN/Atemplate <class Impl> 11412292SN/Avoid 11422292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 11432292SN/A{ 11442292SN/A if (fromIEW->iewBlock[tid]) { 11452292SN/A stalls[tid].iew = true; 11462292SN/A } 11472292SN/A 11482292SN/A if (fromIEW->iewUnblock[tid]) { 11492292SN/A assert(stalls[tid].iew); 11502292SN/A stalls[tid].iew = false; 11512292SN/A } 11522292SN/A 11532292SN/A if (fromCommit->commitBlock[tid]) { 11542292SN/A stalls[tid].commit = true; 11552292SN/A } 11562292SN/A 11572292SN/A if (fromCommit->commitUnblock[tid]) { 11582292SN/A assert(stalls[tid].commit); 11592292SN/A stalls[tid].commit = false; 11602292SN/A } 11612292SN/A} 11622292SN/A 11632292SN/Atemplate <class Impl> 11642292SN/Abool 11652292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 11662292SN/A{ 11672292SN/A bool ret_val = false; 11682292SN/A 11692292SN/A if (stalls[tid].iew) { 11702292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11712292SN/A ret_val = true; 11722292SN/A } else if (stalls[tid].commit) { 11732292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11742292SN/A ret_val = true; 11752292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11762292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11772292SN/A ret_val = true; 11782292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11792292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11802292SN/A ret_val = true; 11812292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11822292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11832292SN/A ret_val = true; 11842292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11852292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11862292SN/A ret_val = true; 11872301SN/A } else if (renameStatus[tid] == SerializeStall && 11882292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11892301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11902292SN/A "empty.\n", 11912292SN/A tid); 11922292SN/A ret_val = true; 11932292SN/A } 11942292SN/A 11952292SN/A return ret_val; 11962292SN/A} 11972292SN/A 11982292SN/Atemplate <class Impl> 11992292SN/Avoid 12002292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 12012292SN/A{ 12022292SN/A bool updated = false; 12032292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 12042292SN/A freeEntries[tid].iqEntries = 12052292SN/A fromIEW->iewInfo[tid].freeIQEntries; 12062292SN/A updated = true; 12072292SN/A } 12082292SN/A 12092292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 12102292SN/A freeEntries[tid].lsqEntries = 12112292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 12122292SN/A updated = true; 12132292SN/A } 12142292SN/A 12152292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12162292SN/A freeEntries[tid].robEntries = 12172292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12182292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12192292SN/A updated = true; 12202292SN/A } 12212292SN/A 12222292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12232292SN/A tid, 12242292SN/A freeEntries[tid].iqEntries, 12252292SN/A freeEntries[tid].robEntries, 12262292SN/A freeEntries[tid].lsqEntries); 12272292SN/A 12282292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12292292SN/A tid, instsInProgress[tid]); 12302292SN/A} 12312292SN/A 12322292SN/Atemplate <class Impl> 12332292SN/Abool 12342292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 12352292SN/A{ 12362292SN/A // Check if there's a squash signal, squash if there is 12372292SN/A // Check stall signals, block if necessary. 12382292SN/A // If status was blocked 12392292SN/A // check if stall conditions have passed 12402292SN/A // if so then go to unblocking 12412292SN/A // If status was Squashing 12422292SN/A // check if squashing is not high. Switch to running this cycle. 12432301SN/A // If status was serialize stall 12442292SN/A // check if ROB is empty and no insts are in flight to the ROB 12452292SN/A 12462292SN/A readFreeEntries(tid); 12472292SN/A readStallSignals(tid); 12482292SN/A 12492292SN/A if (fromCommit->commitInfo[tid].squash) { 12502292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12512292SN/A "commit.\n", tid); 12522292SN/A 12533093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 12543093Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 12553093Sksewell@umich.edu#else 12562935Sksewell@umich.edu InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 12572935Sksewell@umich.edu#endif 12582935Sksewell@umich.edu 12592935Sksewell@umich.edu squash(squashed_seq_num, tid); 12602292SN/A 12612292SN/A return true; 12622292SN/A } 12632292SN/A 12642292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12652292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12662292SN/A 12672292SN/A renameStatus[tid] = Squashing; 12682292SN/A 12692292SN/A return true; 12702292SN/A } 12712292SN/A 12722292SN/A if (checkStall(tid)) { 12732292SN/A return block(tid); 12742292SN/A } 12752292SN/A 12762292SN/A if (renameStatus[tid] == Blocked) { 12772292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12782292SN/A tid); 12792292SN/A 12802292SN/A renameStatus[tid] = Unblocking; 12812292SN/A 12822292SN/A unblock(tid); 12832292SN/A 12842292SN/A return true; 12852292SN/A } 12862292SN/A 12872292SN/A if (renameStatus[tid] == Squashing) { 12882292SN/A // Switch status to running if rename isn't being told to block or 12892292SN/A // squash this cycle. 12903798Sgblack@eecs.umich.edu if (resumeSerialize) { 12913798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12923798Sgblack@eecs.umich.edu tid); 12933798Sgblack@eecs.umich.edu 12943798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12953798Sgblack@eecs.umich.edu return true; 12963798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12973798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12983798Sgblack@eecs.umich.edu tid); 12993798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13003798Sgblack@eecs.umich.edu return true; 13013798Sgblack@eecs.umich.edu } else { 13023788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13033788Sgblack@eecs.umich.edu tid); 13042292SN/A 13053788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13063788Sgblack@eecs.umich.edu return false; 13073788Sgblack@eecs.umich.edu } 13082292SN/A } 13092292SN/A 13102301SN/A if (renameStatus[tid] == SerializeStall) { 13112292SN/A // Stall ends once the ROB is free. 13122301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13132292SN/A "unblocking.\n", tid); 13142292SN/A 13152301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13162292SN/A 13172292SN/A renameStatus[tid] = Unblocking; 13182292SN/A 13192292SN/A unblock(tid); 13202292SN/A 13212292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13222292SN/A "PC %#x.\n", 13232301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 13242292SN/A 13252292SN/A // Put instruction into queue here. 13262301SN/A serial_inst->clearSerializeBefore(); 13272292SN/A 13282292SN/A if (!skidBuffer[tid].empty()) { 13292301SN/A skidBuffer[tid].push_front(serial_inst); 13302292SN/A } else { 13312301SN/A insts[tid].push_front(serial_inst); 13322292SN/A } 13332292SN/A 13342292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13352703Sktlim@umich.edu " Adding to front of list.\n", tid); 13362292SN/A 13372301SN/A serializeInst[tid] = NULL; 13382292SN/A 13392292SN/A return true; 13402292SN/A } 13412292SN/A 13422292SN/A // If we've reached this point, we have not gotten any signals that 13432292SN/A // cause rename to change its status. Rename remains the same as before. 13442292SN/A return false; 13451061SN/A} 13461061SN/A 13471060SN/Atemplate<class Impl> 13481060SN/Avoid 13492292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 13502292SN/A unsigned tid) 13511060SN/A{ 13522292SN/A if (inst_list.empty()) { 13532292SN/A // Mark a bit to say that I must serialize on the next instruction. 13542292SN/A serializeOnNextInst[tid] = true; 13551060SN/A return; 13561060SN/A } 13571060SN/A 13582292SN/A // Set the next instruction as serializing. 13592292SN/A inst_list.front()->setSerializeBefore(); 13602292SN/A} 13612292SN/A 13622292SN/Atemplate <class Impl> 13632292SN/Ainline void 13642292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13652292SN/A{ 13662292SN/A switch (source) { 13672292SN/A case ROB: 13682292SN/A ++renameROBFullEvents; 13692292SN/A break; 13702292SN/A case IQ: 13712292SN/A ++renameIQFullEvents; 13722292SN/A break; 13732292SN/A case LSQ: 13742292SN/A ++renameLSQFullEvents; 13752292SN/A break; 13762292SN/A default: 13772292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13782292SN/A break; 13791060SN/A } 13802292SN/A} 13811060SN/A 13822292SN/Atemplate <class Impl> 13832292SN/Avoid 13842292SN/ADefaultRename<Impl>::dumpHistory() 13852292SN/A{ 13862980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13871060SN/A 13882292SN/A for (int i = 0; i < numThreads; i++) { 13891060SN/A 13902292SN/A buf_it = historyBuffer[i].begin(); 13911060SN/A 13922292SN/A while (buf_it != historyBuffer[i].end()) { 13932292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13942292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13952292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13961060SN/A 13972292SN/A buf_it++; 13981062SN/A } 13991060SN/A } 14001060SN/A} 1401