rename_impl.hh revision 2863
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A#include <list> 321060SN/A 331858SN/A#include "config/full_system.hh" 341717SN/A#include "cpu/o3/rename.hh" 351060SN/A 362292SN/Ausing namespace std; 372292SN/A 381061SN/Atemplate <class Impl> 392292SN/ADefaultRename<Impl>::DefaultRename(Params *params) 402292SN/A : iewToRenameDelay(params->iewToRenameDelay), 412292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 422292SN/A commitToRenameDelay(params->commitToRenameDelay), 432292SN/A renameWidth(params->renameWidth), 442292SN/A commitWidth(params->commitWidth), 452292SN/A numThreads(params->numberOfThreads) 461060SN/A{ 472292SN/A _status = Inactive; 482292SN/A 492292SN/A for (int i=0; i< numThreads; i++) { 502292SN/A renameStatus[i] = Idle; 512292SN/A 522292SN/A freeEntries[i].iqEntries = 0; 532292SN/A freeEntries[i].lsqEntries = 0; 542292SN/A freeEntries[i].robEntries = 0; 552292SN/A 562292SN/A stalls[i].iew = false; 572292SN/A stalls[i].commit = false; 582301SN/A serializeInst[i] = NULL; 592292SN/A 602292SN/A instsInProgress[i] = 0; 612292SN/A 622292SN/A emptyROB[i] = true; 632292SN/A 642292SN/A serializeOnNextInst[i] = false; 652292SN/A } 662292SN/A 672292SN/A // @todo: Make into a parameter. 682292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Astd::string 732292SN/ADefaultRename<Impl>::name() const 742292SN/A{ 752292SN/A return cpu->name() + ".rename"; 761060SN/A} 771060SN/A 781061SN/Atemplate <class Impl> 791060SN/Avoid 802292SN/ADefaultRename<Impl>::regStats() 811062SN/A{ 821062SN/A renameSquashCycles 832301SN/A .name(name() + ".RENAME:SquashCycles") 841062SN/A .desc("Number of cycles rename is squashing") 851062SN/A .prereq(renameSquashCycles); 861062SN/A renameIdleCycles 872301SN/A .name(name() + ".RENAME:IdleCycles") 881062SN/A .desc("Number of cycles rename is idle") 891062SN/A .prereq(renameIdleCycles); 901062SN/A renameBlockCycles 912301SN/A .name(name() + ".RENAME:BlockCycles") 921062SN/A .desc("Number of cycles rename is blocking") 931062SN/A .prereq(renameBlockCycles); 942301SN/A renameSerializeStallCycles 952301SN/A .name(name() + ".RENAME:serializeStallCycles") 962301SN/A .desc("count of cycles rename stalled for serializing inst") 972301SN/A .flags(Stats::total); 982292SN/A renameRunCycles 992301SN/A .name(name() + ".RENAME:RunCycles") 1002292SN/A .desc("Number of cycles rename is running") 1012292SN/A .prereq(renameIdleCycles); 1021062SN/A renameUnblockCycles 1032301SN/A .name(name() + ".RENAME:UnblockCycles") 1041062SN/A .desc("Number of cycles rename is unblocking") 1051062SN/A .prereq(renameUnblockCycles); 1061062SN/A renameRenamedInsts 1072301SN/A .name(name() + ".RENAME:RenamedInsts") 1081062SN/A .desc("Number of instructions processed by rename") 1091062SN/A .prereq(renameRenamedInsts); 1101062SN/A renameSquashedInsts 1112301SN/A .name(name() + ".RENAME:SquashedInsts") 1121062SN/A .desc("Number of squashed instructions processed by rename") 1131062SN/A .prereq(renameSquashedInsts); 1141062SN/A renameROBFullEvents 1152301SN/A .name(name() + ".RENAME:ROBFullEvents") 1162292SN/A .desc("Number of times rename has blocked due to ROB full") 1171062SN/A .prereq(renameROBFullEvents); 1181062SN/A renameIQFullEvents 1192301SN/A .name(name() + ".RENAME:IQFullEvents") 1202292SN/A .desc("Number of times rename has blocked due to IQ full") 1211062SN/A .prereq(renameIQFullEvents); 1222292SN/A renameLSQFullEvents 1232301SN/A .name(name() + ".RENAME:LSQFullEvents") 1242292SN/A .desc("Number of times rename has blocked due to LSQ full") 1252292SN/A .prereq(renameLSQFullEvents); 1261062SN/A renameFullRegistersEvents 1272301SN/A .name(name() + ".RENAME:FullRegisterEvents") 1281062SN/A .desc("Number of times there has been no free registers") 1291062SN/A .prereq(renameFullRegistersEvents); 1301062SN/A renameRenamedOperands 1312301SN/A .name(name() + ".RENAME:RenamedOperands") 1321062SN/A .desc("Number of destination operands rename has renamed") 1331062SN/A .prereq(renameRenamedOperands); 1341062SN/A renameRenameLookups 1352301SN/A .name(name() + ".RENAME:RenameLookups") 1361062SN/A .desc("Number of register rename lookups that rename has made") 1371062SN/A .prereq(renameRenameLookups); 1381062SN/A renameCommittedMaps 1392301SN/A .name(name() + ".RENAME:CommittedMaps") 1401062SN/A .desc("Number of HB maps that are committed") 1411062SN/A .prereq(renameCommittedMaps); 1421062SN/A renameUndoneMaps 1432301SN/A .name(name() + ".RENAME:UndoneMaps") 1441062SN/A .desc("Number of HB maps that are undone due to squashing") 1451062SN/A .prereq(renameUndoneMaps); 1462301SN/A renamedSerializing 1472301SN/A .name(name() + ".RENAME:serializingInsts") 1482301SN/A .desc("count of serializing insts renamed") 1492301SN/A .flags(Stats::total) 1502301SN/A ; 1512301SN/A renamedTempSerializing 1522301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1532301SN/A .desc("count of temporary serializing insts renamed") 1542301SN/A .flags(Stats::total) 1552301SN/A ; 1562307SN/A renameSkidInsts 1572307SN/A .name(name() + ".RENAME:skidInsts") 1582307SN/A .desc("count of insts added to the skid buffer") 1592307SN/A .flags(Stats::total) 1602307SN/A ; 1611062SN/A} 1621062SN/A 1631062SN/Atemplate <class Impl> 1641062SN/Avoid 1652733Sktlim@umich.eduDefaultRename<Impl>::setCPU(O3CPU *cpu_ptr) 1661060SN/A{ 1672292SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1681060SN/A cpu = cpu_ptr; 1691060SN/A} 1701060SN/A 1711061SN/Atemplate <class Impl> 1721060SN/Avoid 1732292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1741060SN/A{ 1752292SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1761060SN/A timeBuffer = tb_ptr; 1771060SN/A 1781060SN/A // Setup wire to read information from time buffer, from IEW stage. 1791060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1821060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1831060SN/A 1841060SN/A // Setup wire to write information to previous stages. 1851060SN/A toDecode = timeBuffer->getWire(0); 1861060SN/A} 1871060SN/A 1881061SN/Atemplate <class Impl> 1891060SN/Avoid 1902292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1911060SN/A{ 1922292SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1931060SN/A renameQueue = rq_ptr; 1941060SN/A 1951060SN/A // Setup wire to write information to future stages. 1961060SN/A toIEW = renameQueue->getWire(0); 1971060SN/A} 1981060SN/A 1991061SN/Atemplate <class Impl> 2001060SN/Avoid 2012292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2021060SN/A{ 2032292SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2041060SN/A decodeQueue = dq_ptr; 2051060SN/A 2061060SN/A // Setup wire to get information from decode. 2071060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2081060SN/A} 2091060SN/A 2101061SN/Atemplate <class Impl> 2111060SN/Avoid 2122292SN/ADefaultRename<Impl>::initStage() 2131060SN/A{ 2142329SN/A // Grab the number of free entries directly from the stages. 2152292SN/A for (int tid=0; tid < numThreads; tid++) { 2162292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2172292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2182292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2192292SN/A emptyROB[tid] = true; 2202292SN/A } 2211060SN/A} 2221060SN/A 2232292SN/Atemplate<class Impl> 2242292SN/Avoid 2252292SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2262292SN/A{ 2272292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2282292SN/A activeThreads = at_ptr; 2292292SN/A} 2302292SN/A 2312292SN/A 2321061SN/Atemplate <class Impl> 2331060SN/Avoid 2342292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2351060SN/A{ 2362292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2371060SN/A 2382292SN/A for (int i=0; i<numThreads; i++) { 2392292SN/A renameMap[i] = &rm_ptr[i]; 2401060SN/A } 2411060SN/A} 2421060SN/A 2431061SN/Atemplate <class Impl> 2441060SN/Avoid 2452292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2461060SN/A{ 2472292SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2482292SN/A freeList = fl_ptr; 2492292SN/A} 2501060SN/A 2512292SN/Atemplate<class Impl> 2522292SN/Avoid 2532292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2542292SN/A{ 2552292SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2562292SN/A scoreboard = _scoreboard; 2571060SN/A} 2581060SN/A 2591061SN/Atemplate <class Impl> 2602863Sktlim@umich.edubool 2612843Sktlim@umich.eduDefaultRename<Impl>::drain() 2621060SN/A{ 2632348SN/A // Rename is ready to switch out at any time. 2642843Sktlim@umich.edu cpu->signalDrained(); 2652863Sktlim@umich.edu return true; 2662316SN/A} 2671060SN/A 2682316SN/Atemplate <class Impl> 2692316SN/Avoid 2702843Sktlim@umich.eduDefaultRename<Impl>::switchOut() 2712316SN/A{ 2722348SN/A // Clear any state, fix up the rename map. 2732307SN/A for (int i = 0; i < numThreads; i++) { 2742307SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 2752307SN/A 2762307SN/A while (!historyBuffer[i].empty()) { 2772307SN/A assert(hb_it != historyBuffer[i].end()); 2782307SN/A 2792307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2802307SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2812307SN/A 2822307SN/A // Tell the rename map to set the architected register to the 2832307SN/A // previous physical register that it was renamed to. 2842307SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2852307SN/A 2862307SN/A // Put the renamed physical register back on the free list. 2872307SN/A freeList->addReg(hb_it->newPhysReg); 2882307SN/A 2892307SN/A historyBuffer[i].erase(hb_it++); 2902307SN/A } 2912307SN/A insts[i].clear(); 2922307SN/A skidBuffer[i].clear(); 2931060SN/A } 2941060SN/A} 2951060SN/A 2961061SN/Atemplate <class Impl> 2971060SN/Avoid 2982307SN/ADefaultRename<Impl>::takeOverFrom() 2991060SN/A{ 3002307SN/A _status = Inactive; 3012307SN/A initStage(); 3021060SN/A 3032329SN/A // Reset all state prior to taking over from the other CPU. 3042307SN/A for (int i=0; i< numThreads; i++) { 3052307SN/A renameStatus[i] = Idle; 3061060SN/A 3072307SN/A stalls[i].iew = false; 3082307SN/A stalls[i].commit = false; 3092307SN/A serializeInst[i] = NULL; 3102307SN/A 3112307SN/A instsInProgress[i] = 0; 3122307SN/A 3132307SN/A emptyROB[i] = true; 3142307SN/A 3152307SN/A serializeOnNextInst[i] = false; 3162307SN/A } 3172307SN/A} 3182307SN/A 3192307SN/Atemplate <class Impl> 3202307SN/Avoid 3212292SN/ADefaultRename<Impl>::squash(unsigned tid) 3221858SN/A{ 3232292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3241858SN/A 3252292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3262292SN/A // If it still needs to block, the blocking should happen the next 3272292SN/A // cycle and there should be space to hold everything due to the squash. 3282292SN/A if (renameStatus[tid] == Blocked || 3292292SN/A renameStatus[tid] == Unblocking || 3302301SN/A renameStatus[tid] == SerializeStall) { 3312698Sktlim@umich.edu 3322292SN/A toDecode->renameUnblock[tid] = 1; 3332698Sktlim@umich.edu 3342301SN/A serializeInst[tid] = NULL; 3352292SN/A } 3362292SN/A 3372292SN/A // Set the status to Squashing. 3382292SN/A renameStatus[tid] = Squashing; 3392292SN/A 3402329SN/A // Squash any instructions from decode. 3412292SN/A unsigned squashCount = 0; 3422292SN/A 3432292SN/A for (int i=0; i<fromDecode->size; i++) { 3442292SN/A if (fromDecode->insts[i]->threadNumber == tid) { 3452731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3462292SN/A wroteToTimeBuffer = true; 3472292SN/A squashCount++; 3482292SN/A } 3492292SN/A } 3502292SN/A 3512292SN/A insts[tid].clear(); 3522292SN/A 3532292SN/A // Clear the skid buffer in case it has any data in it. 3542292SN/A skidBuffer[tid].clear(); 3552292SN/A 3562292SN/A doSquash(tid); 3572292SN/A} 3582292SN/A 3592292SN/Atemplate <class Impl> 3602292SN/Avoid 3612292SN/ADefaultRename<Impl>::tick() 3622292SN/A{ 3632292SN/A wroteToTimeBuffer = false; 3642292SN/A 3652292SN/A blockThisCycle = false; 3662292SN/A 3672292SN/A bool status_change = false; 3682292SN/A 3692292SN/A toIEWIndex = 0; 3702292SN/A 3712292SN/A sortInsts(); 3722292SN/A 3732292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 3742292SN/A 3752292SN/A // Check stall and squash signals. 3762292SN/A while (threads != (*activeThreads).end()) { 3772292SN/A unsigned tid = *threads++; 3782292SN/A 3792292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3802292SN/A 3812292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3822292SN/A 3832292SN/A rename(status_change, tid); 3842292SN/A } 3852292SN/A 3862292SN/A if (status_change) { 3872292SN/A updateStatus(); 3882292SN/A } 3892292SN/A 3902292SN/A if (wroteToTimeBuffer) { 3912292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 3922292SN/A cpu->activityThisCycle(); 3932292SN/A } 3942292SN/A 3952292SN/A threads = (*activeThreads).begin(); 3962292SN/A 3972292SN/A while (threads != (*activeThreads).end()) { 3982292SN/A unsigned tid = *threads++; 3992292SN/A 4002292SN/A // If we committed this cycle then doneSeqNum will be > 0 4012292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4022292SN/A !fromCommit->commitInfo[tid].squash && 4032292SN/A renameStatus[tid] != Squashing) { 4042292SN/A 4052292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4062292SN/A tid); 4072292SN/A } 4082292SN/A } 4092292SN/A 4102292SN/A // @todo: make into updateProgress function 4112292SN/A for (int tid=0; tid < numThreads; tid++) { 4122292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4132292SN/A 4142292SN/A assert(instsInProgress[tid] >=0); 4152292SN/A } 4162292SN/A 4172292SN/A} 4182292SN/A 4192292SN/Atemplate<class Impl> 4202292SN/Avoid 4212292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4222292SN/A{ 4232292SN/A // If status is Running or idle, 4242292SN/A // call renameInsts() 4252292SN/A // If status is Unblocking, 4262292SN/A // buffer any instructions coming from decode 4272292SN/A // continue trying to empty skid buffer 4282292SN/A // check if stall conditions have passed 4292292SN/A 4302292SN/A if (renameStatus[tid] == Blocked) { 4312292SN/A ++renameBlockCycles; 4322292SN/A } else if (renameStatus[tid] == Squashing) { 4332292SN/A ++renameSquashCycles; 4342301SN/A } else if (renameStatus[tid] == SerializeStall) { 4352301SN/A ++renameSerializeStallCycles; 4362292SN/A } 4372292SN/A 4382292SN/A if (renameStatus[tid] == Running || 4392292SN/A renameStatus[tid] == Idle) { 4402292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4412292SN/A "stage.\n", tid); 4422292SN/A 4432292SN/A renameInsts(tid); 4442292SN/A } else if (renameStatus[tid] == Unblocking) { 4452292SN/A renameInsts(tid); 4462292SN/A 4472292SN/A if (validInsts()) { 4482292SN/A // Add the current inputs to the skid buffer so they can be 4492292SN/A // reprocessed when this stage unblocks. 4502292SN/A skidInsert(tid); 4512292SN/A } 4522292SN/A 4532292SN/A // If we switched over to blocking, then there's a potential for 4542292SN/A // an overall status change. 4552292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4561858SN/A } 4571858SN/A} 4581858SN/A 4591858SN/Atemplate <class Impl> 4601858SN/Avoid 4612292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4621858SN/A{ 4632292SN/A // Instructions can be either in the skid buffer or the queue of 4642292SN/A // instructions coming from decode, depending on the status. 4652292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4662292SN/A skidBuffer[tid].size() : insts[tid].size(); 4671858SN/A 4682292SN/A // Check the decode queue to see if instructions are available. 4692292SN/A // If there are no available instructions to rename, then do nothing. 4702292SN/A if (insts_available == 0) { 4712292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4722292SN/A tid); 4732292SN/A // Should I change status to idle? 4742292SN/A ++renameIdleCycles; 4752292SN/A return; 4762292SN/A } else if (renameStatus[tid] == Unblocking) { 4772292SN/A ++renameUnblockCycles; 4782292SN/A } else if (renameStatus[tid] == Running) { 4792292SN/A ++renameRunCycles; 4802292SN/A } 4811858SN/A 4822292SN/A DynInstPtr inst; 4832292SN/A 4842292SN/A // Will have to do a different calculation for the number of free 4852292SN/A // entries. 4862292SN/A int free_rob_entries = calcFreeROBEntries(tid); 4872292SN/A int free_iq_entries = calcFreeIQEntries(tid); 4882292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 4892292SN/A int min_free_entries = free_rob_entries; 4902292SN/A 4912292SN/A FullSource source = ROB; 4922292SN/A 4932292SN/A if (free_iq_entries < min_free_entries) { 4942292SN/A min_free_entries = free_iq_entries; 4952292SN/A source = IQ; 4962292SN/A } 4972292SN/A 4982292SN/A if (free_lsq_entries < min_free_entries) { 4992292SN/A min_free_entries = free_lsq_entries; 5002292SN/A source = LSQ; 5012292SN/A } 5022292SN/A 5032292SN/A // Check if there's any space left. 5042292SN/A if (min_free_entries <= 0) { 5052292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5062292SN/A "entries.\n" 5072292SN/A "ROB has %i free entries.\n" 5082292SN/A "IQ has %i free entries.\n" 5092292SN/A "LSQ has %i free entries.\n", 5102292SN/A tid, 5112292SN/A free_rob_entries, 5122292SN/A free_iq_entries, 5132292SN/A free_lsq_entries); 5142292SN/A 5152292SN/A blockThisCycle = true; 5162292SN/A 5172292SN/A block(tid); 5182292SN/A 5192292SN/A incrFullStat(source); 5202292SN/A 5212292SN/A return; 5222292SN/A } else if (min_free_entries < insts_available) { 5232292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5242292SN/A "%i insts available, but only %i insts can be " 5252292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5262292SN/A tid, insts_available, min_free_entries); 5272292SN/A 5282292SN/A insts_available = min_free_entries; 5292292SN/A 5302292SN/A blockThisCycle = true; 5312292SN/A 5322292SN/A incrFullStat(source); 5332292SN/A } 5342292SN/A 5352292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5362292SN/A skidBuffer[tid] : insts[tid]; 5372292SN/A 5382292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5392292SN/A "send iew.\n", tid, insts_available); 5402292SN/A 5412292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5422292SN/A "dispatched to IQ last cycle.\n", 5432292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5442292SN/A 5452292SN/A // Handle serializing the next instruction if necessary. 5462292SN/A if (serializeOnNextInst[tid]) { 5472292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5482292SN/A // ROB already empty; no need to serialize. 5492292SN/A serializeOnNextInst[tid] = false; 5502292SN/A } else if (!insts_to_rename.empty()) { 5512292SN/A insts_to_rename.front()->setSerializeBefore(); 5522292SN/A } 5532292SN/A } 5542292SN/A 5552292SN/A int renamed_insts = 0; 5562292SN/A 5572292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5582292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5592292SN/A 5602292SN/A assert(!insts_to_rename.empty()); 5612292SN/A 5622292SN/A inst = insts_to_rename.front(); 5632292SN/A 5642292SN/A insts_to_rename.pop_front(); 5652292SN/A 5662292SN/A if (renameStatus[tid] == Unblocking) { 5672292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5682292SN/A "skidBuffer\n", 5692292SN/A tid, inst->seqNum, inst->readPC()); 5702292SN/A } 5712292SN/A 5722292SN/A if (inst->isSquashed()) { 5732292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 5742292SN/A "squashed, skipping.\n", 5752292SN/A tid, inst->seqNum, inst->threadNumber,inst->readPC()); 5762292SN/A 5772292SN/A ++renameSquashedInsts; 5782292SN/A 5792292SN/A // Decrement how many instructions are available. 5802292SN/A --insts_available; 5812292SN/A 5822292SN/A continue; 5832292SN/A } 5842292SN/A 5852292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 5862292SN/A "PC %#x.\n", 5872292SN/A tid, inst->seqNum, inst->readPC()); 5882292SN/A 5892292SN/A // Handle serializeAfter/serializeBefore instructions. 5902292SN/A // serializeAfter marks the next instruction as serializeBefore. 5912292SN/A // serializeBefore makes the instruction wait in rename until the ROB 5922292SN/A // is empty. 5932336SN/A 5942336SN/A // In this model, IPR accesses are serialize before 5952336SN/A // instructions, and store conditionals are serialize after 5962336SN/A // instructions. This is mainly due to lack of support for 5972336SN/A // out-of-order operations of either of those classes of 5982336SN/A // instructions. 5992336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6002336SN/A !inst->isSerializeHandled()) { 6012292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6022292SN/A 6032301SN/A if (!inst->isTempSerializeBefore()) { 6042301SN/A renamedSerializing++; 6052292SN/A inst->setSerializeHandled(); 6062301SN/A } else { 6072301SN/A renamedTempSerializing++; 6082301SN/A } 6092292SN/A 6102301SN/A // Change status over to SerializeStall so that other stages know 6112292SN/A // what this is blocked on. 6122301SN/A renameStatus[tid] = SerializeStall; 6132292SN/A 6142301SN/A serializeInst[tid] = inst; 6152292SN/A 6162292SN/A blockThisCycle = true; 6172292SN/A 6182292SN/A break; 6192336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6202336SN/A !inst->isSerializeHandled()) { 6212292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6222292SN/A 6232307SN/A renamedSerializing++; 6242307SN/A 6252292SN/A inst->setSerializeHandled(); 6262292SN/A 6272292SN/A serializeAfter(insts_to_rename, tid); 6282292SN/A } 6292292SN/A 6302292SN/A // Check here to make sure there are enough destination registers 6312292SN/A // to rename to. Otherwise block. 6322292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6332292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6342292SN/A "physical registers to rename to.\n"); 6352292SN/A blockThisCycle = true; 6362292SN/A 6372292SN/A ++renameFullRegistersEvents; 6382292SN/A 6392292SN/A break; 6402292SN/A } 6412292SN/A 6422292SN/A renameSrcRegs(inst, inst->threadNumber); 6432292SN/A 6442292SN/A renameDestRegs(inst, inst->threadNumber); 6452292SN/A 6462292SN/A ++renamed_insts; 6472292SN/A 6482292SN/A // Put instruction in rename queue. 6492292SN/A toIEW->insts[toIEWIndex] = inst; 6502292SN/A ++(toIEW->size); 6512292SN/A 6522292SN/A // Increment which instruction we're on. 6532292SN/A ++toIEWIndex; 6542292SN/A 6552292SN/A // Decrement how many instructions are available. 6562292SN/A --insts_available; 6572292SN/A } 6582292SN/A 6592292SN/A instsInProgress[tid] += renamed_insts; 6602307SN/A renameRenamedInsts += renamed_insts; 6612292SN/A 6622292SN/A // If we wrote to the time buffer, record this. 6632292SN/A if (toIEWIndex) { 6642292SN/A wroteToTimeBuffer = true; 6652292SN/A } 6662292SN/A 6672292SN/A // Check if there's any instructions left that haven't yet been renamed. 6682292SN/A // If so then block. 6692292SN/A if (insts_available) { 6702292SN/A blockThisCycle = true; 6712292SN/A } 6722292SN/A 6732292SN/A if (blockThisCycle) { 6742292SN/A block(tid); 6752292SN/A toDecode->renameUnblock[tid] = false; 6762292SN/A } 6772292SN/A} 6782292SN/A 6792292SN/Atemplate<class Impl> 6802292SN/Avoid 6812292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 6822292SN/A{ 6832292SN/A DynInstPtr inst = NULL; 6842292SN/A 6852292SN/A while (!insts[tid].empty()) { 6862292SN/A inst = insts[tid].front(); 6872292SN/A 6882292SN/A insts[tid].pop_front(); 6892292SN/A 6902292SN/A assert(tid == inst->threadNumber); 6912292SN/A 6922292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 6932292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 6942292SN/A 6952307SN/A ++renameSkidInsts; 6962307SN/A 6972292SN/A skidBuffer[tid].push_back(inst); 6982292SN/A } 6992292SN/A 7002292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7012292SN/A panic("Skidbuffer Exceeded Max Size"); 7022292SN/A} 7032292SN/A 7042292SN/Atemplate <class Impl> 7052292SN/Avoid 7062292SN/ADefaultRename<Impl>::sortInsts() 7072292SN/A{ 7082292SN/A int insts_from_decode = fromDecode->size; 7092329SN/A#ifdef DEBUG 7102292SN/A for (int i=0; i < numThreads; i++) 7112292SN/A assert(insts[i].empty()); 7122329SN/A#endif 7132292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7142292SN/A DynInstPtr inst = fromDecode->insts[i]; 7152292SN/A insts[inst->threadNumber].push_back(inst); 7162292SN/A } 7172292SN/A} 7182292SN/A 7192292SN/Atemplate<class Impl> 7202292SN/Abool 7212292SN/ADefaultRename<Impl>::skidsEmpty() 7222292SN/A{ 7232292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7242292SN/A 7252292SN/A while (threads != (*activeThreads).end()) { 7262292SN/A if (!skidBuffer[*threads++].empty()) 7272292SN/A return false; 7282292SN/A } 7292292SN/A 7302292SN/A return true; 7312292SN/A} 7322292SN/A 7332292SN/Atemplate<class Impl> 7342292SN/Avoid 7352292SN/ADefaultRename<Impl>::updateStatus() 7362292SN/A{ 7372292SN/A bool any_unblocking = false; 7382292SN/A 7392292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7402292SN/A 7412292SN/A threads = (*activeThreads).begin(); 7422292SN/A 7432292SN/A while (threads != (*activeThreads).end()) { 7442292SN/A unsigned tid = *threads++; 7452292SN/A 7462292SN/A if (renameStatus[tid] == Unblocking) { 7472292SN/A any_unblocking = true; 7482292SN/A break; 7492292SN/A } 7502292SN/A } 7512292SN/A 7522292SN/A // Rename will have activity if it's unblocking. 7532292SN/A if (any_unblocking) { 7542292SN/A if (_status == Inactive) { 7552292SN/A _status = Active; 7562292SN/A 7572292SN/A DPRINTF(Activity, "Activating stage.\n"); 7582292SN/A 7592733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7602292SN/A } 7612292SN/A } else { 7622292SN/A // If it's not unblocking, then rename will not have any internal 7632292SN/A // activity. Switch it to inactive. 7642292SN/A if (_status == Active) { 7652292SN/A _status = Inactive; 7662292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 7672292SN/A 7682733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 7692292SN/A } 7702292SN/A } 7712292SN/A} 7722292SN/A 7732292SN/Atemplate <class Impl> 7742292SN/Abool 7752292SN/ADefaultRename<Impl>::block(unsigned tid) 7762292SN/A{ 7772292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 7782292SN/A 7792292SN/A // Add the current inputs onto the skid buffer, so they can be 7802292SN/A // reprocessed when this stage unblocks. 7812292SN/A skidInsert(tid); 7822292SN/A 7832292SN/A // Only signal backwards to block if the previous stages do not think 7842292SN/A // rename is already blocked. 7852292SN/A if (renameStatus[tid] != Blocked) { 7862292SN/A if (renameStatus[tid] != Unblocking) { 7872292SN/A toDecode->renameBlock[tid] = true; 7882292SN/A toDecode->renameUnblock[tid] = false; 7892292SN/A wroteToTimeBuffer = true; 7902292SN/A } 7912292SN/A 7922329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 7932329SN/A // it would not know to complete the serialize stall. 7942301SN/A if (renameStatus[tid] != SerializeStall) { 7952292SN/A // Set status to Blocked. 7962292SN/A renameStatus[tid] = Blocked; 7972292SN/A return true; 7982292SN/A } 7992292SN/A } 8002292SN/A 8012292SN/A return false; 8022292SN/A} 8032292SN/A 8042292SN/Atemplate <class Impl> 8052292SN/Abool 8062292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8072292SN/A{ 8082292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8092292SN/A 8102292SN/A // Rename is done unblocking if the skid buffer is empty. 8112301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8122292SN/A 8132292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8142292SN/A 8152292SN/A toDecode->renameUnblock[tid] = true; 8162292SN/A wroteToTimeBuffer = true; 8172292SN/A 8182292SN/A renameStatus[tid] = Running; 8192292SN/A return true; 8202292SN/A } 8212292SN/A 8222292SN/A return false; 8232292SN/A} 8242292SN/A 8252292SN/Atemplate <class Impl> 8262292SN/Avoid 8272292SN/ADefaultRename<Impl>::doSquash(unsigned tid) 8282292SN/A{ 8292292SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 8302292SN/A 8312292SN/A InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 8322292SN/A 8331060SN/A // After a syscall squashes everything, the history buffer may be empty 8341060SN/A // but the ROB may still be squashing instructions. 8352292SN/A if (historyBuffer[tid].empty()) { 8361060SN/A return; 8371060SN/A } 8381060SN/A 8391060SN/A // Go through the most recent instructions, undoing the mappings 8401060SN/A // they did and freeing up the registers. 8412292SN/A while (!historyBuffer[tid].empty() && 8422292SN/A (*hb_it).instSeqNum > squashed_seq_num) { 8432292SN/A assert(hb_it != historyBuffer[tid].end()); 8441062SN/A 8452292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8462292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8471060SN/A 8482292SN/A // Tell the rename map to set the architected register to the 8492292SN/A // previous physical register that it was renamed to. 8502292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8511060SN/A 8522292SN/A // Put the renamed physical register back on the free list. 8532292SN/A freeList->addReg(hb_it->newPhysReg); 8541062SN/A 8552292SN/A historyBuffer[tid].erase(hb_it++); 8561061SN/A 8571062SN/A ++renameUndoneMaps; 8581060SN/A } 8591060SN/A} 8601060SN/A 8611060SN/Atemplate<class Impl> 8621060SN/Avoid 8632292SN/ADefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 8641060SN/A{ 8652292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 8662292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 8672292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 8682292SN/A 8692292SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 8701060SN/A 8711061SN/A --hb_it; 8721060SN/A 8732292SN/A if (historyBuffer[tid].empty()) { 8742292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 8752292SN/A return; 8762292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 8772292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 8782292SN/A "that a syscall happened recently.\n", tid); 8791060SN/A return; 8801060SN/A } 8811060SN/A 8822292SN/A // Commit all the renames up until (and including) the committed sequence 8832292SN/A // number. Some or even all of the committed instructions may not have 8842292SN/A // rename histories if they did not have destination registers that were 8852292SN/A // renamed. 8862292SN/A while (!historyBuffer[tid].empty() && 8872292SN/A hb_it != historyBuffer[tid].end() && 8882292SN/A (*hb_it).instSeqNum <= inst_seq_num) { 8891060SN/A 8902329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 8912329SN/A "[sn:%lli].\n", 8922292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 8931061SN/A 8942292SN/A freeList->addReg((*hb_it).prevPhysReg); 8952292SN/A ++renameCommittedMaps; 8961061SN/A 8972292SN/A historyBuffer[tid].erase(hb_it--); 8981060SN/A } 8991060SN/A} 9001060SN/A 9011061SN/Atemplate <class Impl> 9021061SN/Ainline void 9032292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9041061SN/A{ 9052292SN/A assert(renameMap[tid] != 0); 9062292SN/A 9071061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9081061SN/A 9091061SN/A // Get the architectual register numbers from the source and 9101061SN/A // destination operands, and redirect them to the right register. 9111061SN/A // Will need to mark dependencies though. 9122292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9131061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9141061SN/A 9151061SN/A // Look up the source registers to get the phys. register they've 9161061SN/A // been renamed to, and set the sources to those registers. 9172292SN/A PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 9181061SN/A 9192292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9202292SN/A "physical reg %i.\n", tid, (int)src_reg, 9212292SN/A (int)renamed_reg); 9221061SN/A 9231061SN/A inst->renameSrcReg(src_idx, renamed_reg); 9241061SN/A 9252292SN/A // See if the register is ready or not. 9262292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9272292SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 9281061SN/A 9291061SN/A inst->markSrcRegReady(src_idx); 9301061SN/A } 9311062SN/A 9321062SN/A ++renameRenameLookups; 9331061SN/A } 9341061SN/A} 9351061SN/A 9361061SN/Atemplate <class Impl> 9371061SN/Ainline void 9382292SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 9391061SN/A{ 9402292SN/A typename RenameMap::RenameInfo rename_result; 9411061SN/A 9421061SN/A unsigned num_dest_regs = inst->numDestRegs(); 9431061SN/A 9442292SN/A // Rename the destination registers. 9452292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 9462292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 9471061SN/A 9482292SN/A // Get the physical register that the destination will be 9492292SN/A // renamed to. 9502292SN/A rename_result = renameMap[tid]->rename(dest_reg); 9511061SN/A 9522292SN/A //Mark Scoreboard entry as not ready 9532292SN/A scoreboard->unsetReg(rename_result.first); 9541062SN/A 9552292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 9562292SN/A "reg %i.\n", tid, (int)dest_reg, 9572292SN/A (int)rename_result.first); 9581062SN/A 9592292SN/A // Record the rename information so that a history can be kept. 9602292SN/A RenameHistory hb_entry(inst->seqNum, dest_reg, 9612292SN/A rename_result.first, 9622292SN/A rename_result.second); 9631062SN/A 9642292SN/A historyBuffer[tid].push_front(hb_entry); 9651062SN/A 9662292SN/A DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 9672292SN/A "[sn:%lli].\n",tid, 9682292SN/A (*historyBuffer[tid].begin()).instSeqNum); 9691062SN/A 9702292SN/A // Tell the instruction to rename the appropriate destination 9712292SN/A // register (dest_idx) to the new physical register 9722292SN/A // (rename_result.first), and record the previous physical 9732292SN/A // register that the same logical register was renamed to 9742292SN/A // (rename_result.second). 9752292SN/A inst->renameDestReg(dest_idx, 9762292SN/A rename_result.first, 9772292SN/A rename_result.second); 9781062SN/A 9792292SN/A ++renameRenamedOperands; 9801061SN/A } 9811061SN/A} 9821061SN/A 9831061SN/Atemplate <class Impl> 9841061SN/Ainline int 9852292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 9861061SN/A{ 9872292SN/A int num_free = freeEntries[tid].robEntries - 9882292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 9892292SN/A 9902292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 9912292SN/A 9922292SN/A return num_free; 9931061SN/A} 9941061SN/A 9951061SN/Atemplate <class Impl> 9961061SN/Ainline int 9972292SN/ADefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 9981061SN/A{ 9992292SN/A int num_free = freeEntries[tid].iqEntries - 10002292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10012292SN/A 10022292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10032292SN/A 10042292SN/A return num_free; 10052292SN/A} 10062292SN/A 10072292SN/Atemplate <class Impl> 10082292SN/Ainline int 10092292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10102292SN/A{ 10112292SN/A int num_free = freeEntries[tid].lsqEntries - 10122292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10132292SN/A 10142292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10152292SN/A 10162292SN/A return num_free; 10172292SN/A} 10182292SN/A 10192292SN/Atemplate <class Impl> 10202292SN/Aunsigned 10212292SN/ADefaultRename<Impl>::validInsts() 10222292SN/A{ 10232292SN/A unsigned inst_count = 0; 10242292SN/A 10252292SN/A for (int i=0; i<fromDecode->size; i++) { 10262731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 10272292SN/A inst_count++; 10282292SN/A } 10292292SN/A 10302292SN/A return inst_count; 10312292SN/A} 10322292SN/A 10332292SN/Atemplate <class Impl> 10342292SN/Avoid 10352292SN/ADefaultRename<Impl>::readStallSignals(unsigned tid) 10362292SN/A{ 10372292SN/A if (fromIEW->iewBlock[tid]) { 10382292SN/A stalls[tid].iew = true; 10392292SN/A } 10402292SN/A 10412292SN/A if (fromIEW->iewUnblock[tid]) { 10422292SN/A assert(stalls[tid].iew); 10432292SN/A stalls[tid].iew = false; 10442292SN/A } 10452292SN/A 10462292SN/A if (fromCommit->commitBlock[tid]) { 10472292SN/A stalls[tid].commit = true; 10482292SN/A } 10492292SN/A 10502292SN/A if (fromCommit->commitUnblock[tid]) { 10512292SN/A assert(stalls[tid].commit); 10522292SN/A stalls[tid].commit = false; 10532292SN/A } 10542292SN/A} 10552292SN/A 10562292SN/Atemplate <class Impl> 10572292SN/Abool 10582292SN/ADefaultRename<Impl>::checkStall(unsigned tid) 10592292SN/A{ 10602292SN/A bool ret_val = false; 10612292SN/A 10622292SN/A if (stalls[tid].iew) { 10632292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 10642292SN/A ret_val = true; 10652292SN/A } else if (stalls[tid].commit) { 10662292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 10672292SN/A ret_val = true; 10682292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 10692292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 10702292SN/A ret_val = true; 10712292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 10722292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 10732292SN/A ret_val = true; 10742292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 10752292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 10762292SN/A ret_val = true; 10772292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 10782292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 10792292SN/A ret_val = true; 10802301SN/A } else if (renameStatus[tid] == SerializeStall && 10812292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 10822301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 10832292SN/A "empty.\n", 10842292SN/A tid); 10852292SN/A ret_val = true; 10862292SN/A } 10872292SN/A 10882292SN/A return ret_val; 10892292SN/A} 10902292SN/A 10912292SN/Atemplate <class Impl> 10922292SN/Avoid 10932292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 10942292SN/A{ 10952292SN/A bool updated = false; 10962292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 10972292SN/A freeEntries[tid].iqEntries = 10982292SN/A fromIEW->iewInfo[tid].freeIQEntries; 10992292SN/A updated = true; 11002292SN/A } 11012292SN/A 11022292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11032292SN/A freeEntries[tid].lsqEntries = 11042292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11052292SN/A updated = true; 11062292SN/A } 11072292SN/A 11082292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11092292SN/A freeEntries[tid].robEntries = 11102292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11112292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11122292SN/A updated = true; 11132292SN/A } 11142292SN/A 11152292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11162292SN/A tid, 11172292SN/A freeEntries[tid].iqEntries, 11182292SN/A freeEntries[tid].robEntries, 11192292SN/A freeEntries[tid].lsqEntries); 11202292SN/A 11212292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11222292SN/A tid, instsInProgress[tid]); 11232292SN/A} 11242292SN/A 11252292SN/Atemplate <class Impl> 11262292SN/Abool 11272292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 11282292SN/A{ 11292292SN/A // Check if there's a squash signal, squash if there is 11302292SN/A // Check stall signals, block if necessary. 11312292SN/A // If status was blocked 11322292SN/A // check if stall conditions have passed 11332292SN/A // if so then go to unblocking 11342292SN/A // If status was Squashing 11352292SN/A // check if squashing is not high. Switch to running this cycle. 11362301SN/A // If status was serialize stall 11372292SN/A // check if ROB is empty and no insts are in flight to the ROB 11382292SN/A 11392292SN/A readFreeEntries(tid); 11402292SN/A readStallSignals(tid); 11412292SN/A 11422292SN/A if (fromCommit->commitInfo[tid].squash) { 11432292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 11442292SN/A "commit.\n", tid); 11452292SN/A 11462292SN/A squash(tid); 11472292SN/A 11482292SN/A return true; 11492292SN/A } 11502292SN/A 11512292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 11522292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 11532292SN/A 11542292SN/A renameStatus[tid] = Squashing; 11552292SN/A 11562292SN/A return true; 11572292SN/A } 11582292SN/A 11592292SN/A if (checkStall(tid)) { 11602292SN/A return block(tid); 11612292SN/A } 11622292SN/A 11632292SN/A if (renameStatus[tid] == Blocked) { 11642292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 11652292SN/A tid); 11662292SN/A 11672292SN/A renameStatus[tid] = Unblocking; 11682292SN/A 11692292SN/A unblock(tid); 11702292SN/A 11712292SN/A return true; 11722292SN/A } 11732292SN/A 11742292SN/A if (renameStatus[tid] == Squashing) { 11752292SN/A // Switch status to running if rename isn't being told to block or 11762292SN/A // squash this cycle. 11772292SN/A DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 11782292SN/A tid); 11792292SN/A 11802292SN/A renameStatus[tid] = Running; 11812292SN/A 11822292SN/A return false; 11832292SN/A } 11842292SN/A 11852301SN/A if (renameStatus[tid] == SerializeStall) { 11862292SN/A // Stall ends once the ROB is free. 11872301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 11882292SN/A "unblocking.\n", tid); 11892292SN/A 11902301SN/A DynInstPtr serial_inst = serializeInst[tid]; 11912292SN/A 11922292SN/A renameStatus[tid] = Unblocking; 11932292SN/A 11942292SN/A unblock(tid); 11952292SN/A 11962292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 11972292SN/A "PC %#x.\n", 11982301SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 11992292SN/A 12002292SN/A // Put instruction into queue here. 12012301SN/A serial_inst->clearSerializeBefore(); 12022292SN/A 12032292SN/A if (!skidBuffer[tid].empty()) { 12042301SN/A skidBuffer[tid].push_front(serial_inst); 12052292SN/A } else { 12062301SN/A insts[tid].push_front(serial_inst); 12072292SN/A } 12082292SN/A 12092292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12102703Sktlim@umich.edu " Adding to front of list.\n", tid); 12112292SN/A 12122301SN/A serializeInst[tid] = NULL; 12132292SN/A 12142292SN/A return true; 12152292SN/A } 12162292SN/A 12172292SN/A // If we've reached this point, we have not gotten any signals that 12182292SN/A // cause rename to change its status. Rename remains the same as before. 12192292SN/A return false; 12201061SN/A} 12211061SN/A 12221060SN/Atemplate<class Impl> 12231060SN/Avoid 12242292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 12252292SN/A unsigned tid) 12261060SN/A{ 12272292SN/A if (inst_list.empty()) { 12282292SN/A // Mark a bit to say that I must serialize on the next instruction. 12292292SN/A serializeOnNextInst[tid] = true; 12301060SN/A return; 12311060SN/A } 12321060SN/A 12332292SN/A // Set the next instruction as serializing. 12342292SN/A inst_list.front()->setSerializeBefore(); 12352292SN/A} 12362292SN/A 12372292SN/Atemplate <class Impl> 12382292SN/Ainline void 12392292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 12402292SN/A{ 12412292SN/A switch (source) { 12422292SN/A case ROB: 12432292SN/A ++renameROBFullEvents; 12442292SN/A break; 12452292SN/A case IQ: 12462292SN/A ++renameIQFullEvents; 12472292SN/A break; 12482292SN/A case LSQ: 12492292SN/A ++renameLSQFullEvents; 12502292SN/A break; 12512292SN/A default: 12522292SN/A panic("Rename full stall stat should be incremented for a reason!"); 12532292SN/A break; 12541060SN/A } 12552292SN/A} 12561060SN/A 12572292SN/Atemplate <class Impl> 12582292SN/Avoid 12592292SN/ADefaultRename<Impl>::dumpHistory() 12602292SN/A{ 12612292SN/A typename list<RenameHistory>::iterator buf_it; 12621060SN/A 12632292SN/A for (int i = 0; i < numThreads; i++) { 12641060SN/A 12652292SN/A buf_it = historyBuffer[i].begin(); 12661060SN/A 12672292SN/A while (buf_it != historyBuffer[i].end()) { 12682292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 12692292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 12702292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 12711060SN/A 12722292SN/A buf_it++; 12731062SN/A } 12741060SN/A } 12751060SN/A} 1276