rename_impl.hh revision 2703
11689SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292935Sksewell@umich.edu */ 301689SN/A 311689SN/A#include <list> 321060SN/A 331060SN/A#include "config/full_system.hh" 343773Sgblack@eecs.umich.edu#include "cpu/o3/rename.hh" 353773Sgblack@eecs.umich.edu 361858SN/Ausing namespace std; 371717SN/A 381060SN/Atemplate <class Impl> 391061SN/ADefaultRename<Impl>::DefaultRename(Params *params) 404329Sktlim@umich.edu : iewToRenameDelay(params->iewToRenameDelay), 414329Sktlim@umich.edu decodeToRenameDelay(params->decodeToRenameDelay), 424329Sktlim@umich.edu commitToRenameDelay(params->commitToRenameDelay), 432292SN/A renameWidth(params->renameWidth), 442292SN/A commitWidth(params->commitWidth), 452292SN/A numThreads(params->numberOfThreads) 462292SN/A{ 473788Sgblack@eecs.umich.edu _status = Inactive; 483798Sgblack@eecs.umich.edu 492361SN/A for (int i=0; i< numThreads; i++) { 502361SN/A renameStatus[i] = Idle; 511060SN/A 522292SN/A freeEntries[i].iqEntries = 0; 532292SN/A freeEntries[i].lsqEntries = 0; 542292SN/A freeEntries[i].robEntries = 0; 552292SN/A 562292SN/A stalls[i].iew = false; 572292SN/A stalls[i].commit = false; 582292SN/A serializeInst[i] = NULL; 592292SN/A 602292SN/A instsInProgress[i] = 0; 612292SN/A 622292SN/A emptyROB[i] = true; 632301SN/A 642292SN/A serializeOnNextInst[i] = false; 652292SN/A } 662292SN/A 672292SN/A // @todo: Make into a parameter. 682292SN/A skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Astd::string 732292SN/ADefaultRename<Impl>::name() const 742292SN/A{ 752292SN/A return cpu->name() + ".rename"; 762292SN/A} 772292SN/A 782292SN/Atemplate <class Impl> 792292SN/Avoid 802292SN/ADefaultRename<Impl>::regStats() 811060SN/A{ 821060SN/A renameSquashCycles 831061SN/A .name(name() + ".RENAME:SquashCycles") 841060SN/A .desc("Number of cycles rename is squashing") 852292SN/A .prereq(renameSquashCycles); 861062SN/A renameIdleCycles 871062SN/A .name(name() + ".RENAME:IdleCycles") 882301SN/A .desc("Number of cycles rename is idle") 891062SN/A .prereq(renameIdleCycles); 901062SN/A renameBlockCycles 911062SN/A .name(name() + ".RENAME:BlockCycles") 922301SN/A .desc("Number of cycles rename is blocking") 931062SN/A .prereq(renameBlockCycles); 941062SN/A renameSerializeStallCycles 951062SN/A .name(name() + ".RENAME:serializeStallCycles") 962301SN/A .desc("count of cycles rename stalled for serializing inst") 971062SN/A .flags(Stats::total); 981062SN/A renameRunCycles 992301SN/A .name(name() + ".RENAME:RunCycles") 1002301SN/A .desc("Number of cycles rename is running") 1012301SN/A .prereq(renameIdleCycles); 1022301SN/A renameUnblockCycles 1032292SN/A .name(name() + ".RENAME:UnblockCycles") 1042301SN/A .desc("Number of cycles rename is unblocking") 1052292SN/A .prereq(renameUnblockCycles); 1062292SN/A renameRenamedInsts 1071062SN/A .name(name() + ".RENAME:RenamedInsts") 1082301SN/A .desc("Number of instructions processed by rename") 1091062SN/A .prereq(renameRenamedInsts); 1101062SN/A renameSquashedInsts 1111062SN/A .name(name() + ".RENAME:SquashedInsts") 1122301SN/A .desc("Number of squashed instructions processed by rename") 1131062SN/A .prereq(renameSquashedInsts); 1141062SN/A renameROBFullEvents 1151062SN/A .name(name() + ".RENAME:ROBFullEvents") 1162301SN/A .desc("Number of times rename has blocked due to ROB full") 1171062SN/A .prereq(renameROBFullEvents); 1181062SN/A renameIQFullEvents 1191062SN/A .name(name() + ".RENAME:IQFullEvents") 1202301SN/A .desc("Number of times rename has blocked due to IQ full") 1212292SN/A .prereq(renameIQFullEvents); 1221062SN/A renameLSQFullEvents 1231062SN/A .name(name() + ".RENAME:LSQFullEvents") 1242301SN/A .desc("Number of times rename has blocked due to LSQ full") 1252292SN/A .prereq(renameLSQFullEvents); 1261062SN/A renameFullRegistersEvents 1272292SN/A .name(name() + ".RENAME:FullRegisterEvents") 1282301SN/A .desc("Number of times there has been no free registers") 1292292SN/A .prereq(renameFullRegistersEvents); 1302292SN/A renameRenamedOperands 1311062SN/A .name(name() + ".RENAME:RenamedOperands") 1322301SN/A .desc("Number of destination operands rename has renamed") 1331062SN/A .prereq(renameRenamedOperands); 1341062SN/A renameRenameLookups 1351062SN/A .name(name() + ".RENAME:RenameLookups") 1362301SN/A .desc("Number of register rename lookups that rename has made") 1371062SN/A .prereq(renameRenameLookups); 1381062SN/A renameCommittedMaps 1391062SN/A .name(name() + ".RENAME:CommittedMaps") 1402301SN/A .desc("Number of HB maps that are committed") 1411062SN/A .prereq(renameCommittedMaps); 1421062SN/A renameUndoneMaps 1431062SN/A .name(name() + ".RENAME:UndoneMaps") 1442301SN/A .desc("Number of HB maps that are undone due to squashing") 1451062SN/A .prereq(renameUndoneMaps); 1461062SN/A renamedSerializing 1471062SN/A .name(name() + ".RENAME:serializingInsts") 1482301SN/A .desc("count of serializing insts renamed") 1491062SN/A .flags(Stats::total) 1501062SN/A ; 1512301SN/A renamedTempSerializing 1522301SN/A .name(name() + ".RENAME:tempSerializingInsts") 1532301SN/A .desc("count of temporary serializing insts renamed") 1542301SN/A .flags(Stats::total) 1552301SN/A ; 1562301SN/A renameSkidInsts 1572301SN/A .name(name() + ".RENAME:skidInsts") 1582301SN/A .desc("count of insts added to the skid buffer") 1592301SN/A .flags(Stats::total) 1602301SN/A ; 1612307SN/A} 1622307SN/A 1632307SN/Atemplate <class Impl> 1642307SN/Avoid 1652307SN/ADefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1661062SN/A{ 1671062SN/A DPRINTF(Rename, "Setting CPU pointer.\n"); 1681062SN/A cpu = cpu_ptr; 1691062SN/A} 1702292SN/A 1711060SN/Atemplate <class Impl> 1721060SN/Avoid 1731060SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1741060SN/A{ 1751060SN/A DPRINTF(Rename, "Setting time buffer pointer.\n"); 1761060SN/A timeBuffer = tb_ptr; 1771060SN/A 1781060SN/A // Setup wire to read information from time buffer, from IEW stage. 1791060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1801060SN/A 1811060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1821060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1831060SN/A 1841061SN/A // Setup wire to write information to previous stages. 1851060SN/A toDecode = timeBuffer->getWire(0); 1862292SN/A} 1871060SN/A 1881060SN/Atemplate <class Impl> 1891060SN/Avoid 1901060SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1911060SN/A{ 1921060SN/A DPRINTF(Rename, "Setting rename queue pointer.\n"); 1931060SN/A renameQueue = rq_ptr; 1941061SN/A 1951060SN/A // Setup wire to write information to future stages. 1962292SN/A toIEW = renameQueue->getWire(0); 1971060SN/A} 1981060SN/A 1991060SN/Atemplate <class Impl> 2001060SN/Avoid 2011060SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2021060SN/A{ 2031060SN/A DPRINTF(Rename, "Setting decode queue pointer.\n"); 2041061SN/A decodeQueue = dq_ptr; 2051060SN/A 2062292SN/A // Setup wire to get information from decode. 2071060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2082329SN/A} 2092292SN/A 2102292SN/Atemplate <class Impl> 2112292SN/Avoid 2122292SN/ADefaultRename<Impl>::initStage() 2132292SN/A{ 2142292SN/A // Grab the number of free entries directly from the stages. 2151060SN/A for (int tid=0; tid < numThreads; tid++) { 2161060SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2172292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2182292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2192980Sgblack@eecs.umich.edu emptyROB[tid] = true; 2202292SN/A } 2212292SN/A} 2222292SN/A 2232292SN/Atemplate<class Impl> 2242292SN/Avoid 2251061SN/ADefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2261060SN/A{ 2272292SN/A DPRINTF(Rename, "Setting active threads list pointer.\n"); 2281060SN/A activeThreads = at_ptr; 2292292SN/A} 2302292SN/A 2311060SN/A 2321060SN/Atemplate <class Impl> 2331060SN/Avoid 2341061SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2351060SN/A{ 2362292SN/A DPRINTF(Rename, "Setting rename map pointers.\n"); 2371060SN/A 2382292SN/A for (int i=0; i<numThreads; i++) { 2392292SN/A renameMap[i] = &rm_ptr[i]; 2401060SN/A } 2412292SN/A} 2422292SN/A 2432292SN/Atemplate <class Impl> 2442292SN/Avoid 2452292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2461060SN/A{ 2471060SN/A DPRINTF(Rename, "Setting free list pointer.\n"); 2481061SN/A freeList = fl_ptr; 2492863Sktlim@umich.edu} 2502843Sktlim@umich.edu 2511060SN/Atemplate<class Impl> 2522348SN/Avoid 2532843Sktlim@umich.eduDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2542863Sktlim@umich.edu{ 2552316SN/A DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2561060SN/A scoreboard = _scoreboard; 2572316SN/A} 2582316SN/A 2592843Sktlim@umich.edutemplate <class Impl> 2602316SN/Avoid 2612348SN/ADefaultRename<Impl>::switchOut() 2622307SN/A{ 2632980Sgblack@eecs.umich.edu // Rename is ready to switch out at any time. 2642980Sgblack@eecs.umich.edu cpu->signalSwitched(); 2652307SN/A} 2662307SN/A 2672307SN/Atemplate <class Impl> 2682307SN/Avoid 2692307SN/ADefaultRename<Impl>::doSwitchOut() 2702307SN/A{ 2712307SN/A // Clear any state, fix up the rename map. 2722307SN/A for (int i = 0; i < numThreads; i++) { 2732307SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 2742307SN/A 2752307SN/A while (!historyBuffer[i].empty()) { 2762307SN/A assert(hb_it != historyBuffer[i].end()); 2772307SN/A 2782307SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 2792361SN/A "number %i.\n", i, (*hb_it).instSeqNum); 2802361SN/A 2812361SN/A // Tell the rename map to set the architected register to the 2822361SN/A // previous physical register that it was renamed to. 2832361SN/A renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 2842307SN/A 2852307SN/A // Put the renamed physical register back on the free list. 2862307SN/A freeList->addReg(hb_it->newPhysReg); 2872307SN/A 2881060SN/A historyBuffer[i].erase(hb_it++); 2891060SN/A } 2901060SN/A insts[i].clear(); 2911061SN/A skidBuffer[i].clear(); 2921060SN/A } 2932307SN/A} 2941060SN/A 2952307SN/Atemplate <class Impl> 2962307SN/Avoid 2971060SN/ADefaultRename<Impl>::takeOverFrom() 2982329SN/A{ 2992307SN/A _status = Inactive; 3002307SN/A initStage(); 3011060SN/A 3022307SN/A // Reset all state prior to taking over from the other CPU. 3032307SN/A for (int i=0; i< numThreads; i++) { 3042307SN/A renameStatus[i] = Idle; 3052307SN/A 3062307SN/A stalls[i].iew = false; 3072307SN/A stalls[i].commit = false; 3082307SN/A serializeInst[i] = NULL; 3092307SN/A 3102307SN/A instsInProgress[i] = 0; 3112307SN/A 3122307SN/A emptyROB[i] = true; 3132307SN/A 3142307SN/A serializeOnNextInst[i] = false; 3152307SN/A } 3162935Sksewell@umich.edu} 3171858SN/A 3182292SN/Atemplate <class Impl> 3191858SN/Avoid 3202292SN/ADefaultRename<Impl>::squash(unsigned tid) 3212292SN/A{ 3222292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3232292SN/A 3243788Sgblack@eecs.umich.edu // Clear the stall signal if rename was blocked or unblocking before. 3252292SN/A // If it still needs to block, the blocking should happen the next 3262698Sktlim@umich.edu // cycle and there should be space to hold everything due to the squash. 3273788Sgblack@eecs.umich.edu if (renameStatus[tid] == Blocked || 3282301SN/A renameStatus[tid] == Unblocking || 3293788Sgblack@eecs.umich.edu renameStatus[tid] == SerializeStall) { 3303788Sgblack@eecs.umich.edu 3313788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3323788Sgblack@eecs.umich.edu 3333788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3343788Sgblack@eecs.umich.edu } 3353788Sgblack@eecs.umich.edu 3363788Sgblack@eecs.umich.edu // Set the status to Squashing. 3373788Sgblack@eecs.umich.edu renameStatus[tid] = Squashing; 3383788Sgblack@eecs.umich.edu 3393788Sgblack@eecs.umich.edu // Squash any instructions from decode. 3402292SN/A unsigned squashCount = 0; 3412292SN/A 3422292SN/A for (int i=0; i<fromDecode->size; i++) { 3432292SN/A if (fromDecode->insts[i]->threadNumber == tid) { 3442292SN/A fromDecode->insts[i]->squashed = true; 3452329SN/A wroteToTimeBuffer = true; 3462292SN/A squashCount++; 3472292SN/A } 3482292SN/A } 3492935Sksewell@umich.edu 3502935Sksewell@umich.edu insts[tid].clear(); 3512731Sktlim@umich.edu 3522292SN/A // Clear the skid buffer in case it has any data in it. 3532292SN/A skidBuffer[tid].clear(); 3542292SN/A 3552935Sksewell@umich.edu doSquash(tid); 3562292SN/A} 3572292SN/A 3582935Sksewell@umich.edutemplate <class Impl> 3592935Sksewell@umich.eduvoid 3602935Sksewell@umich.eduDefaultRename<Impl>::tick() 3612935Sksewell@umich.edu{ 3622935Sksewell@umich.edu wroteToTimeBuffer = false; 3633093Sksewell@umich.edu 3642935Sksewell@umich.edu blockThisCycle = false; 3652935Sksewell@umich.edu 3662935Sksewell@umich.edu bool status_change = false; 3672935Sksewell@umich.edu 3682935Sksewell@umich.edu toIEWIndex = 0; 3692935Sksewell@umich.edu 3702935Sksewell@umich.edu sortInsts(); 3712935Sksewell@umich.edu 3722935Sksewell@umich.edu list<unsigned>::iterator threads = (*activeThreads).begin(); 3732935Sksewell@umich.edu 3742935Sksewell@umich.edu // Check stall and squash signals. 3753093Sksewell@umich.edu while (threads != (*activeThreads).end()) { 3763093Sksewell@umich.edu unsigned tid = *threads++; 3772935Sksewell@umich.edu 3782292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3792292SN/A 3802935Sksewell@umich.edu status_change = checkSignalsAndUpdate(tid) || status_change; 3812935Sksewell@umich.edu 3823093Sksewell@umich.edu rename(status_change, tid); 3832935Sksewell@umich.edu } 3842935Sksewell@umich.edu 3852935Sksewell@umich.edu if (status_change) { 3862935Sksewell@umich.edu updateStatus(); 3872935Sksewell@umich.edu } 3882935Sksewell@umich.edu 3892935Sksewell@umich.edu if (wroteToTimeBuffer) { 3902935Sksewell@umich.edu DPRINTF(Activity, "Activity this cycle.\n"); 3912935Sksewell@umich.edu cpu->activityThisCycle(); 3922935Sksewell@umich.edu } 3932935Sksewell@umich.edu 3943798Sgblack@eecs.umich.edu threads = (*activeThreads).begin(); 3953798Sgblack@eecs.umich.edu 3963798Sgblack@eecs.umich.edu while (threads != (*activeThreads).end()) { 3973093Sksewell@umich.edu unsigned tid = *threads++; 3983093Sksewell@umich.edu 3992935Sksewell@umich.edu // If we committed this cycle then doneSeqNum will be > 0 4002935Sksewell@umich.edu if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4012292SN/A !fromCommit->commitInfo[tid].squash && 4022292SN/A renameStatus[tid] != Squashing) { 4032292SN/A 4042292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4052292SN/A tid); 4062292SN/A } 4072292SN/A } 4082292SN/A 4092292SN/A // @todo: make into updateProgress function 4102292SN/A for (int tid=0; tid < numThreads; tid++) { 4112292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4122292SN/A 4132292SN/A assert(instsInProgress[tid] >=0); 4142292SN/A } 4152292SN/A 4162292SN/A} 4173867Sbinkertn@umich.edu 4183867Sbinkertn@umich.edutemplate<class Impl> 4192292SN/Avoid 4202292SN/ADefaultRename<Impl>::rename(bool &status_change, unsigned tid) 4213867Sbinkertn@umich.edu{ 4222292SN/A // If status is Running or idle, 4232292SN/A // call renameInsts() 4242292SN/A // If status is Unblocking, 4252292SN/A // buffer any instructions coming from decode 4262292SN/A // continue trying to empty skid buffer 4272292SN/A // check if stall conditions have passed 4282292SN/A 4292292SN/A if (renameStatus[tid] == Blocked) { 4302292SN/A ++renameBlockCycles; 4312292SN/A } else if (renameStatus[tid] == Squashing) { 4322292SN/A ++renameSquashCycles; 4332292SN/A } else if (renameStatus[tid] == SerializeStall) { 4342292SN/A ++renameSerializeStallCycles; 4352292SN/A } 4362292SN/A 4372292SN/A if (renameStatus[tid] == Running || 4382292SN/A renameStatus[tid] == Idle) { 4392292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4403867Sbinkertn@umich.edu "stage.\n", tid); 4412292SN/A 4423867Sbinkertn@umich.edu renameInsts(tid); 4432292SN/A } else if (renameStatus[tid] == Unblocking) { 4442292SN/A renameInsts(tid); 4452292SN/A 4462292SN/A if (validInsts()) { 4472292SN/A // Add the current inputs to the skid buffer so they can be 4482292SN/A // reprocessed when this stage unblocks. 4492292SN/A skidInsert(tid); 4502292SN/A } 4512292SN/A 4522292SN/A // If we switched over to blocking, then there's a potential for 4532292SN/A // an overall status change. 4542292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4552292SN/A } 4562292SN/A} 4572292SN/A 4582292SN/Atemplate <class Impl> 4592292SN/Avoid 4602292SN/ADefaultRename<Impl>::renameInsts(unsigned tid) 4612292SN/A{ 4622292SN/A // Instructions can be either in the skid buffer or the queue of 4632292SN/A // instructions coming from decode, depending on the status. 4642292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4652292SN/A skidBuffer[tid].size() : insts[tid].size(); 4662292SN/A 4672292SN/A // Check the decode queue to see if instructions are available. 4682292SN/A // If there are no available instructions to rename, then do nothing. 4692292SN/A if (insts_available == 0) { 4702292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4712292SN/A tid); 4722292SN/A // Should I change status to idle? 4732292SN/A ++renameIdleCycles; 4742292SN/A return; 4752292SN/A } else if (renameStatus[tid] == Unblocking) { 4762292SN/A ++renameUnblockCycles; 4772292SN/A } else if (renameStatus[tid] == Running) { 4782292SN/A ++renameRunCycles; 4792301SN/A } 4802301SN/A 4813788Sgblack@eecs.umich.edu DynInstPtr inst; 4823788Sgblack@eecs.umich.edu 4833788Sgblack@eecs.umich.edu // Will have to do a different calculation for the number of free 4843788Sgblack@eecs.umich.edu // entries. 4853788Sgblack@eecs.umich.edu int free_rob_entries = calcFreeROBEntries(tid); 4863788Sgblack@eecs.umich.edu int free_iq_entries = calcFreeIQEntries(tid); 4873788Sgblack@eecs.umich.edu int free_lsq_entries = calcFreeLSQEntries(tid); 4883788Sgblack@eecs.umich.edu int min_free_entries = free_rob_entries; 4893798Sgblack@eecs.umich.edu 4903798Sgblack@eecs.umich.edu FullSource source = ROB; 4913798Sgblack@eecs.umich.edu 4923798Sgblack@eecs.umich.edu if (free_iq_entries < min_free_entries) { 4933798Sgblack@eecs.umich.edu min_free_entries = free_iq_entries; 4943798Sgblack@eecs.umich.edu source = IQ; 4952292SN/A } 4962292SN/A 4972292SN/A if (free_lsq_entries < min_free_entries) { 4982292SN/A min_free_entries = free_lsq_entries; 4992292SN/A source = LSQ; 5002292SN/A } 5012292SN/A 5022292SN/A // Check if there's any space left. 5032292SN/A if (min_free_entries <= 0) { 5042292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5052292SN/A "entries.\n" 5062292SN/A "ROB has %i free entries.\n" 5072292SN/A "IQ has %i free entries.\n" 5082292SN/A "LSQ has %i free entries.\n", 5092292SN/A tid, 5102292SN/A free_rob_entries, 5112292SN/A free_iq_entries, 5122292SN/A free_lsq_entries); 5132292SN/A 5142292SN/A blockThisCycle = true; 5151858SN/A 5161858SN/A block(tid); 5171858SN/A 5181858SN/A incrFullStat(source); 5191858SN/A 5202292SN/A return; 5211858SN/A } else if (min_free_entries < insts_available) { 5222292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5232292SN/A "%i insts available, but only %i insts can be " 5242292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5252292SN/A tid, insts_available, min_free_entries); 5261858SN/A 5272292SN/A insts_available = min_free_entries; 5282292SN/A 5292292SN/A blockThisCycle = true; 5302292SN/A 5312292SN/A incrFullStat(source); 5322292SN/A } 5332292SN/A 5342292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5352292SN/A skidBuffer[tid] : insts[tid]; 5362292SN/A 5372292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5382292SN/A "send iew.\n", tid, insts_available); 5392292SN/A 5401858SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5412292SN/A "dispatched to IQ last cycle.\n", 5422292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5432292SN/A 5442292SN/A // Handle serializing the next instruction if necessary. 5452292SN/A if (serializeOnNextInst[tid]) { 5462292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5472292SN/A // ROB already empty; no need to serialize. 5482292SN/A serializeOnNextInst[tid] = false; 5492292SN/A } else if (!insts_to_rename.empty()) { 5502292SN/A insts_to_rename.front()->setSerializeBefore(); 5512292SN/A } 5522292SN/A } 5532292SN/A 5542292SN/A int renamed_insts = 0; 5552292SN/A 5562292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5572292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5582292SN/A 5592292SN/A assert(!insts_to_rename.empty()); 5602292SN/A 5612292SN/A inst = insts_to_rename.front(); 5622292SN/A 5632292SN/A insts_to_rename.pop_front(); 5642292SN/A 5652292SN/A if (renameStatus[tid] == Unblocking) { 5662292SN/A DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 5672292SN/A "skidBuffer\n", 5682292SN/A tid, inst->seqNum, inst->readPC()); 5692292SN/A } 5702292SN/A 5712292SN/A if (inst->isSquashed()) { 5722292SN/A DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 5732292SN/A "squashed, skipping.\n", 5742292SN/A tid, inst->seqNum, inst->threadNumber,inst->readPC()); 5752292SN/A 5762292SN/A ++renameSquashedInsts; 5772292SN/A 5782292SN/A // Decrement how many instructions are available. 5792292SN/A --insts_available; 5802292SN/A 5812292SN/A continue; 5822292SN/A } 5832292SN/A 5842292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 5852292SN/A "PC %#x.\n", 5862292SN/A tid, inst->seqNum, inst->readPC()); 5872292SN/A 5882292SN/A // Handle serializeAfter/serializeBefore instructions. 5892292SN/A // serializeAfter marks the next instruction as serializeBefore. 5902292SN/A // serializeBefore makes the instruction wait in rename until the ROB 5912292SN/A // is empty. 5922292SN/A 5932292SN/A // In this model, IPR accesses are serialize before 5942292SN/A // instructions, and store conditionals are serialize after 5952292SN/A // instructions. This is mainly due to lack of support for 5962292SN/A // out-of-order operations of either of those classes of 5972292SN/A // instructions. 5982292SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 5992292SN/A !inst->isSerializeHandled()) { 6002292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6012292SN/A 6022292SN/A if (!inst->isTempSerializeBefore()) { 6032292SN/A renamedSerializing++; 6042292SN/A inst->setSerializeHandled(); 6052292SN/A } else { 6062292SN/A renamedTempSerializing++; 6072292SN/A } 6082292SN/A 6092292SN/A // Change status over to SerializeStall so that other stages know 6102292SN/A // what this is blocked on. 6112292SN/A renameStatus[tid] = SerializeStall; 6122292SN/A 6132292SN/A serializeInst[tid] = inst; 6142292SN/A 6152292SN/A blockThisCycle = true; 6162292SN/A 6172292SN/A break; 6182292SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6192292SN/A !inst->isSerializeHandled()) { 6202292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6212292SN/A 6222292SN/A renamedSerializing++; 6232292SN/A 6242292SN/A inst->setSerializeHandled(); 6252292SN/A 6262292SN/A serializeAfter(insts_to_rename, tid); 6272292SN/A } 6282292SN/A 6292292SN/A // Check here to make sure there are enough destination registers 6302292SN/A // to rename to. Otherwise block. 6312292SN/A if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6322292SN/A DPRINTF(Rename, "Blocking due to lack of free " 6332292SN/A "physical registers to rename to.\n"); 6342935Sksewell@umich.edu blockThisCycle = true; 6352292SN/A 6362292SN/A ++renameFullRegistersEvents; 6372292SN/A 6382292SN/A break; 6392292SN/A } 6402292SN/A 6412292SN/A renameSrcRegs(inst, inst->threadNumber); 6422292SN/A 6432292SN/A renameDestRegs(inst, inst->threadNumber); 6442292SN/A 6452292SN/A ++renamed_insts; 6462292SN/A 6472292SN/A // Put instruction in rename queue. 6482292SN/A toIEW->insts[toIEWIndex] = inst; 6492292SN/A ++(toIEW->size); 6502292SN/A 6512292SN/A // Increment which instruction we're on. 6522336SN/A ++toIEWIndex; 6532336SN/A 6542336SN/A // Decrement how many instructions are available. 6552336SN/A --insts_available; 6562336SN/A } 6572336SN/A 6582336SN/A instsInProgress[tid] += renamed_insts; 6592336SN/A renameRenamedInsts += renamed_insts; 6602292SN/A 6612292SN/A // If we wrote to the time buffer, record this. 6622301SN/A if (toIEWIndex) { 6632301SN/A wroteToTimeBuffer = true; 6642292SN/A } 6652301SN/A 6662301SN/A // Check if there's any instructions left that haven't yet been renamed. 6672301SN/A // If so then block. 6682292SN/A if (insts_available) { 6692301SN/A blockThisCycle = true; 6702292SN/A } 6712301SN/A 6722292SN/A if (blockThisCycle) { 6732301SN/A block(tid); 6742292SN/A toDecode->renameUnblock[tid] = false; 6752292SN/A } 6762292SN/A} 6772292SN/A 6782336SN/Atemplate<class Impl> 6792336SN/Avoid 6802292SN/ADefaultRename<Impl>::skidInsert(unsigned tid) 6812292SN/A{ 6822307SN/A DynInstPtr inst = NULL; 6832307SN/A 6842292SN/A while (!insts[tid].empty()) { 6852292SN/A inst = insts[tid].front(); 6862292SN/A 6872292SN/A insts[tid].pop_front(); 6882292SN/A 6892292SN/A assert(tid == inst->threadNumber); 6902292SN/A 6912292SN/A DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 6922292SN/A "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 6932292SN/A 6942292SN/A ++renameSkidInsts; 6952292SN/A 6962292SN/A skidBuffer[tid].push_back(inst); 6972292SN/A } 6982292SN/A 6992292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7002292SN/A panic("Skidbuffer Exceeded Max Size"); 7012292SN/A} 7022292SN/A 7032292SN/Atemplate <class Impl> 7042292SN/Avoid 7052292SN/ADefaultRename<Impl>::sortInsts() 7062292SN/A{ 7072292SN/A int insts_from_decode = fromDecode->size; 7082292SN/A#ifdef DEBUG 7092292SN/A for (int i=0; i < numThreads; i++) 7102292SN/A assert(insts[i].empty()); 7112292SN/A#endif 7122292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7132292SN/A DynInstPtr inst = fromDecode->insts[i]; 7142292SN/A insts[inst->threadNumber].push_back(inst); 7152292SN/A } 7162292SN/A} 7172292SN/A 7182292SN/Atemplate<class Impl> 7192307SN/Abool 7202292SN/ADefaultRename<Impl>::skidsEmpty() 7212292SN/A{ 7222292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7232292SN/A 7242292SN/A while (threads != (*activeThreads).end()) { 7252292SN/A if (!skidBuffer[*threads++].empty()) 7262292SN/A return false; 7272292SN/A } 7282292SN/A 7292292SN/A return true; 7302292SN/A} 7312292SN/A 7322292SN/Atemplate<class Impl> 7332292SN/Avoid 7342292SN/ADefaultRename<Impl>::updateStatus() 7352292SN/A{ 7362292SN/A bool any_unblocking = false; 7372292SN/A 7382292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 7392292SN/A 7402292SN/A threads = (*activeThreads).begin(); 7412292SN/A 7422292SN/A while (threads != (*activeThreads).end()) { 7432292SN/A unsigned tid = *threads++; 7442292SN/A 7452292SN/A if (renameStatus[tid] == Unblocking) { 7462292SN/A any_unblocking = true; 7472292SN/A break; 7482292SN/A } 7492292SN/A } 7502292SN/A 7512292SN/A // Rename will have activity if it's unblocking. 7522292SN/A if (any_unblocking) { 7532292SN/A if (_status == Inactive) { 7542307SN/A _status = Active; 7552307SN/A 7562292SN/A DPRINTF(Activity, "Activating stage.\n"); 7572292SN/A 7582292SN/A cpu->activateStage(FullCPU::RenameIdx); 7592292SN/A } 7603798Sgblack@eecs.umich.edu } else { 7613798Sgblack@eecs.umich.edu // If it's not unblocking, then rename will not have any internal 7623798Sgblack@eecs.umich.edu // activity. Switch it to inactive. 7633798Sgblack@eecs.umich.edu if (_status == Active) { 7643798Sgblack@eecs.umich.edu _status = Inactive; 7653798Sgblack@eecs.umich.edu DPRINTF(Activity, "Deactivating stage.\n"); 7663798Sgblack@eecs.umich.edu 7673798Sgblack@eecs.umich.edu cpu->deactivateStage(FullCPU::RenameIdx); 7683798Sgblack@eecs.umich.edu } 7692292SN/A } 7703798Sgblack@eecs.umich.edu} 7712292SN/A 7722292SN/Atemplate <class Impl> 7732292SN/Abool 7742292SN/ADefaultRename<Impl>::block(unsigned tid) 7752292SN/A{ 7762292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 7772292SN/A 7782329SN/A // Add the current inputs onto the skid buffer, so they can be 7793093Sksewell@umich.edu // reprocessed when this stage unblocks. 7802292SN/A skidInsert(tid); 7812292SN/A 7822329SN/A // Only signal backwards to block if the previous stages do not think 7832935Sksewell@umich.edu // rename is already blocked. 7842292SN/A if (renameStatus[tid] != Blocked) { 7852292SN/A if (renameStatus[tid] != Unblocking) { 7862292SN/A toDecode->renameBlock[tid] = true; 7872292SN/A toDecode->renameUnblock[tid] = false; 7882292SN/A wroteToTimeBuffer = true; 7892292SN/A } 7902292SN/A 7912292SN/A // Rename can not go from SerializeStall to Blocked, otherwise 7922292SN/A // it would not know to complete the serialize stall. 7932292SN/A if (renameStatus[tid] != SerializeStall) { 7943867Sbinkertn@umich.edu // Set status to Blocked. 7953867Sbinkertn@umich.edu renameStatus[tid] = Blocked; 7962292SN/A return true; 7973867Sbinkertn@umich.edu } 7983867Sbinkertn@umich.edu } 7993867Sbinkertn@umich.edu 8003867Sbinkertn@umich.edu return false; 8012292SN/A} 8022292SN/A 8032292SN/Atemplate <class Impl> 8042292SN/Abool 8052292SN/ADefaultRename<Impl>::unblock(unsigned tid) 8062292SN/A{ 8072292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8082292SN/A 8092292SN/A // Rename is done unblocking if the skid buffer is empty. 8102292SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8112292SN/A 8122292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8133867Sbinkertn@umich.edu 8143867Sbinkertn@umich.edu toDecode->renameUnblock[tid] = true; 8152292SN/A wroteToTimeBuffer = true; 8163867Sbinkertn@umich.edu 8172292SN/A renameStatus[tid] = Running; 8182292SN/A return true; 8192292SN/A } 8202292SN/A 8212292SN/A return false; 8222292SN/A} 8232292SN/A 8242292SN/Atemplate <class Impl> 8252292SN/Avoid 8262292SN/ADefaultRename<Impl>::doSquash(unsigned tid) 8272292SN/A{ 8282292SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 8292292SN/A 8302292SN/A InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 8312292SN/A 8322733Sktlim@umich.edu // After a syscall squashes everything, the history buffer may be empty 8332292SN/A // but the ROB may still be squashing instructions. 8342292SN/A if (historyBuffer[tid].empty()) { 8352292SN/A return; 8362292SN/A } 8372292SN/A 8382292SN/A // Go through the most recent instructions, undoing the mappings 8392292SN/A // they did and freeing up the registers. 8402292SN/A while (!historyBuffer[tid].empty() && 8412733Sktlim@umich.edu (*hb_it).instSeqNum > squashed_seq_num) { 8422292SN/A assert(hb_it != historyBuffer[tid].end()); 8432292SN/A 8442292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8452292SN/A "number %i.\n", tid, (*hb_it).instSeqNum); 8462292SN/A 8472292SN/A // Tell the rename map to set the architected register to the 8482292SN/A // previous physical register that it was renamed to. 8492292SN/A renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8502292SN/A 8512292SN/A // Put the renamed physical register back on the free list. 8522292SN/A freeList->addReg(hb_it->newPhysReg); 8532292SN/A 8542292SN/A historyBuffer[tid].erase(hb_it++); 8552292SN/A 8562292SN/A ++renameUndoneMaps; 8572292SN/A } 8582292SN/A} 8593798Sgblack@eecs.umich.edu 8603798Sgblack@eecs.umich.edutemplate<class Impl> 8613798Sgblack@eecs.umich.eduvoid 8623798Sgblack@eecs.umich.eduDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 8632292SN/A{ 8642292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 8652292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 8662292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 8672292SN/A 8682329SN/A typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 8692329SN/A 8702301SN/A --hb_it; 8712292SN/A 8722292SN/A if (historyBuffer[tid].empty()) { 8732292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 8742292SN/A return; 8752292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 8762292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 8772292SN/A "that a syscall happened recently.\n", tid); 8782292SN/A return; 8792292SN/A } 8802292SN/A 8812292SN/A // Commit all the renames up until (and including) the committed sequence 8822292SN/A // number. Some or even all of the committed instructions may not have 8832292SN/A // rename histories if they did not have destination registers that were 8842292SN/A // renamed. 8852292SN/A while (!historyBuffer[tid].empty() && 8862292SN/A hb_it != historyBuffer[tid].end() && 8872301SN/A (*hb_it).instSeqNum <= inst_seq_num) { 8882292SN/A 8892292SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 8902292SN/A "[sn:%lli].\n", 8912292SN/A tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 8922292SN/A 8932292SN/A freeList->addReg((*hb_it).prevPhysReg); 8942292SN/A ++renameCommittedMaps; 8952292SN/A 8962292SN/A historyBuffer[tid].erase(hb_it--); 8972292SN/A } 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Ainline void 9022292SN/ADefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 9032935Sksewell@umich.edu{ 9042292SN/A assert(renameMap[tid] != 0); 9052980Sgblack@eecs.umich.edu 9062980Sgblack@eecs.umich.edu unsigned num_src_regs = inst->numSrcRegs(); 9072292SN/A 9081060SN/A // Get the architectual register numbers from the source and 9091060SN/A // destination operands, and redirect them to the right register. 9102292SN/A // Will need to mark dependencies though. 9111060SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9121060SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9131060SN/A 9141060SN/A // Look up the source registers to get the phys. register they've 9151060SN/A // been renamed to, and set the sources to those registers. 9162292SN/A PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 9172292SN/A 9182292SN/A DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 9191062SN/A "physical reg %i.\n", tid, (int)src_reg, 9202292SN/A (int)renamed_reg); 9212292SN/A 9221060SN/A inst->renameSrcReg(src_idx, renamed_reg); 9232292SN/A 9242292SN/A // See if the register is ready or not. 9252292SN/A if (scoreboard->getReg(renamed_reg) == true) { 9261060SN/A DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 9272292SN/A 9282292SN/A inst->markSrcRegReady(src_idx); 9291062SN/A } 9302367SN/A 9312367SN/A ++renameRenameLookups; 9322367SN/A } 9332367SN/A} 9342367SN/A 9352292SN/Atemplate <class Impl> 9361061SN/Ainline void 9371062SN/ADefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 9381060SN/A{ 9391060SN/A typename RenameMap::RenameInfo rename_result; 9401060SN/A 9411060SN/A unsigned num_dest_regs = inst->numDestRegs(); 9421060SN/A 9432292SN/A // Rename the destination registers. 9441060SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 9452292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 9462292SN/A 9472292SN/A // Get the physical register that the destination will be 9482292SN/A // renamed to. 9492980Sgblack@eecs.umich.edu rename_result = renameMap[tid]->rename(dest_reg); 9502980Sgblack@eecs.umich.edu 9511060SN/A //Mark Scoreboard entry as not ready 9521061SN/A scoreboard->unsetReg(rename_result.first); 9531060SN/A 9542292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 9552292SN/A "reg %i.\n", tid, (int)dest_reg, 9562292SN/A (int)rename_result.first); 9572292SN/A 9582292SN/A // Record the rename information so that a history can be kept. 9592292SN/A RenameHistory hb_entry(inst->seqNum, dest_reg, 9601060SN/A rename_result.first, 9611060SN/A rename_result.second); 9621060SN/A 9632292SN/A historyBuffer[tid].push_front(hb_entry); 9642292SN/A 9652292SN/A DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 9662292SN/A "[sn:%lli].\n",tid, 9672292SN/A (*historyBuffer[tid].begin()).instSeqNum); 9682292SN/A 9692292SN/A // Tell the instruction to rename the appropriate destination 9701060SN/A // register (dest_idx) to the new physical register 9712329SN/A // (rename_result.first), and record the previous physical 9722329SN/A // register that the same logical register was renamed to 9732292SN/A // (rename_result.second). 9741061SN/A inst->renameDestReg(dest_idx, 9752292SN/A rename_result.first, 9762292SN/A rename_result.second); 9771061SN/A 9782292SN/A ++renameRenamedOperands; 9791060SN/A } 9801060SN/A} 9811060SN/A 9821061SN/Atemplate <class Impl> 9831061SN/Ainline int 9842292SN/ADefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 9851061SN/A{ 9862292SN/A int num_free = freeEntries[tid].robEntries - 9872292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 9881061SN/A 9891061SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 9901061SN/A 9911061SN/A return num_free; 9921061SN/A} 9932292SN/A 9941061SN/Atemplate <class Impl> 9953773Sgblack@eecs.umich.eduinline int 9963773Sgblack@eecs.umich.eduDefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 9973773Sgblack@eecs.umich.edu{ 9983773Sgblack@eecs.umich.edu int num_free = freeEntries[tid].iqEntries - 9993773Sgblack@eecs.umich.edu (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 10003773Sgblack@eecs.umich.edu 10011061SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 10021061SN/A 10031061SN/A return num_free; 10043773Sgblack@eecs.umich.edu} 10051061SN/A 10062292SN/Atemplate <class Impl> 10073773Sgblack@eecs.umich.eduinline int 10082292SN/ADefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 10091061SN/A{ 10101061SN/A int num_free = freeEntries[tid].lsqEntries - 10111061SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 10122292SN/A 10132292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 10142292SN/A 10151061SN/A return num_free; 10161061SN/A} 10171061SN/A 10181062SN/Atemplate <class Impl> 10191062SN/Aunsigned 10201061SN/ADefaultRename<Impl>::validInsts() 10211061SN/A{ 10221061SN/A unsigned inst_count = 0; 10231061SN/A 10241061SN/A for (int i=0; i<fromDecode->size; i++) { 10252292SN/A if (!fromDecode->insts[i]->squashed) 10261061SN/A inst_count++; 10272292SN/A } 10281061SN/A 10291061SN/A return inst_count; 10301061SN/A} 10312292SN/A 10322292SN/Atemplate <class Impl> 10332292SN/Avoid 10343773Sgblack@eecs.umich.eduDefaultRename<Impl>::readStallSignals(unsigned tid) 10353773Sgblack@eecs.umich.edu{ 10363773Sgblack@eecs.umich.edu if (fromIEW->iewBlock[tid]) { 10373773Sgblack@eecs.umich.edu stalls[tid].iew = true; 10383773Sgblack@eecs.umich.edu } 10393773Sgblack@eecs.umich.edu 10403773Sgblack@eecs.umich.edu if (fromIEW->iewUnblock[tid]) { 10411061SN/A assert(stalls[tid].iew); 10422292SN/A stalls[tid].iew = false; 10432292SN/A } 10443773Sgblack@eecs.umich.edu 10451061SN/A if (fromCommit->commitBlock[tid]) { 10462292SN/A stalls[tid].commit = true; 10472292SN/A } 10481062SN/A 10492292SN/A if (fromCommit->commitUnblock[tid]) { 10503773Sgblack@eecs.umich.edu assert(stalls[tid].commit); 10512292SN/A stalls[tid].commit = false; 10521062SN/A } 10532292SN/A} 10543773Sgblack@eecs.umich.edu 10552292SN/Atemplate <class Impl> 10562292SN/Abool 10571062SN/ADefaultRename<Impl>::checkStall(unsigned tid) 10582292SN/A{ 10591062SN/A bool ret_val = false; 10602935Sksewell@umich.edu 10612935Sksewell@umich.edu if (stalls[tid].iew) { 10622935Sksewell@umich.edu DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 10632292SN/A ret_val = true; 10641062SN/A } else if (stalls[tid].commit) { 10652292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 10662292SN/A ret_val = true; 10672292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 10682292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 10692292SN/A ret_val = true; 10702292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 10712292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 10722292SN/A ret_val = true; 10731062SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 10742292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 10751061SN/A ret_val = true; 10761061SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 10771061SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 10781061SN/A ret_val = true; 10791061SN/A } else if (renameStatus[tid] == SerializeStall && 10802292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 10811061SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 10822292SN/A "empty.\n", 10832292SN/A tid); 10842292SN/A ret_val = true; 10852292SN/A } 10862292SN/A 10872292SN/A return ret_val; 10881061SN/A} 10891061SN/A 10901061SN/Atemplate <class Impl> 10911061SN/Avoid 10922292SN/ADefaultRename<Impl>::readFreeEntries(unsigned tid) 10931061SN/A{ 10942292SN/A bool updated = false; 10952292SN/A if (fromIEW->iewInfo[tid].usedIQ) { 10962292SN/A freeEntries[tid].iqEntries = 10972292SN/A fromIEW->iewInfo[tid].freeIQEntries; 10982292SN/A updated = true; 10992292SN/A } 11002292SN/A 11012292SN/A if (fromIEW->iewInfo[tid].usedLSQ) { 11022292SN/A freeEntries[tid].lsqEntries = 11032292SN/A fromIEW->iewInfo[tid].freeLSQEntries; 11042292SN/A updated = true; 11052292SN/A } 11062292SN/A 11072292SN/A if (fromCommit->commitInfo[tid].usedROB) { 11082292SN/A freeEntries[tid].robEntries = 11092292SN/A fromCommit->commitInfo[tid].freeROBEntries; 11102292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 11112292SN/A updated = true; 11122292SN/A } 11132292SN/A 11142292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 11152292SN/A tid, 11162292SN/A freeEntries[tid].iqEntries, 11172292SN/A freeEntries[tid].robEntries, 11182292SN/A freeEntries[tid].lsqEntries); 11192292SN/A 11202292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 11212731Sktlim@umich.edu tid, instsInProgress[tid]); 11222292SN/A} 11232292SN/A 11242292SN/Atemplate <class Impl> 11252292SN/Abool 11262292SN/ADefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 11272292SN/A{ 11282292SN/A // Check if there's a squash signal, squash if there is 11292292SN/A // Check stall signals, block if necessary. 11302292SN/A // If status was blocked 11312292SN/A // check if stall conditions have passed 11322292SN/A // if so then go to unblocking 11332292SN/A // If status was Squashing 11342292SN/A // check if squashing is not high. Switch to running this cycle. 11352292SN/A // If status was serialize stall 11362292SN/A // check if ROB is empty and no insts are in flight to the ROB 11372292SN/A 11382292SN/A readFreeEntries(tid); 11392292SN/A readStallSignals(tid); 11402292SN/A 11412292SN/A if (fromCommit->commitInfo[tid].squash) { 11422292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 11432292SN/A "commit.\n", tid); 11442292SN/A 11452292SN/A squash(tid); 11462292SN/A 11472292SN/A return true; 11482292SN/A } 11492292SN/A 11502292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 11512292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 11522292SN/A 11532292SN/A renameStatus[tid] = Squashing; 11542292SN/A 11552292SN/A return true; 11562292SN/A } 11572292SN/A 11582292SN/A if (checkStall(tid)) { 11592292SN/A return block(tid); 11602292SN/A } 11612292SN/A 11622292SN/A if (renameStatus[tid] == Blocked) { 11632292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 11642292SN/A tid); 11652292SN/A 11662292SN/A renameStatus[tid] = Unblocking; 11672292SN/A 11682292SN/A unblock(tid); 11692292SN/A 11702292SN/A return true; 11712292SN/A } 11722292SN/A 11732292SN/A if (renameStatus[tid] == Squashing) { 11742292SN/A // Switch status to running if rename isn't being told to block or 11752301SN/A // squash this cycle. 11762292SN/A DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 11772301SN/A tid); 11782292SN/A 11792292SN/A renameStatus[tid] = Running; 11802292SN/A 11812292SN/A return false; 11822292SN/A } 11832292SN/A 11842292SN/A if (renameStatus[tid] == SerializeStall) { 11852292SN/A // Stall ends once the ROB is free. 11862292SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 11872292SN/A "unblocking.\n", tid); 11882292SN/A 11892292SN/A DynInstPtr serial_inst = serializeInst[tid]; 11902292SN/A 11912292SN/A renameStatus[tid] = Unblocking; 11922292SN/A 11932292SN/A unblock(tid); 11942292SN/A 11952292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 11962292SN/A "PC %#x.\n", 11972292SN/A tid, serial_inst->seqNum, serial_inst->readPC()); 11982292SN/A 11992292SN/A // Put instruction into queue here. 12002292SN/A serial_inst->clearSerializeBefore(); 12012292SN/A 12022292SN/A if (!skidBuffer[tid].empty()) { 12032292SN/A skidBuffer[tid].push_front(serial_inst); 12042292SN/A } else { 12052292SN/A insts[tid].push_front(serial_inst); 12062292SN/A } 12072292SN/A 12082292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 12092292SN/A " Adding to front of list.\n", tid); 12102292SN/A 12112292SN/A serializeInst[tid] = NULL; 12122292SN/A 12132292SN/A return true; 12142292SN/A } 12152292SN/A 12162292SN/A // If we've reached this point, we have not gotten any signals that 12172292SN/A // cause rename to change its status. Rename remains the same as before. 12182292SN/A return false; 12192292SN/A} 12202292SN/A 12212292SN/Atemplate<class Impl> 12222292SN/Avoid 12232292SN/ADefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 12242292SN/A unsigned tid) 12252292SN/A{ 12262292SN/A if (inst_list.empty()) { 12272292SN/A // Mark a bit to say that I must serialize on the next instruction. 12282292SN/A serializeOnNextInst[tid] = true; 12292292SN/A return; 12302292SN/A } 12312301SN/A 12322292SN/A // Set the next instruction as serializing. 12332292SN/A inst_list.front()->setSerializeBefore(); 12342292SN/A} 12352292SN/A 12362292SN/Atemplate <class Impl> 12372292SN/Ainline void 12382292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 12392292SN/A{ 12402292SN/A switch (source) { 12413093Sksewell@umich.edu case ROB: 12423093Sksewell@umich.edu ++renameROBFullEvents; 12433093Sksewell@umich.edu break; 12442935Sksewell@umich.edu case IQ: 12452935Sksewell@umich.edu ++renameIQFullEvents; 12462935Sksewell@umich.edu break; 12472935Sksewell@umich.edu case LSQ: 12482292SN/A ++renameLSQFullEvents; 12492292SN/A break; 12502292SN/A default: 12512292SN/A panic("Rename full stall stat should be incremented for a reason!"); 12522292SN/A break; 12532292SN/A } 12542292SN/A} 12552292SN/A 12562292SN/Atemplate <class Impl> 12572292SN/Avoid 12582292SN/ADefaultRename<Impl>::dumpHistory() 12592292SN/A{ 12602292SN/A typename list<RenameHistory>::iterator buf_it; 12612292SN/A 12622292SN/A for (int i = 0; i < numThreads; i++) { 12632292SN/A 12642292SN/A buf_it = historyBuffer[i].begin(); 12652292SN/A 12662292SN/A while (buf_it != historyBuffer[i].end()) { 12672292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 12682292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 12692292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 12702292SN/A 12712292SN/A buf_it++; 12722292SN/A } 12732292SN/A } 12742292SN/A} 12752292SN/A