rename_impl.hh revision 2698
12914SN/A/* 28856SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 38856SN/A * All rights reserved. 48856SN/A * 58856SN/A * Redistribution and use in source and binary forms, with or without 68856SN/A * modification, are permitted provided that the following conditions are 78856SN/A * met: redistributions of source code must retain the above copyright 88856SN/A * notice, this list of conditions and the following disclaimer; 98856SN/A * redistributions in binary form must reproduce the above copyright 108856SN/A * notice, this list of conditions and the following disclaimer in the 118856SN/A * documentation and/or other materials provided with the distribution; 128856SN/A * neither the name of the copyright holders nor the names of its 138856SN/A * contributors may be used to endorse or promote products derived from 142914SN/A * this software without specific prior written permission. 152914SN/A * 162914SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914SN/A * 282914SN/A * Authors: Kevin Lim 292914SN/A */ 302914SN/A 312914SN/A#include <list> 322914SN/A 332914SN/A#include "config/full_system.hh" 342914SN/A#include "cpu/o3/rename.hh" 352914SN/A 362914SN/Ausing namespace std; 372914SN/A 382914SN/Atemplate <class Impl> 392914SN/ADefaultRename<Impl>::DefaultRename(Params *params) 402914SN/A : iewToRenameDelay(params->iewToRenameDelay), 418856SN/A decodeToRenameDelay(params->decodeToRenameDelay), 422914SN/A commitToRenameDelay(params->commitToRenameDelay), 432914SN/A renameWidth(params->renameWidth), 448914Sandreas.hansson@arm.com commitWidth(params->commitWidth), 458914Sandreas.hansson@arm.com numThreads(params->numberOfThreads) 463091SN/A{ 472914SN/A _status = Inactive; 482914SN/A 498914Sandreas.hansson@arm.com for (int i=0; i< numThreads; i++) { 508914Sandreas.hansson@arm.com renameStatus[i] = Idle; 518914Sandreas.hansson@arm.com 528914Sandreas.hansson@arm.com freeEntries[i].iqEntries = 0; 538914Sandreas.hansson@arm.com freeEntries[i].lsqEntries = 0; 542914SN/A freeEntries[i].robEntries = 0; 552914SN/A 568229SN/A stalls[i].iew = false; 578229SN/A stalls[i].commit = false; 582914SN/A serializeInst[i] = NULL; 599342SAndreas.Sandberg@arm.com 609356Snilay@cs.wisc.edu instsInProgress[i] = 0; 612914SN/A 623091SN/A emptyROB[i] = true; 638914Sandreas.hansson@arm.com 648914Sandreas.hansson@arm.com serializeOnNextInst[i] = false; 653091SN/A } 669342SAndreas.Sandberg@arm.com 672914SN/A // @todo: Make into a parameter. 688914Sandreas.hansson@arm.com skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth; 694490SN/A} 704490SN/A 714490SN/Atemplate <class Impl> 724490SN/Astd::string 734490SN/ADefaultRename<Impl>::name() const 748948Sandreas.hansson@arm.com{ 758948Sandreas.hansson@arm.com return cpu->name() + ".rename"; 768948Sandreas.hansson@arm.com} 774490SN/A 784490SN/Atemplate <class Impl> 794490SN/Avoid 804490SN/ADefaultRename<Impl>::regStats() 814490SN/A{ 823090SN/A renameSquashCycles 833090SN/A .name(name() + ".RENAME:SquashCycles") 844490SN/A .desc("Number of cycles rename is squashing") 854490SN/A .prereq(renameSquashCycles); 868914Sandreas.hansson@arm.com renameIdleCycles 878914Sandreas.hansson@arm.com .name(name() + ".RENAME:IdleCycles") 888914Sandreas.hansson@arm.com .desc("Number of cycles rename is idle") 894490SN/A .prereq(renameIdleCycles); 904490SN/A renameBlockCycles 914490SN/A .name(name() + ".RENAME:BlockCycles") 923091SN/A .desc("Number of cycles rename is blocking") 932914SN/A .prereq(renameBlockCycles); 948914Sandreas.hansson@arm.com renameSerializeStallCycles 953403SN/A .name(name() + ".RENAME:serializeStallCycles") 968914Sandreas.hansson@arm.com .desc("count of cycles rename stalled for serializing inst") 972914SN/A .flags(Stats::total); 989342SAndreas.Sandberg@arm.com renameRunCycles 992914SN/A .name(name() + ".RENAME:RunCycles") 1009342SAndreas.Sandberg@arm.com .desc("Number of cycles rename is running") 1012914SN/A .prereq(renameIdleCycles); 1028914Sandreas.hansson@arm.com renameUnblockCycles 1038914Sandreas.hansson@arm.com .name(name() + ".RENAME:UnblockCycles") 1048975Sandreas.hansson@arm.com .desc("Number of cycles rename is unblocking") 1058975Sandreas.hansson@arm.com .prereq(renameUnblockCycles); 1068914Sandreas.hansson@arm.com renameRenamedInsts 1074492SN/A .name(name() + ".RENAME:RenamedInsts") 1084492SN/A .desc("Number of instructions processed by rename") 1094492SN/A .prereq(renameRenamedInsts); 1104492SN/A renameSquashedInsts 11110322Sandreas.hansson@arm.com .name(name() + ".RENAME:SquashedInsts") 1127823SN/A .desc("Number of squashed instructions processed by rename") 1134492SN/A .prereq(renameSquashedInsts); 11410322Sandreas.hansson@arm.com renameROBFullEvents 1154666SN/A .name(name() + ".RENAME:ROBFullEvents") 1164666SN/A .desc("Number of times rename has blocked due to ROB full") 1178708SN/A .prereq(renameROBFullEvents); 1188914Sandreas.hansson@arm.com renameIQFullEvents 1198914Sandreas.hansson@arm.com .name(name() + ".RENAME:IQFullEvents") 1208914Sandreas.hansson@arm.com .desc("Number of times rename has blocked due to IQ full") 1218914Sandreas.hansson@arm.com .prereq(renameIQFullEvents); 1228914Sandreas.hansson@arm.com renameLSQFullEvents 1234492SN/A .name(name() + ".RENAME:LSQFullEvents") 1248856SN/A .desc("Number of times rename has blocked due to LSQ full") 1258856SN/A .prereq(renameLSQFullEvents); 1268856SN/A renameFullRegistersEvents 1278856SN/A .name(name() + ".RENAME:FullRegisterEvents") 1288856SN/A .desc("Number of times there has been no free registers") 1298856SN/A .prereq(renameFullRegistersEvents); 1308856SN/A renameRenamedOperands 1318856SN/A .name(name() + ".RENAME:RenamedOperands") 1328856SN/A .desc("Number of destination operands rename has renamed") 1338856SN/A .prereq(renameRenamedOperands); 1348856SN/A renameRenameLookups 1358975Sandreas.hansson@arm.com .name(name() + ".RENAME:RenameLookups") 1368975Sandreas.hansson@arm.com .desc("Number of register rename lookups that rename has made") 1378975Sandreas.hansson@arm.com .prereq(renameRenameLookups); 1388975Sandreas.hansson@arm.com renameCommittedMaps 1398975Sandreas.hansson@arm.com .name(name() + ".RENAME:CommittedMaps") 1408856SN/A .desc("Number of HB maps that are committed") 1418856SN/A .prereq(renameCommittedMaps); 1428856SN/A renameUndoneMaps 1438856SN/A .name(name() + ".RENAME:UndoneMaps") 1448856SN/A .desc("Number of HB maps that are undone due to squashing") 1458856SN/A .prereq(renameUndoneMaps); 1468856SN/A renamedSerializing 1472914SN/A .name(name() + ".RENAME:serializingInsts") 1483091SN/A .desc("count of serializing insts renamed") 1498711SN/A .flags(Stats::total) 1508711SN/A ; 1518711SN/A renamedTempSerializing 1528711SN/A .name(name() + ".RENAME:tempSerializingInsts") 1538711SN/A .desc("count of temporary serializing insts renamed") 1548711SN/A .flags(Stats::total) 1558711SN/A ; 1563091SN/A renameSkidInsts 1578914Sandreas.hansson@arm.com .name(name() + ".RENAME:skidInsts") 1588975Sandreas.hansson@arm.com .desc("count of insts added to the skid buffer") 1598975Sandreas.hansson@arm.com .flags(Stats::total) 1608914Sandreas.hansson@arm.com ; 1618914Sandreas.hansson@arm.com} 1628914Sandreas.hansson@arm.com 1638914Sandreas.hansson@arm.comtemplate <class Impl> 1648975Sandreas.hansson@arm.comvoid 1658914Sandreas.hansson@arm.comDefaultRename<Impl>::setCPU(FullCPU *cpu_ptr) 1668914Sandreas.hansson@arm.com{ 1678914Sandreas.hansson@arm.com DPRINTF(Rename, "Setting CPU pointer.\n"); 1688914Sandreas.hansson@arm.com cpu = cpu_ptr; 1698914Sandreas.hansson@arm.com} 1708914Sandreas.hansson@arm.com 1718975Sandreas.hansson@arm.comtemplate <class Impl> 1728975Sandreas.hansson@arm.comvoid 1738914Sandreas.hansson@arm.comDefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1748975Sandreas.hansson@arm.com{ 1758914Sandreas.hansson@arm.com DPRINTF(Rename, "Setting time buffer pointer.\n"); 1768914Sandreas.hansson@arm.com timeBuffer = tb_ptr; 1778914Sandreas.hansson@arm.com 1788975Sandreas.hansson@arm.com // Setup wire to read information from time buffer, from IEW stage. 1794490SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1808856SN/A 1818856SN/A // Setup wire to read infromation from time buffer, from commit stage. 1828856SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1838856SN/A 1848914Sandreas.hansson@arm.com // Setup wire to write information to previous stages. 1858914Sandreas.hansson@arm.com toDecode = timeBuffer->getWire(0); 1868914Sandreas.hansson@arm.com} 1878914Sandreas.hansson@arm.com 1888914Sandreas.hansson@arm.comtemplate <class Impl> 1898914Sandreas.hansson@arm.comvoid 1908914Sandreas.hansson@arm.comDefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 1918914Sandreas.hansson@arm.com{ 1928914Sandreas.hansson@arm.com DPRINTF(Rename, "Setting rename queue pointer.\n"); 1938914Sandreas.hansson@arm.com renameQueue = rq_ptr; 1948914Sandreas.hansson@arm.com 1958914Sandreas.hansson@arm.com // Setup wire to write information to future stages. 1968914Sandreas.hansson@arm.com toIEW = renameQueue->getWire(0); 1978914Sandreas.hansson@arm.com} 1988914Sandreas.hansson@arm.com 1998948Sandreas.hansson@arm.comtemplate <class Impl> 2008914Sandreas.hansson@arm.comvoid 2018948Sandreas.hansson@arm.comDefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2028914Sandreas.hansson@arm.com{ 2038914Sandreas.hansson@arm.com DPRINTF(Rename, "Setting decode queue pointer.\n"); 2048914Sandreas.hansson@arm.com decodeQueue = dq_ptr; 2058914Sandreas.hansson@arm.com 2068914Sandreas.hansson@arm.com // Setup wire to get information from decode. 2078914Sandreas.hansson@arm.com fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2088914Sandreas.hansson@arm.com} 2098914Sandreas.hansson@arm.com 2109342SAndreas.Sandberg@arm.comtemplate <class Impl> 2112914SN/Avoid 2122914SN/ADefaultRename<Impl>::initStage() 2138975Sandreas.hansson@arm.com{ 2148975Sandreas.hansson@arm.com // Grab the number of free entries directly from the stages. 2158975Sandreas.hansson@arm.com for (int tid=0; tid < numThreads; tid++) { 2168975Sandreas.hansson@arm.com freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2178975Sandreas.hansson@arm.com freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2188975Sandreas.hansson@arm.com freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2198975Sandreas.hansson@arm.com emptyROB[tid] = true; 2208975Sandreas.hansson@arm.com } 2218975Sandreas.hansson@arm.com} 2228975Sandreas.hansson@arm.com 2238975Sandreas.hansson@arm.comtemplate<class Impl> 2248975Sandreas.hansson@arm.comvoid 2258975Sandreas.hansson@arm.comDefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr) 2268975Sandreas.hansson@arm.com{ 2278975Sandreas.hansson@arm.com DPRINTF(Rename, "Setting active threads list pointer.\n"); 2288975Sandreas.hansson@arm.com activeThreads = at_ptr; 2298975Sandreas.hansson@arm.com} 2308975Sandreas.hansson@arm.com 2318975Sandreas.hansson@arm.com 2328975Sandreas.hansson@arm.comtemplate <class Impl> 2338975Sandreas.hansson@arm.comvoid 2348975Sandreas.hansson@arm.comDefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2358975Sandreas.hansson@arm.com{ 2368975Sandreas.hansson@arm.com DPRINTF(Rename, "Setting rename map pointers.\n"); 2378975Sandreas.hansson@arm.com 2388975Sandreas.hansson@arm.com for (int i=0; i<numThreads; i++) { 2398975Sandreas.hansson@arm.com renameMap[i] = &rm_ptr[i]; 2408975Sandreas.hansson@arm.com } 2418975Sandreas.hansson@arm.com} 2428975Sandreas.hansson@arm.com 2438975Sandreas.hansson@arm.comtemplate <class Impl> 2448975Sandreas.hansson@arm.comvoid 2458975Sandreas.hansson@arm.comDefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2468975Sandreas.hansson@arm.com{ 2478975Sandreas.hansson@arm.com DPRINTF(Rename, "Setting free list pointer.\n"); 2488975Sandreas.hansson@arm.com freeList = fl_ptr; 2498975Sandreas.hansson@arm.com} 2508975Sandreas.hansson@arm.com 2518975Sandreas.hansson@arm.comtemplate<class Impl> 2528975Sandreas.hansson@arm.comvoid 2538975Sandreas.hansson@arm.comDefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2548975Sandreas.hansson@arm.com{ 2558975Sandreas.hansson@arm.com DPRINTF(Rename, "Setting scoreboard pointer.\n"); 2568975Sandreas.hansson@arm.com scoreboard = _scoreboard; 2578975Sandreas.hansson@arm.com} 2588975Sandreas.hansson@arm.com 2598975Sandreas.hansson@arm.comtemplate <class Impl> 2608975Sandreas.hansson@arm.comvoid 2618975Sandreas.hansson@arm.comDefaultRename<Impl>::switchOut() 2628975Sandreas.hansson@arm.com{ 2638975Sandreas.hansson@arm.com // Rename is ready to switch out at any time. 2648975Sandreas.hansson@arm.com cpu->signalSwitched(); 2658975Sandreas.hansson@arm.com} 2668975Sandreas.hansson@arm.com 2678975Sandreas.hansson@arm.comtemplate <class Impl> 2688975Sandreas.hansson@arm.comvoid 2698975Sandreas.hansson@arm.comDefaultRename<Impl>::doSwitchOut() 2708975Sandreas.hansson@arm.com{ 2718975Sandreas.hansson@arm.com // Clear any state, fix up the rename map. 2728948Sandreas.hansson@arm.com for (int i = 0; i < numThreads; i++) { 273 typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin(); 274 275 while (!historyBuffer[i].empty()) { 276 assert(hb_it != historyBuffer[i].end()); 277 278 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 279 "number %i.\n", i, (*hb_it).instSeqNum); 280 281 // Tell the rename map to set the architected register to the 282 // previous physical register that it was renamed to. 283 renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 284 285 // Put the renamed physical register back on the free list. 286 freeList->addReg(hb_it->newPhysReg); 287 288 historyBuffer[i].erase(hb_it++); 289 } 290 insts[i].clear(); 291 skidBuffer[i].clear(); 292 } 293} 294 295template <class Impl> 296void 297DefaultRename<Impl>::takeOverFrom() 298{ 299 _status = Inactive; 300 initStage(); 301 302 // Reset all state prior to taking over from the other CPU. 303 for (int i=0; i< numThreads; i++) { 304 renameStatus[i] = Idle; 305 306 stalls[i].iew = false; 307 stalls[i].commit = false; 308 serializeInst[i] = NULL; 309 310 instsInProgress[i] = 0; 311 312 emptyROB[i] = true; 313 314 serializeOnNextInst[i] = false; 315 } 316} 317 318template <class Impl> 319void 320DefaultRename<Impl>::squash(unsigned tid) 321{ 322 DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 323 324 // Clear the stall signal if rename was blocked or unblocking before. 325 // If it still needs to block, the blocking should happen the next 326 // cycle and there should be space to hold everything due to the squash. 327 if (renameStatus[tid] == Blocked || 328 renameStatus[tid] == Unblocking || 329 renameStatus[tid] == SerializeStall) { 330 331 toDecode->renameUnblock[tid] = 1; 332 333 serializeInst[tid] = NULL; 334 } 335 336 // Set the status to Squashing. 337 renameStatus[tid] = Squashing; 338 339 // Squash any instructions from decode. 340 unsigned squashCount = 0; 341 342 for (int i=0; i<fromDecode->size; i++) { 343 if (fromDecode->insts[i]->threadNumber == tid) { 344 fromDecode->insts[i]->squashed = true; 345 wroteToTimeBuffer = true; 346 squashCount++; 347 } 348 } 349 350 insts[tid].clear(); 351 352 // Clear the skid buffer in case it has any data in it. 353 skidBuffer[tid].clear(); 354 355 doSquash(tid); 356} 357 358template <class Impl> 359void 360DefaultRename<Impl>::tick() 361{ 362 wroteToTimeBuffer = false; 363 364 blockThisCycle = false; 365 366 bool status_change = false; 367 368 toIEWIndex = 0; 369 370 sortInsts(); 371 372 list<unsigned>::iterator threads = (*activeThreads).begin(); 373 374 // Check stall and squash signals. 375 while (threads != (*activeThreads).end()) { 376 unsigned tid = *threads++; 377 378 DPRINTF(Rename, "Processing [tid:%i]\n", tid); 379 380 status_change = checkSignalsAndUpdate(tid) || status_change; 381 382 rename(status_change, tid); 383 } 384 385 if (status_change) { 386 updateStatus(); 387 } 388 389 if (wroteToTimeBuffer) { 390 DPRINTF(Activity, "Activity this cycle.\n"); 391 cpu->activityThisCycle(); 392 } 393 394 threads = (*activeThreads).begin(); 395 396 while (threads != (*activeThreads).end()) { 397 unsigned tid = *threads++; 398 399 // If we committed this cycle then doneSeqNum will be > 0 400 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 401 !fromCommit->commitInfo[tid].squash && 402 renameStatus[tid] != Squashing) { 403 404 removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 405 tid); 406 } 407 } 408 409 // @todo: make into updateProgress function 410 for (int tid=0; tid < numThreads; tid++) { 411 instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 412 413 assert(instsInProgress[tid] >=0); 414 } 415 416} 417 418template<class Impl> 419void 420DefaultRename<Impl>::rename(bool &status_change, unsigned tid) 421{ 422 // If status is Running or idle, 423 // call renameInsts() 424 // If status is Unblocking, 425 // buffer any instructions coming from decode 426 // continue trying to empty skid buffer 427 // check if stall conditions have passed 428 429 if (renameStatus[tid] == Blocked) { 430 ++renameBlockCycles; 431 } else if (renameStatus[tid] == Squashing) { 432 ++renameSquashCycles; 433 } else if (renameStatus[tid] == SerializeStall) { 434 ++renameSerializeStallCycles; 435 } 436 437 if (renameStatus[tid] == Running || 438 renameStatus[tid] == Idle) { 439 DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 440 "stage.\n", tid); 441 442 renameInsts(tid); 443 } else if (renameStatus[tid] == Unblocking) { 444 renameInsts(tid); 445 446 if (validInsts()) { 447 // Add the current inputs to the skid buffer so they can be 448 // reprocessed when this stage unblocks. 449 skidInsert(tid); 450 } 451 452 // If we switched over to blocking, then there's a potential for 453 // an overall status change. 454 status_change = unblock(tid) || status_change || blockThisCycle; 455 } 456} 457 458template <class Impl> 459void 460DefaultRename<Impl>::renameInsts(unsigned tid) 461{ 462 // Instructions can be either in the skid buffer or the queue of 463 // instructions coming from decode, depending on the status. 464 int insts_available = renameStatus[tid] == Unblocking ? 465 skidBuffer[tid].size() : insts[tid].size(); 466 467 // Check the decode queue to see if instructions are available. 468 // If there are no available instructions to rename, then do nothing. 469 if (insts_available == 0) { 470 DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 471 tid); 472 // Should I change status to idle? 473 ++renameIdleCycles; 474 return; 475 } else if (renameStatus[tid] == Unblocking) { 476 ++renameUnblockCycles; 477 } else if (renameStatus[tid] == Running) { 478 ++renameRunCycles; 479 } 480 481 DynInstPtr inst; 482 483 // Will have to do a different calculation for the number of free 484 // entries. 485 int free_rob_entries = calcFreeROBEntries(tid); 486 int free_iq_entries = calcFreeIQEntries(tid); 487 int free_lsq_entries = calcFreeLSQEntries(tid); 488 int min_free_entries = free_rob_entries; 489 490 FullSource source = ROB; 491 492 if (free_iq_entries < min_free_entries) { 493 min_free_entries = free_iq_entries; 494 source = IQ; 495 } 496 497 if (free_lsq_entries < min_free_entries) { 498 min_free_entries = free_lsq_entries; 499 source = LSQ; 500 } 501 502 // Check if there's any space left. 503 if (min_free_entries <= 0) { 504 DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 505 "entries.\n" 506 "ROB has %i free entries.\n" 507 "IQ has %i free entries.\n" 508 "LSQ has %i free entries.\n", 509 tid, 510 free_rob_entries, 511 free_iq_entries, 512 free_lsq_entries); 513 514 blockThisCycle = true; 515 516 block(tid); 517 518 incrFullStat(source); 519 520 return; 521 } else if (min_free_entries < insts_available) { 522 DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 523 "%i insts available, but only %i insts can be " 524 "renamed due to ROB/IQ/LSQ limits.\n", 525 tid, insts_available, min_free_entries); 526 527 insts_available = min_free_entries; 528 529 blockThisCycle = true; 530 531 incrFullStat(source); 532 } 533 534 InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 535 skidBuffer[tid] : insts[tid]; 536 537 DPRINTF(Rename, "[tid:%u]: %i available instructions to " 538 "send iew.\n", tid, insts_available); 539 540 DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 541 "dispatched to IQ last cycle.\n", 542 tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 543 544 // Handle serializing the next instruction if necessary. 545 if (serializeOnNextInst[tid]) { 546 if (emptyROB[tid] && instsInProgress[tid] == 0) { 547 // ROB already empty; no need to serialize. 548 serializeOnNextInst[tid] = false; 549 } else if (!insts_to_rename.empty()) { 550 insts_to_rename.front()->setSerializeBefore(); 551 } 552 } 553 554 int renamed_insts = 0; 555 556 while (insts_available > 0 && toIEWIndex < renameWidth) { 557 DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 558 559 assert(!insts_to_rename.empty()); 560 561 inst = insts_to_rename.front(); 562 563 insts_to_rename.pop_front(); 564 565 if (renameStatus[tid] == Unblocking) { 566 DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename " 567 "skidBuffer\n", 568 tid, inst->seqNum, inst->readPC()); 569 } 570 571 if (inst->isSquashed()) { 572 DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is " 573 "squashed, skipping.\n", 574 tid, inst->seqNum, inst->threadNumber,inst->readPC()); 575 576 ++renameSquashedInsts; 577 578 // Decrement how many instructions are available. 579 --insts_available; 580 581 continue; 582 } 583 584 DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 585 "PC %#x.\n", 586 tid, inst->seqNum, inst->readPC()); 587 588 // Handle serializeAfter/serializeBefore instructions. 589 // serializeAfter marks the next instruction as serializeBefore. 590 // serializeBefore makes the instruction wait in rename until the ROB 591 // is empty. 592 593 // In this model, IPR accesses are serialize before 594 // instructions, and store conditionals are serialize after 595 // instructions. This is mainly due to lack of support for 596 // out-of-order operations of either of those classes of 597 // instructions. 598 if ((inst->isIprAccess() || inst->isSerializeBefore()) && 599 !inst->isSerializeHandled()) { 600 DPRINTF(Rename, "Serialize before instruction encountered.\n"); 601 602 if (!inst->isTempSerializeBefore()) { 603 renamedSerializing++; 604 inst->setSerializeHandled(); 605 } else { 606 renamedTempSerializing++; 607 } 608 609 // Change status over to SerializeStall so that other stages know 610 // what this is blocked on. 611 renameStatus[tid] = SerializeStall; 612 613 serializeInst[tid] = inst; 614 615 blockThisCycle = true; 616 617 break; 618 } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 619 !inst->isSerializeHandled()) { 620 DPRINTF(Rename, "Serialize after instruction encountered.\n"); 621 622 renamedSerializing++; 623 624 inst->setSerializeHandled(); 625 626 serializeAfter(insts_to_rename, tid); 627 } 628 629 // Check here to make sure there are enough destination registers 630 // to rename to. Otherwise block. 631 if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 632 DPRINTF(Rename, "Blocking due to lack of free " 633 "physical registers to rename to.\n"); 634 blockThisCycle = true; 635 636 ++renameFullRegistersEvents; 637 638 break; 639 } 640 641 renameSrcRegs(inst, inst->threadNumber); 642 643 renameDestRegs(inst, inst->threadNumber); 644 645 ++renamed_insts; 646 647 // Put instruction in rename queue. 648 toIEW->insts[toIEWIndex] = inst; 649 ++(toIEW->size); 650 651 // Increment which instruction we're on. 652 ++toIEWIndex; 653 654 // Decrement how many instructions are available. 655 --insts_available; 656 } 657 658 instsInProgress[tid] += renamed_insts; 659 renameRenamedInsts += renamed_insts; 660 661 // If we wrote to the time buffer, record this. 662 if (toIEWIndex) { 663 wroteToTimeBuffer = true; 664 } 665 666 // Check if there's any instructions left that haven't yet been renamed. 667 // If so then block. 668 if (insts_available) { 669 blockThisCycle = true; 670 } 671 672 if (blockThisCycle) { 673 block(tid); 674 toDecode->renameUnblock[tid] = false; 675 } 676} 677 678template<class Impl> 679void 680DefaultRename<Impl>::skidInsert(unsigned tid) 681{ 682 DynInstPtr inst = NULL; 683 684 while (!insts[tid].empty()) { 685 inst = insts[tid].front(); 686 687 insts[tid].pop_front(); 688 689 assert(tid == inst->threadNumber); 690 691 DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename " 692 "skidBuffer\n", tid, inst->seqNum, inst->readPC()); 693 694 ++renameSkidInsts; 695 696 skidBuffer[tid].push_back(inst); 697 } 698 699 if (skidBuffer[tid].size() > skidBufferMax) 700 panic("Skidbuffer Exceeded Max Size"); 701} 702 703template <class Impl> 704void 705DefaultRename<Impl>::sortInsts() 706{ 707 int insts_from_decode = fromDecode->size; 708#ifdef DEBUG 709 for (int i=0; i < numThreads; i++) 710 assert(insts[i].empty()); 711#endif 712 for (int i = 0; i < insts_from_decode; ++i) { 713 DynInstPtr inst = fromDecode->insts[i]; 714 insts[inst->threadNumber].push_back(inst); 715 } 716} 717 718template<class Impl> 719bool 720DefaultRename<Impl>::skidsEmpty() 721{ 722 list<unsigned>::iterator threads = (*activeThreads).begin(); 723 724 while (threads != (*activeThreads).end()) { 725 if (!skidBuffer[*threads++].empty()) 726 return false; 727 } 728 729 return true; 730} 731 732template<class Impl> 733void 734DefaultRename<Impl>::updateStatus() 735{ 736 bool any_unblocking = false; 737 738 list<unsigned>::iterator threads = (*activeThreads).begin(); 739 740 threads = (*activeThreads).begin(); 741 742 while (threads != (*activeThreads).end()) { 743 unsigned tid = *threads++; 744 745 if (renameStatus[tid] == Unblocking) { 746 any_unblocking = true; 747 break; 748 } 749 } 750 751 // Rename will have activity if it's unblocking. 752 if (any_unblocking) { 753 if (_status == Inactive) { 754 _status = Active; 755 756 DPRINTF(Activity, "Activating stage.\n"); 757 758 cpu->activateStage(FullCPU::RenameIdx); 759 } 760 } else { 761 // If it's not unblocking, then rename will not have any internal 762 // activity. Switch it to inactive. 763 if (_status == Active) { 764 _status = Inactive; 765 DPRINTF(Activity, "Deactivating stage.\n"); 766 767 cpu->deactivateStage(FullCPU::RenameIdx); 768 } 769 } 770} 771 772template <class Impl> 773bool 774DefaultRename<Impl>::block(unsigned tid) 775{ 776 DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 777 778 // Add the current inputs onto the skid buffer, so they can be 779 // reprocessed when this stage unblocks. 780 skidInsert(tid); 781 782 // Only signal backwards to block if the previous stages do not think 783 // rename is already blocked. 784 if (renameStatus[tid] != Blocked) { 785 if (renameStatus[tid] != Unblocking) { 786 toDecode->renameBlock[tid] = true; 787 toDecode->renameUnblock[tid] = false; 788 wroteToTimeBuffer = true; 789 } 790 791 // Rename can not go from SerializeStall to Blocked, otherwise 792 // it would not know to complete the serialize stall. 793 if (renameStatus[tid] != SerializeStall) { 794 // Set status to Blocked. 795 renameStatus[tid] = Blocked; 796 return true; 797 } 798 } 799 800 return false; 801} 802 803template <class Impl> 804bool 805DefaultRename<Impl>::unblock(unsigned tid) 806{ 807 DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 808 809 // Rename is done unblocking if the skid buffer is empty. 810 if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 811 812 DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 813 814 toDecode->renameUnblock[tid] = true; 815 wroteToTimeBuffer = true; 816 817 renameStatus[tid] = Running; 818 return true; 819 } 820 821 return false; 822} 823 824template <class Impl> 825void 826DefaultRename<Impl>::doSquash(unsigned tid) 827{ 828 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin(); 829 830 InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum; 831 832 // After a syscall squashes everything, the history buffer may be empty 833 // but the ROB may still be squashing instructions. 834 if (historyBuffer[tid].empty()) { 835 return; 836 } 837 838 // Go through the most recent instructions, undoing the mappings 839 // they did and freeing up the registers. 840 while (!historyBuffer[tid].empty() && 841 (*hb_it).instSeqNum > squashed_seq_num) { 842 assert(hb_it != historyBuffer[tid].end()); 843 844 DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 845 "number %i.\n", tid, (*hb_it).instSeqNum); 846 847 // Tell the rename map to set the architected register to the 848 // previous physical register that it was renamed to. 849 renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 850 851 // Put the renamed physical register back on the free list. 852 freeList->addReg(hb_it->newPhysReg); 853 854 historyBuffer[tid].erase(hb_it++); 855 856 ++renameUndoneMaps; 857 } 858} 859 860template<class Impl> 861void 862DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid) 863{ 864 DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 865 "history buffer %u (size=%i), until [sn:%lli].\n", 866 tid, tid, historyBuffer[tid].size(), inst_seq_num); 867 868 typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end(); 869 870 --hb_it; 871 872 if (historyBuffer[tid].empty()) { 873 DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 874 return; 875 } else if (hb_it->instSeqNum > inst_seq_num) { 876 DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 877 "that a syscall happened recently.\n", tid); 878 return; 879 } 880 881 // Commit all the renames up until (and including) the committed sequence 882 // number. Some or even all of the committed instructions may not have 883 // rename histories if they did not have destination registers that were 884 // renamed. 885 while (!historyBuffer[tid].empty() && 886 hb_it != historyBuffer[tid].end() && 887 (*hb_it).instSeqNum <= inst_seq_num) { 888 889 DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 890 "[sn:%lli].\n", 891 tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum); 892 893 freeList->addReg((*hb_it).prevPhysReg); 894 ++renameCommittedMaps; 895 896 historyBuffer[tid].erase(hb_it--); 897 } 898} 899 900template <class Impl> 901inline void 902DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) 903{ 904 assert(renameMap[tid] != 0); 905 906 unsigned num_src_regs = inst->numSrcRegs(); 907 908 // Get the architectual register numbers from the source and 909 // destination operands, and redirect them to the right register. 910 // Will need to mark dependencies though. 911 for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 912 RegIndex src_reg = inst->srcRegIdx(src_idx); 913 914 // Look up the source registers to get the phys. register they've 915 // been renamed to, and set the sources to those registers. 916 PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg); 917 918 DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got " 919 "physical reg %i.\n", tid, (int)src_reg, 920 (int)renamed_reg); 921 922 inst->renameSrcReg(src_idx, renamed_reg); 923 924 // See if the register is ready or not. 925 if (scoreboard->getReg(renamed_reg) == true) { 926 DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid); 927 928 inst->markSrcRegReady(src_idx); 929 } 930 931 ++renameRenameLookups; 932 } 933} 934 935template <class Impl> 936inline void 937DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid) 938{ 939 typename RenameMap::RenameInfo rename_result; 940 941 unsigned num_dest_regs = inst->numDestRegs(); 942 943 // Rename the destination registers. 944 for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 945 RegIndex dest_reg = inst->destRegIdx(dest_idx); 946 947 // Get the physical register that the destination will be 948 // renamed to. 949 rename_result = renameMap[tid]->rename(dest_reg); 950 951 //Mark Scoreboard entry as not ready 952 scoreboard->unsetReg(rename_result.first); 953 954 DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 955 "reg %i.\n", tid, (int)dest_reg, 956 (int)rename_result.first); 957 958 // Record the rename information so that a history can be kept. 959 RenameHistory hb_entry(inst->seqNum, dest_reg, 960 rename_result.first, 961 rename_result.second); 962 963 historyBuffer[tid].push_front(hb_entry); 964 965 DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, " 966 "[sn:%lli].\n",tid, 967 (*historyBuffer[tid].begin()).instSeqNum); 968 969 // Tell the instruction to rename the appropriate destination 970 // register (dest_idx) to the new physical register 971 // (rename_result.first), and record the previous physical 972 // register that the same logical register was renamed to 973 // (rename_result.second). 974 inst->renameDestReg(dest_idx, 975 rename_result.first, 976 rename_result.second); 977 978 ++renameRenamedOperands; 979 } 980} 981 982template <class Impl> 983inline int 984DefaultRename<Impl>::calcFreeROBEntries(unsigned tid) 985{ 986 int num_free = freeEntries[tid].robEntries - 987 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 988 989 //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 990 991 return num_free; 992} 993 994template <class Impl> 995inline int 996DefaultRename<Impl>::calcFreeIQEntries(unsigned tid) 997{ 998 int num_free = freeEntries[tid].iqEntries - 999 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 1000 1001 //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 1002 1003 return num_free; 1004} 1005 1006template <class Impl> 1007inline int 1008DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid) 1009{ 1010 int num_free = freeEntries[tid].lsqEntries - 1011 (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 1012 1013 //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 1014 1015 return num_free; 1016} 1017 1018template <class Impl> 1019unsigned 1020DefaultRename<Impl>::validInsts() 1021{ 1022 unsigned inst_count = 0; 1023 1024 for (int i=0; i<fromDecode->size; i++) { 1025 if (!fromDecode->insts[i]->squashed) 1026 inst_count++; 1027 } 1028 1029 return inst_count; 1030} 1031 1032template <class Impl> 1033void 1034DefaultRename<Impl>::readStallSignals(unsigned tid) 1035{ 1036 if (fromIEW->iewBlock[tid]) { 1037 stalls[tid].iew = true; 1038 } 1039 1040 if (fromIEW->iewUnblock[tid]) { 1041 assert(stalls[tid].iew); 1042 stalls[tid].iew = false; 1043 } 1044 1045 if (fromCommit->commitBlock[tid]) { 1046 stalls[tid].commit = true; 1047 } 1048 1049 if (fromCommit->commitUnblock[tid]) { 1050 assert(stalls[tid].commit); 1051 stalls[tid].commit = false; 1052 } 1053} 1054 1055template <class Impl> 1056bool 1057DefaultRename<Impl>::checkStall(unsigned tid) 1058{ 1059 bool ret_val = false; 1060 1061 if (stalls[tid].iew) { 1062 DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 1063 ret_val = true; 1064 } else if (stalls[tid].commit) { 1065 DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 1066 ret_val = true; 1067 } else if (calcFreeROBEntries(tid) <= 0) { 1068 DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 1069 ret_val = true; 1070 } else if (calcFreeIQEntries(tid) <= 0) { 1071 DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 1072 ret_val = true; 1073 } else if (calcFreeLSQEntries(tid) <= 0) { 1074 DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 1075 ret_val = true; 1076 } else if (renameMap[tid]->numFreeEntries() <= 0) { 1077 DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 1078 ret_val = true; 1079 } else if (renameStatus[tid] == SerializeStall && 1080 (!emptyROB[tid] || instsInProgress[tid])) { 1081 DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 1082 "empty.\n", 1083 tid); 1084 ret_val = true; 1085 } 1086 1087 return ret_val; 1088} 1089 1090template <class Impl> 1091void 1092DefaultRename<Impl>::readFreeEntries(unsigned tid) 1093{ 1094 bool updated = false; 1095 if (fromIEW->iewInfo[tid].usedIQ) { 1096 freeEntries[tid].iqEntries = 1097 fromIEW->iewInfo[tid].freeIQEntries; 1098 updated = true; 1099 } 1100 1101 if (fromIEW->iewInfo[tid].usedLSQ) { 1102 freeEntries[tid].lsqEntries = 1103 fromIEW->iewInfo[tid].freeLSQEntries; 1104 updated = true; 1105 } 1106 1107 if (fromCommit->commitInfo[tid].usedROB) { 1108 freeEntries[tid].robEntries = 1109 fromCommit->commitInfo[tid].freeROBEntries; 1110 emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 1111 updated = true; 1112 } 1113 1114 DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 1115 tid, 1116 freeEntries[tid].iqEntries, 1117 freeEntries[tid].robEntries, 1118 freeEntries[tid].lsqEntries); 1119 1120 DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 1121 tid, instsInProgress[tid]); 1122} 1123 1124template <class Impl> 1125bool 1126DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid) 1127{ 1128 // Check if there's a squash signal, squash if there is 1129 // Check stall signals, block if necessary. 1130 // If status was blocked 1131 // check if stall conditions have passed 1132 // if so then go to unblocking 1133 // If status was Squashing 1134 // check if squashing is not high. Switch to running this cycle. 1135 // If status was serialize stall 1136 // check if ROB is empty and no insts are in flight to the ROB 1137 1138 readFreeEntries(tid); 1139 readStallSignals(tid); 1140 1141 if (fromCommit->commitInfo[tid].squash) { 1142 DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 1143 "commit.\n", tid); 1144 1145 squash(tid); 1146 1147 return true; 1148 } 1149 1150 if (fromCommit->commitInfo[tid].robSquashing) { 1151 DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 1152 1153 renameStatus[tid] = Squashing; 1154 1155 return true; 1156 } 1157 1158 if (checkStall(tid)) { 1159 return block(tid); 1160 } 1161 1162 if (renameStatus[tid] == Blocked) { 1163 DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 1164 tid); 1165 1166 renameStatus[tid] = Unblocking; 1167 1168 unblock(tid); 1169 1170 return true; 1171 } 1172 1173 if (renameStatus[tid] == Squashing) { 1174 // Switch status to running if rename isn't being told to block or 1175 // squash this cycle. 1176 DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 1177 tid); 1178 1179 renameStatus[tid] = Running; 1180 1181 return false; 1182 } 1183 1184 if (renameStatus[tid] == SerializeStall) { 1185 // Stall ends once the ROB is free. 1186 DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 1187 "unblocking.\n", tid); 1188 1189 DynInstPtr serial_inst = serializeInst[tid]; 1190 1191 renameStatus[tid] = Unblocking; 1192 1193 unblock(tid); 1194 1195 DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 1196 "PC %#x.\n", 1197 tid, serial_inst->seqNum, serial_inst->readPC()); 1198 1199 // Put instruction into queue here. 1200 serial_inst->clearSerializeBefore(); 1201 1202 if (!skidBuffer[tid].empty()) { 1203 skidBuffer[tid].push_front(serial_inst); 1204 } else { 1205 insts[tid].push_front(serial_inst); 1206 } 1207 1208 DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 1209 " Adding to front of list.", tid); 1210 1211 serializeInst[tid] = NULL; 1212 1213 return true; 1214 } 1215 1216 // If we've reached this point, we have not gotten any signals that 1217 // cause rename to change its status. Rename remains the same as before. 1218 return false; 1219} 1220 1221template<class Impl> 1222void 1223DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, 1224 unsigned tid) 1225{ 1226 if (inst_list.empty()) { 1227 // Mark a bit to say that I must serialize on the next instruction. 1228 serializeOnNextInst[tid] = true; 1229 return; 1230 } 1231 1232 // Set the next instruction as serializing. 1233 inst_list.front()->setSerializeBefore(); 1234} 1235 1236template <class Impl> 1237inline void 1238DefaultRename<Impl>::incrFullStat(const FullSource &source) 1239{ 1240 switch (source) { 1241 case ROB: 1242 ++renameROBFullEvents; 1243 break; 1244 case IQ: 1245 ++renameIQFullEvents; 1246 break; 1247 case LSQ: 1248 ++renameLSQFullEvents; 1249 break; 1250 default: 1251 panic("Rename full stall stat should be incremented for a reason!"); 1252 break; 1253 } 1254} 1255 1256template <class Impl> 1257void 1258DefaultRename<Impl>::dumpHistory() 1259{ 1260 typename list<RenameHistory>::iterator buf_it; 1261 1262 for (int i = 0; i < numThreads; i++) { 1263 1264 buf_it = historyBuffer[i].begin(); 1265 1266 while (buf_it != historyBuffer[i].end()) { 1267 cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 1268 "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 1269 (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 1270 1271 buf_it++; 1272 } 1273 } 1274} 1275