rename_impl.hh revision 2348 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <list>
30
31#include "config/full_system.hh"
32#include "cpu/o3/rename.hh"
33
34using namespace std;
35
36template <class Impl>
37DefaultRename<Impl>::DefaultRename(Params *params)
38    : iewToRenameDelay(params->iewToRenameDelay),
39      decodeToRenameDelay(params->decodeToRenameDelay),
40      commitToRenameDelay(params->commitToRenameDelay),
41      renameWidth(params->renameWidth),
42      commitWidth(params->commitWidth),
43      numThreads(params->numberOfThreads)
44{
45    _status = Inactive;
46
47    for (int i=0; i< numThreads; i++) {
48        renameStatus[i] = Idle;
49
50        freeEntries[i].iqEntries = 0;
51        freeEntries[i].lsqEntries = 0;
52        freeEntries[i].robEntries = 0;
53
54        stalls[i].iew = false;
55        stalls[i].commit = false;
56        serializeInst[i] = NULL;
57
58        instsInProgress[i] = 0;
59
60        emptyROB[i] = true;
61
62        serializeOnNextInst[i] = false;
63    }
64
65    // @todo: Make into a parameter.
66    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
67}
68
69template <class Impl>
70std::string
71DefaultRename<Impl>::name() const
72{
73    return cpu->name() + ".rename";
74}
75
76template <class Impl>
77void
78DefaultRename<Impl>::regStats()
79{
80    renameSquashCycles
81        .name(name() + ".RENAME:SquashCycles")
82        .desc("Number of cycles rename is squashing")
83        .prereq(renameSquashCycles);
84    renameIdleCycles
85        .name(name() + ".RENAME:IdleCycles")
86        .desc("Number of cycles rename is idle")
87        .prereq(renameIdleCycles);
88    renameBlockCycles
89        .name(name() + ".RENAME:BlockCycles")
90        .desc("Number of cycles rename is blocking")
91        .prereq(renameBlockCycles);
92    renameSerializeStallCycles
93        .name(name() + ".RENAME:serializeStallCycles")
94        .desc("count of cycles rename stalled for serializing inst")
95        .flags(Stats::total);
96    renameRunCycles
97        .name(name() + ".RENAME:RunCycles")
98        .desc("Number of cycles rename is running")
99        .prereq(renameIdleCycles);
100    renameUnblockCycles
101        .name(name() + ".RENAME:UnblockCycles")
102        .desc("Number of cycles rename is unblocking")
103        .prereq(renameUnblockCycles);
104    renameRenamedInsts
105        .name(name() + ".RENAME:RenamedInsts")
106        .desc("Number of instructions processed by rename")
107        .prereq(renameRenamedInsts);
108    renameSquashedInsts
109        .name(name() + ".RENAME:SquashedInsts")
110        .desc("Number of squashed instructions processed by rename")
111        .prereq(renameSquashedInsts);
112    renameROBFullEvents
113        .name(name() + ".RENAME:ROBFullEvents")
114        .desc("Number of times rename has blocked due to ROB full")
115        .prereq(renameROBFullEvents);
116    renameIQFullEvents
117        .name(name() + ".RENAME:IQFullEvents")
118        .desc("Number of times rename has blocked due to IQ full")
119        .prereq(renameIQFullEvents);
120    renameLSQFullEvents
121        .name(name() + ".RENAME:LSQFullEvents")
122        .desc("Number of times rename has blocked due to LSQ full")
123        .prereq(renameLSQFullEvents);
124    renameFullRegistersEvents
125        .name(name() + ".RENAME:FullRegisterEvents")
126        .desc("Number of times there has been no free registers")
127        .prereq(renameFullRegistersEvents);
128    renameRenamedOperands
129        .name(name() + ".RENAME:RenamedOperands")
130        .desc("Number of destination operands rename has renamed")
131        .prereq(renameRenamedOperands);
132    renameRenameLookups
133        .name(name() + ".RENAME:RenameLookups")
134        .desc("Number of register rename lookups that rename has made")
135        .prereq(renameRenameLookups);
136    renameCommittedMaps
137        .name(name() + ".RENAME:CommittedMaps")
138        .desc("Number of HB maps that are committed")
139        .prereq(renameCommittedMaps);
140    renameUndoneMaps
141        .name(name() + ".RENAME:UndoneMaps")
142        .desc("Number of HB maps that are undone due to squashing")
143        .prereq(renameUndoneMaps);
144    renamedSerializing
145        .name(name() + ".RENAME:serializingInsts")
146        .desc("count of serializing insts renamed")
147        .flags(Stats::total)
148        ;
149    renamedTempSerializing
150        .name(name() + ".RENAME:tempSerializingInsts")
151        .desc("count of temporary serializing insts renamed")
152        .flags(Stats::total)
153        ;
154    renameSkidInsts
155        .name(name() + ".RENAME:skidInsts")
156        .desc("count of insts added to the skid buffer")
157        .flags(Stats::total)
158        ;
159}
160
161template <class Impl>
162void
163DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr)
164{
165    DPRINTF(Rename, "Setting CPU pointer.\n");
166    cpu = cpu_ptr;
167}
168
169template <class Impl>
170void
171DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
172{
173    DPRINTF(Rename, "Setting time buffer pointer.\n");
174    timeBuffer = tb_ptr;
175
176    // Setup wire to read information from time buffer, from IEW stage.
177    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
178
179    // Setup wire to read infromation from time buffer, from commit stage.
180    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
181
182    // Setup wire to write information to previous stages.
183    toDecode = timeBuffer->getWire(0);
184}
185
186template <class Impl>
187void
188DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
189{
190    DPRINTF(Rename, "Setting rename queue pointer.\n");
191    renameQueue = rq_ptr;
192
193    // Setup wire to write information to future stages.
194    toIEW = renameQueue->getWire(0);
195}
196
197template <class Impl>
198void
199DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
200{
201    DPRINTF(Rename, "Setting decode queue pointer.\n");
202    decodeQueue = dq_ptr;
203
204    // Setup wire to get information from decode.
205    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
210DefaultRename<Impl>::initStage()
211{
212    // Grab the number of free entries directly from the stages.
213    for (int tid=0; tid < numThreads; tid++) {
214        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
215        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
216        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
217        emptyROB[tid] = true;
218    }
219}
220
221template<class Impl>
222void
223DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
224{
225    DPRINTF(Rename, "Setting active threads list pointer.\n");
226    activeThreads = at_ptr;
227}
228
229
230template <class Impl>
231void
232DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
233{
234    DPRINTF(Rename, "Setting rename map pointers.\n");
235
236    for (int i=0; i<numThreads; i++) {
237        renameMap[i] = &rm_ptr[i];
238    }
239}
240
241template <class Impl>
242void
243DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
244{
245    DPRINTF(Rename, "Setting free list pointer.\n");
246    freeList = fl_ptr;
247}
248
249template<class Impl>
250void
251DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
252{
253    DPRINTF(Rename, "Setting scoreboard pointer.\n");
254    scoreboard = _scoreboard;
255}
256
257template <class Impl>
258void
259DefaultRename<Impl>::switchOut()
260{
261    // Rename is ready to switch out at any time.
262    cpu->signalSwitched();
263}
264
265template <class Impl>
266void
267DefaultRename<Impl>::doSwitchOut()
268{
269    // Clear any state, fix up the rename map.
270    for (int i = 0; i < numThreads; i++) {
271        typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
272
273        while (!historyBuffer[i].empty()) {
274            assert(hb_it != historyBuffer[i].end());
275
276            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
277                    "number %i.\n", i, (*hb_it).instSeqNum);
278
279            // Tell the rename map to set the architected register to the
280            // previous physical register that it was renamed to.
281            renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
282
283            // Put the renamed physical register back on the free list.
284            freeList->addReg(hb_it->newPhysReg);
285
286            historyBuffer[i].erase(hb_it++);
287        }
288        insts[i].clear();
289        skidBuffer[i].clear();
290    }
291}
292
293template <class Impl>
294void
295DefaultRename<Impl>::takeOverFrom()
296{
297    _status = Inactive;
298    initStage();
299
300    // Reset all state prior to taking over from the other CPU.
301    for (int i=0; i< numThreads; i++) {
302        renameStatus[i] = Idle;
303
304        stalls[i].iew = false;
305        stalls[i].commit = false;
306        serializeInst[i] = NULL;
307
308        instsInProgress[i] = 0;
309
310        emptyROB[i] = true;
311
312        serializeOnNextInst[i] = false;
313    }
314}
315
316template <class Impl>
317void
318DefaultRename<Impl>::squash(unsigned tid)
319{
320    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
321
322    // Clear the stall signal if rename was blocked or unblocking before.
323    // If it still needs to block, the blocking should happen the next
324    // cycle and there should be space to hold everything due to the squash.
325    if (renameStatus[tid] == Blocked ||
326        renameStatus[tid] == Unblocking ||
327        renameStatus[tid] == SerializeStall) {
328#if 0
329        // In syscall emulation, we can have both a block and a squash due
330        // to a syscall in the same cycle.  This would cause both signals to
331        // be high.  This shouldn't happen in full system.
332        if (toDecode->renameBlock[tid]) {
333            toDecode->renameBlock[tid] = 0;
334        } else {
335            toDecode->renameUnblock[tid] = 1;
336        }
337#else
338        toDecode->renameUnblock[tid] = 1;
339#endif
340        serializeInst[tid] = NULL;
341    }
342
343    // Set the status to Squashing.
344    renameStatus[tid] = Squashing;
345
346    // Squash any instructions from decode.
347    unsigned squashCount = 0;
348
349    for (int i=0; i<fromDecode->size; i++) {
350        if (fromDecode->insts[i]->threadNumber == tid) {
351            fromDecode->insts[i]->squashed = true;
352            wroteToTimeBuffer = true;
353            squashCount++;
354        }
355    }
356
357    insts[tid].clear();
358
359    // Clear the skid buffer in case it has any data in it.
360    skidBuffer[tid].clear();
361
362    doSquash(tid);
363}
364
365template <class Impl>
366void
367DefaultRename<Impl>::tick()
368{
369    wroteToTimeBuffer = false;
370
371    blockThisCycle = false;
372
373    bool status_change = false;
374
375    toIEWIndex = 0;
376
377    sortInsts();
378
379    list<unsigned>::iterator threads = (*activeThreads).begin();
380
381    // Check stall and squash signals.
382    while (threads != (*activeThreads).end()) {
383        unsigned tid = *threads++;
384
385        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
386
387        status_change = checkSignalsAndUpdate(tid) || status_change;
388
389        rename(status_change, tid);
390    }
391
392    if (status_change) {
393        updateStatus();
394    }
395
396    if (wroteToTimeBuffer) {
397        DPRINTF(Activity, "Activity this cycle.\n");
398        cpu->activityThisCycle();
399    }
400
401    threads = (*activeThreads).begin();
402
403    while (threads != (*activeThreads).end()) {
404        unsigned tid = *threads++;
405
406        // If we committed this cycle then doneSeqNum will be > 0
407        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
408            !fromCommit->commitInfo[tid].squash &&
409            renameStatus[tid] != Squashing) {
410
411            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
412                                  tid);
413        }
414    }
415
416    // @todo: make into updateProgress function
417    for (int tid=0; tid < numThreads; tid++) {
418        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
419
420        assert(instsInProgress[tid] >=0);
421    }
422
423}
424
425template<class Impl>
426void
427DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
428{
429    // If status is Running or idle,
430    //     call renameInsts()
431    // If status is Unblocking,
432    //     buffer any instructions coming from decode
433    //     continue trying to empty skid buffer
434    //     check if stall conditions have passed
435
436    if (renameStatus[tid] == Blocked) {
437        ++renameBlockCycles;
438    } else if (renameStatus[tid] == Squashing) {
439        ++renameSquashCycles;
440    } else if (renameStatus[tid] == SerializeStall) {
441        ++renameSerializeStallCycles;
442    }
443
444    if (renameStatus[tid] == Running ||
445        renameStatus[tid] == Idle) {
446        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
447                "stage.\n", tid);
448
449        renameInsts(tid);
450    } else if (renameStatus[tid] == Unblocking) {
451        renameInsts(tid);
452
453        if (validInsts()) {
454            // Add the current inputs to the skid buffer so they can be
455            // reprocessed when this stage unblocks.
456            skidInsert(tid);
457        }
458
459        // If we switched over to blocking, then there's a potential for
460        // an overall status change.
461        status_change = unblock(tid) || status_change || blockThisCycle;
462    }
463}
464
465template <class Impl>
466void
467DefaultRename<Impl>::renameInsts(unsigned tid)
468{
469    // Instructions can be either in the skid buffer or the queue of
470    // instructions coming from decode, depending on the status.
471    int insts_available = renameStatus[tid] == Unblocking ?
472        skidBuffer[tid].size() : insts[tid].size();
473
474    // Check the decode queue to see if instructions are available.
475    // If there are no available instructions to rename, then do nothing.
476    if (insts_available == 0) {
477        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
478                tid);
479        // Should I change status to idle?
480        ++renameIdleCycles;
481        return;
482    } else if (renameStatus[tid] == Unblocking) {
483        ++renameUnblockCycles;
484    } else if (renameStatus[tid] == Running) {
485        ++renameRunCycles;
486    }
487
488    DynInstPtr inst;
489
490    // Will have to do a different calculation for the number of free
491    // entries.
492    int free_rob_entries = calcFreeROBEntries(tid);
493    int free_iq_entries  = calcFreeIQEntries(tid);
494    int free_lsq_entries = calcFreeLSQEntries(tid);
495    int min_free_entries = free_rob_entries;
496
497    FullSource source = ROB;
498
499    if (free_iq_entries < min_free_entries) {
500        min_free_entries = free_iq_entries;
501        source = IQ;
502    }
503
504    if (free_lsq_entries < min_free_entries) {
505        min_free_entries = free_lsq_entries;
506        source = LSQ;
507    }
508
509    // Check if there's any space left.
510    if (min_free_entries <= 0) {
511        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
512                "entries.\n"
513                "ROB has %i free entries.\n"
514                "IQ has %i free entries.\n"
515                "LSQ has %i free entries.\n",
516                tid,
517                free_rob_entries,
518                free_iq_entries,
519                free_lsq_entries);
520
521        blockThisCycle = true;
522
523        block(tid);
524
525        incrFullStat(source);
526
527        return;
528    } else if (min_free_entries < insts_available) {
529        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
530                "%i insts available, but only %i insts can be "
531                "renamed due to ROB/IQ/LSQ limits.\n",
532                tid, insts_available, min_free_entries);
533
534        insts_available = min_free_entries;
535
536        blockThisCycle = true;
537
538        incrFullStat(source);
539    }
540
541    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
542        skidBuffer[tid] : insts[tid];
543
544    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
545            "send iew.\n", tid, insts_available);
546
547    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
548            "dispatched to IQ last cycle.\n",
549            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
550
551    // Handle serializing the next instruction if necessary.
552    if (serializeOnNextInst[tid]) {
553        if (emptyROB[tid] && instsInProgress[tid] == 0) {
554            // ROB already empty; no need to serialize.
555            serializeOnNextInst[tid] = false;
556        } else if (!insts_to_rename.empty()) {
557            insts_to_rename.front()->setSerializeBefore();
558        }
559    }
560
561    int renamed_insts = 0;
562
563    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
564        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
565
566        assert(!insts_to_rename.empty());
567
568        inst = insts_to_rename.front();
569
570        insts_to_rename.pop_front();
571
572        if (renameStatus[tid] == Unblocking) {
573            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
574                    "skidBuffer\n",
575                    tid, inst->seqNum, inst->readPC());
576        }
577
578        if (inst->isSquashed()) {
579            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
580                    "squashed, skipping.\n",
581                    tid, inst->seqNum, inst->threadNumber,inst->readPC());
582
583            ++renameSquashedInsts;
584
585            // Decrement how many instructions are available.
586            --insts_available;
587
588            continue;
589        }
590
591        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
592                "PC %#x.\n",
593                tid, inst->seqNum, inst->readPC());
594
595        // Handle serializeAfter/serializeBefore instructions.
596        // serializeAfter marks the next instruction as serializeBefore.
597        // serializeBefore makes the instruction wait in rename until the ROB
598        // is empty.
599
600        // In this model, IPR accesses are serialize before
601        // instructions, and store conditionals are serialize after
602        // instructions.  This is mainly due to lack of support for
603        // out-of-order operations of either of those classes of
604        // instructions.
605        if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
606            !inst->isSerializeHandled()) {
607            DPRINTF(Rename, "Serialize before instruction encountered.\n");
608
609            if (!inst->isTempSerializeBefore()) {
610                renamedSerializing++;
611                inst->setSerializeHandled();
612            } else {
613                renamedTempSerializing++;
614            }
615
616            // Change status over to SerializeStall so that other stages know
617            // what this is blocked on.
618            renameStatus[tid] = SerializeStall;
619
620            serializeInst[tid] = inst;
621
622            blockThisCycle = true;
623
624            break;
625        } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) &&
626                   !inst->isSerializeHandled()) {
627            DPRINTF(Rename, "Serialize after instruction encountered.\n");
628
629            renamedSerializing++;
630
631            inst->setSerializeHandled();
632
633            serializeAfter(insts_to_rename, tid);
634        }
635
636        // Check here to make sure there are enough destination registers
637        // to rename to.  Otherwise block.
638        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
639            DPRINTF(Rename, "Blocking due to lack of free "
640                    "physical registers to rename to.\n");
641            blockThisCycle = true;
642
643            ++renameFullRegistersEvents;
644
645            break;
646        }
647
648        renameSrcRegs(inst, inst->threadNumber);
649
650        renameDestRegs(inst, inst->threadNumber);
651
652        ++renamed_insts;
653
654        // Put instruction in rename queue.
655        toIEW->insts[toIEWIndex] = inst;
656        ++(toIEW->size);
657
658        // Increment which instruction we're on.
659        ++toIEWIndex;
660
661        // Decrement how many instructions are available.
662        --insts_available;
663    }
664
665    instsInProgress[tid] += renamed_insts;
666    renameRenamedInsts += renamed_insts;
667
668    // If we wrote to the time buffer, record this.
669    if (toIEWIndex) {
670        wroteToTimeBuffer = true;
671    }
672
673    // Check if there's any instructions left that haven't yet been renamed.
674    // If so then block.
675    if (insts_available) {
676        blockThisCycle = true;
677    }
678
679    if (blockThisCycle) {
680        block(tid);
681        toDecode->renameUnblock[tid] = false;
682    }
683}
684
685template<class Impl>
686void
687DefaultRename<Impl>::skidInsert(unsigned tid)
688{
689    DynInstPtr inst = NULL;
690
691    while (!insts[tid].empty()) {
692        inst = insts[tid].front();
693
694        insts[tid].pop_front();
695
696        assert(tid == inst->threadNumber);
697
698        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
699                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
700
701        ++renameSkidInsts;
702
703        skidBuffer[tid].push_back(inst);
704    }
705
706    if (skidBuffer[tid].size() > skidBufferMax)
707        panic("Skidbuffer Exceeded Max Size");
708}
709
710template <class Impl>
711void
712DefaultRename<Impl>::sortInsts()
713{
714    int insts_from_decode = fromDecode->size;
715#ifdef DEBUG
716    for (int i=0; i < numThreads; i++)
717        assert(insts[i].empty());
718#endif
719    for (int i = 0; i < insts_from_decode; ++i) {
720        DynInstPtr inst = fromDecode->insts[i];
721        insts[inst->threadNumber].push_back(inst);
722    }
723}
724
725template<class Impl>
726bool
727DefaultRename<Impl>::skidsEmpty()
728{
729    list<unsigned>::iterator threads = (*activeThreads).begin();
730
731    while (threads != (*activeThreads).end()) {
732        if (!skidBuffer[*threads++].empty())
733            return false;
734    }
735
736    return true;
737}
738
739template<class Impl>
740void
741DefaultRename<Impl>::updateStatus()
742{
743    bool any_unblocking = false;
744
745    list<unsigned>::iterator threads = (*activeThreads).begin();
746
747    threads = (*activeThreads).begin();
748
749    while (threads != (*activeThreads).end()) {
750        unsigned tid = *threads++;
751
752        if (renameStatus[tid] == Unblocking) {
753            any_unblocking = true;
754            break;
755        }
756    }
757
758    // Rename will have activity if it's unblocking.
759    if (any_unblocking) {
760        if (_status == Inactive) {
761            _status = Active;
762
763            DPRINTF(Activity, "Activating stage.\n");
764
765            cpu->activateStage(FullCPU::RenameIdx);
766        }
767    } else {
768        // If it's not unblocking, then rename will not have any internal
769        // activity.  Switch it to inactive.
770        if (_status == Active) {
771            _status = Inactive;
772            DPRINTF(Activity, "Deactivating stage.\n");
773
774            cpu->deactivateStage(FullCPU::RenameIdx);
775        }
776    }
777}
778
779template <class Impl>
780bool
781DefaultRename<Impl>::block(unsigned tid)
782{
783    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
784
785    // Add the current inputs onto the skid buffer, so they can be
786    // reprocessed when this stage unblocks.
787    skidInsert(tid);
788
789    // Only signal backwards to block if the previous stages do not think
790    // rename is already blocked.
791    if (renameStatus[tid] != Blocked) {
792        if (renameStatus[tid] != Unblocking) {
793            toDecode->renameBlock[tid] = true;
794            toDecode->renameUnblock[tid] = false;
795            wroteToTimeBuffer = true;
796        }
797
798        // Rename can not go from SerializeStall to Blocked, otherwise
799        // it would not know to complete the serialize stall.
800        if (renameStatus[tid] != SerializeStall) {
801            // Set status to Blocked.
802            renameStatus[tid] = Blocked;
803            return true;
804        }
805    }
806
807    return false;
808}
809
810template <class Impl>
811bool
812DefaultRename<Impl>::unblock(unsigned tid)
813{
814    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
815
816    // Rename is done unblocking if the skid buffer is empty.
817    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
818
819        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
820
821        toDecode->renameUnblock[tid] = true;
822        wroteToTimeBuffer = true;
823
824        renameStatus[tid] = Running;
825        return true;
826    }
827
828    return false;
829}
830
831template <class Impl>
832void
833DefaultRename<Impl>::doSquash(unsigned tid)
834{
835    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
836
837    InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
838
839    // After a syscall squashes everything, the history buffer may be empty
840    // but the ROB may still be squashing instructions.
841    if (historyBuffer[tid].empty()) {
842        return;
843    }
844
845    // Go through the most recent instructions, undoing the mappings
846    // they did and freeing up the registers.
847    while (!historyBuffer[tid].empty() &&
848           (*hb_it).instSeqNum > squashed_seq_num) {
849        assert(hb_it != historyBuffer[tid].end());
850
851        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
852                "number %i.\n", tid, (*hb_it).instSeqNum);
853
854        // Tell the rename map to set the architected register to the
855        // previous physical register that it was renamed to.
856        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
857
858        // Put the renamed physical register back on the free list.
859        freeList->addReg(hb_it->newPhysReg);
860
861        historyBuffer[tid].erase(hb_it++);
862
863        ++renameUndoneMaps;
864    }
865}
866
867template<class Impl>
868void
869DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
870{
871    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
872            "history buffer %u (size=%i), until [sn:%lli].\n",
873            tid, tid, historyBuffer[tid].size(), inst_seq_num);
874
875    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
876
877    --hb_it;
878
879    if (historyBuffer[tid].empty()) {
880        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
881        return;
882    } else if (hb_it->instSeqNum > inst_seq_num) {
883        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
884                "that a syscall happened recently.\n", tid);
885        return;
886    }
887
888    // Commit all the renames up until (and including) the committed sequence
889    // number. Some or even all of the committed instructions may not have
890    // rename histories if they did not have destination registers that were
891    // renamed.
892    while (!historyBuffer[tid].empty() &&
893           hb_it != historyBuffer[tid].end() &&
894           (*hb_it).instSeqNum <= inst_seq_num) {
895
896        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, "
897                "[sn:%lli].\n",
898                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
899
900        freeList->addReg((*hb_it).prevPhysReg);
901        ++renameCommittedMaps;
902
903        historyBuffer[tid].erase(hb_it--);
904    }
905}
906
907template <class Impl>
908inline void
909DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
910{
911    assert(renameMap[tid] != 0);
912
913    unsigned num_src_regs = inst->numSrcRegs();
914
915    // Get the architectual register numbers from the source and
916    // destination operands, and redirect them to the right register.
917    // Will need to mark dependencies though.
918    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
919        RegIndex src_reg = inst->srcRegIdx(src_idx);
920
921        // Look up the source registers to get the phys. register they've
922        // been renamed to, and set the sources to those registers.
923        PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
924
925        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
926                "physical reg %i.\n", tid, (int)src_reg,
927                (int)renamed_reg);
928
929        inst->renameSrcReg(src_idx, renamed_reg);
930
931        // See if the register is ready or not.
932        if (scoreboard->getReg(renamed_reg) == true) {
933            DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
934
935            inst->markSrcRegReady(src_idx);
936        }
937
938        ++renameRenameLookups;
939    }
940}
941
942template <class Impl>
943inline void
944DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
945{
946    typename RenameMap::RenameInfo rename_result;
947
948    unsigned num_dest_regs = inst->numDestRegs();
949
950    // Rename the destination registers.
951    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
952        RegIndex dest_reg = inst->destRegIdx(dest_idx);
953
954        // Get the physical register that the destination will be
955        // renamed to.
956        rename_result = renameMap[tid]->rename(dest_reg);
957
958        //Mark Scoreboard entry as not ready
959        scoreboard->unsetReg(rename_result.first);
960
961        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
962                "reg %i.\n", tid, (int)dest_reg,
963                (int)rename_result.first);
964
965        // Record the rename information so that a history can be kept.
966        RenameHistory hb_entry(inst->seqNum, dest_reg,
967                               rename_result.first,
968                               rename_result.second);
969
970        historyBuffer[tid].push_front(hb_entry);
971
972        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
973                "[sn:%lli].\n",tid,
974                (*historyBuffer[tid].begin()).instSeqNum);
975
976        // Tell the instruction to rename the appropriate destination
977        // register (dest_idx) to the new physical register
978        // (rename_result.first), and record the previous physical
979        // register that the same logical register was renamed to
980        // (rename_result.second).
981        inst->renameDestReg(dest_idx,
982                            rename_result.first,
983                            rename_result.second);
984
985        ++renameRenamedOperands;
986    }
987}
988
989template <class Impl>
990inline int
991DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
992{
993    int num_free = freeEntries[tid].robEntries -
994                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
995
996    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
997
998    return num_free;
999}
1000
1001template <class Impl>
1002inline int
1003DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1004{
1005    int num_free = freeEntries[tid].iqEntries -
1006                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1007
1008    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1009
1010    return num_free;
1011}
1012
1013template <class Impl>
1014inline int
1015DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1016{
1017    int num_free = freeEntries[tid].lsqEntries -
1018                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1019
1020    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1021
1022    return num_free;
1023}
1024
1025template <class Impl>
1026unsigned
1027DefaultRename<Impl>::validInsts()
1028{
1029    unsigned inst_count = 0;
1030
1031    for (int i=0; i<fromDecode->size; i++) {
1032        if (!fromDecode->insts[i]->squashed)
1033            inst_count++;
1034    }
1035
1036    return inst_count;
1037}
1038
1039template <class Impl>
1040void
1041DefaultRename<Impl>::readStallSignals(unsigned tid)
1042{
1043    if (fromIEW->iewBlock[tid]) {
1044        stalls[tid].iew = true;
1045    }
1046
1047    if (fromIEW->iewUnblock[tid]) {
1048        assert(stalls[tid].iew);
1049        stalls[tid].iew = false;
1050    }
1051
1052    if (fromCommit->commitBlock[tid]) {
1053        stalls[tid].commit = true;
1054    }
1055
1056    if (fromCommit->commitUnblock[tid]) {
1057        assert(stalls[tid].commit);
1058        stalls[tid].commit = false;
1059    }
1060}
1061
1062template <class Impl>
1063bool
1064DefaultRename<Impl>::checkStall(unsigned tid)
1065{
1066    bool ret_val = false;
1067
1068    if (stalls[tid].iew) {
1069        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1070        ret_val = true;
1071    } else if (stalls[tid].commit) {
1072        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1073        ret_val = true;
1074    } else if (calcFreeROBEntries(tid) <= 0) {
1075        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1076        ret_val = true;
1077    } else if (calcFreeIQEntries(tid) <= 0) {
1078        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1079        ret_val = true;
1080    } else if (calcFreeLSQEntries(tid) <= 0) {
1081        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1082        ret_val = true;
1083    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1084        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1085        ret_val = true;
1086    } else if (renameStatus[tid] == SerializeStall &&
1087               (!emptyROB[tid] || instsInProgress[tid])) {
1088        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1089                "empty.\n",
1090                tid);
1091        ret_val = true;
1092    }
1093
1094    return ret_val;
1095}
1096
1097template <class Impl>
1098void
1099DefaultRename<Impl>::readFreeEntries(unsigned tid)
1100{
1101    bool updated = false;
1102    if (fromIEW->iewInfo[tid].usedIQ) {
1103        freeEntries[tid].iqEntries =
1104            fromIEW->iewInfo[tid].freeIQEntries;
1105        updated = true;
1106    }
1107
1108    if (fromIEW->iewInfo[tid].usedLSQ) {
1109        freeEntries[tid].lsqEntries =
1110            fromIEW->iewInfo[tid].freeLSQEntries;
1111        updated = true;
1112    }
1113
1114    if (fromCommit->commitInfo[tid].usedROB) {
1115        freeEntries[tid].robEntries =
1116            fromCommit->commitInfo[tid].freeROBEntries;
1117        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1118        updated = true;
1119    }
1120
1121    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1122            tid,
1123            freeEntries[tid].iqEntries,
1124            freeEntries[tid].robEntries,
1125            freeEntries[tid].lsqEntries);
1126
1127    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1128            tid, instsInProgress[tid]);
1129}
1130
1131template <class Impl>
1132bool
1133DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1134{
1135    // Check if there's a squash signal, squash if there is
1136    // Check stall signals, block if necessary.
1137    // If status was blocked
1138    //     check if stall conditions have passed
1139    //         if so then go to unblocking
1140    // If status was Squashing
1141    //     check if squashing is not high.  Switch to running this cycle.
1142    // If status was serialize stall
1143    //     check if ROB is empty and no insts are in flight to the ROB
1144
1145    readFreeEntries(tid);
1146    readStallSignals(tid);
1147
1148    if (fromCommit->commitInfo[tid].squash) {
1149        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1150                "commit.\n", tid);
1151
1152        squash(tid);
1153
1154        return true;
1155    }
1156
1157    if (fromCommit->commitInfo[tid].robSquashing) {
1158        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1159
1160        renameStatus[tid] = Squashing;
1161
1162        return true;
1163    }
1164
1165    if (checkStall(tid)) {
1166        return block(tid);
1167    }
1168
1169    if (renameStatus[tid] == Blocked) {
1170        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1171                tid);
1172
1173        renameStatus[tid] = Unblocking;
1174
1175        unblock(tid);
1176
1177        return true;
1178    }
1179
1180    if (renameStatus[tid] == Squashing) {
1181        // Switch status to running if rename isn't being told to block or
1182        // squash this cycle.
1183        DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1184                tid);
1185
1186        renameStatus[tid] = Running;
1187
1188        return false;
1189    }
1190
1191    if (renameStatus[tid] == SerializeStall) {
1192        // Stall ends once the ROB is free.
1193        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1194                "unblocking.\n", tid);
1195
1196        DynInstPtr serial_inst = serializeInst[tid];
1197
1198        renameStatus[tid] = Unblocking;
1199
1200        unblock(tid);
1201
1202        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1203                "PC %#x.\n",
1204                tid, serial_inst->seqNum, serial_inst->readPC());
1205
1206        // Put instruction into queue here.
1207        serial_inst->clearSerializeBefore();
1208
1209        if (!skidBuffer[tid].empty()) {
1210            skidBuffer[tid].push_front(serial_inst);
1211        } else {
1212            insts[tid].push_front(serial_inst);
1213        }
1214
1215        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1216                " Adding to front of list.", tid);
1217
1218        serializeInst[tid] = NULL;
1219
1220        return true;
1221    }
1222
1223    // If we've reached this point, we have not gotten any signals that
1224    // cause rename to change its status.  Rename remains the same as before.
1225    return false;
1226}
1227
1228template<class Impl>
1229void
1230DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1231                                   unsigned tid)
1232{
1233    if (inst_list.empty()) {
1234        // Mark a bit to say that I must serialize on the next instruction.
1235        serializeOnNextInst[tid] = true;
1236        return;
1237    }
1238
1239    // Set the next instruction as serializing.
1240    inst_list.front()->setSerializeBefore();
1241}
1242
1243template <class Impl>
1244inline void
1245DefaultRename<Impl>::incrFullStat(const FullSource &source)
1246{
1247    switch (source) {
1248      case ROB:
1249        ++renameROBFullEvents;
1250        break;
1251      case IQ:
1252        ++renameIQFullEvents;
1253        break;
1254      case LSQ:
1255        ++renameLSQFullEvents;
1256        break;
1257      default:
1258        panic("Rename full stall stat should be incremented for a reason!");
1259        break;
1260    }
1261}
1262
1263template <class Impl>
1264void
1265DefaultRename<Impl>::dumpHistory()
1266{
1267    typename list<RenameHistory>::iterator buf_it;
1268
1269    for (int i = 0; i < numThreads; i++) {
1270
1271        buf_it = historyBuffer[i].begin();
1272
1273        while (buf_it != historyBuffer[i].end()) {
1274            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1275                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1276                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1277
1278            buf_it++;
1279        }
1280    }
1281}
1282