rename_impl.hh revision 2316 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <list>
30
31#include "config/full_system.hh"
32#include "cpu/o3/rename.hh"
33
34using namespace std;
35
36template <class Impl>
37DefaultRename<Impl>::DefaultRename(Params *params)
38    : iewToRenameDelay(params->iewToRenameDelay),
39      decodeToRenameDelay(params->decodeToRenameDelay),
40      commitToRenameDelay(params->commitToRenameDelay),
41      renameWidth(params->renameWidth),
42      commitWidth(params->commitWidth),
43      numThreads(params->numberOfThreads)
44{
45    _status = Inactive;
46
47    for (int i=0; i< numThreads; i++) {
48        renameStatus[i] = Idle;
49
50        freeEntries[i].iqEntries = 0;
51        freeEntries[i].lsqEntries = 0;
52        freeEntries[i].robEntries = 0;
53
54        stalls[i].iew = false;
55        stalls[i].commit = false;
56        serializeInst[i] = NULL;
57
58        instsInProgress[i] = 0;
59
60        emptyROB[i] = true;
61
62        serializeOnNextInst[i] = false;
63    }
64
65    // @todo: Make into a parameter.
66    skidBufferMax = (2 * (iewToRenameDelay * params->decodeWidth)) + renameWidth;
67}
68
69template <class Impl>
70std::string
71DefaultRename<Impl>::name() const
72{
73    return cpu->name() + ".rename";
74}
75
76template <class Impl>
77void
78DefaultRename<Impl>::regStats()
79{
80    renameSquashCycles
81        .name(name() + ".RENAME:SquashCycles")
82        .desc("Number of cycles rename is squashing")
83        .prereq(renameSquashCycles);
84    renameIdleCycles
85        .name(name() + ".RENAME:IdleCycles")
86        .desc("Number of cycles rename is idle")
87        .prereq(renameIdleCycles);
88    renameBlockCycles
89        .name(name() + ".RENAME:BlockCycles")
90        .desc("Number of cycles rename is blocking")
91        .prereq(renameBlockCycles);
92    renameSerializeStallCycles
93        .name(name() + ".RENAME:serializeStallCycles")
94        .desc("count of cycles rename stalled for serializing inst")
95        .flags(Stats::total);
96    renameRunCycles
97        .name(name() + ".RENAME:RunCycles")
98        .desc("Number of cycles rename is running")
99        .prereq(renameIdleCycles);
100    renameUnblockCycles
101        .name(name() + ".RENAME:UnblockCycles")
102        .desc("Number of cycles rename is unblocking")
103        .prereq(renameUnblockCycles);
104    renameRenamedInsts
105        .name(name() + ".RENAME:RenamedInsts")
106        .desc("Number of instructions processed by rename")
107        .prereq(renameRenamedInsts);
108    renameSquashedInsts
109        .name(name() + ".RENAME:SquashedInsts")
110        .desc("Number of squashed instructions processed by rename")
111        .prereq(renameSquashedInsts);
112    renameROBFullEvents
113        .name(name() + ".RENAME:ROBFullEvents")
114        .desc("Number of times rename has blocked due to ROB full")
115        .prereq(renameROBFullEvents);
116    renameIQFullEvents
117        .name(name() + ".RENAME:IQFullEvents")
118        .desc("Number of times rename has blocked due to IQ full")
119        .prereq(renameIQFullEvents);
120    renameLSQFullEvents
121        .name(name() + ".RENAME:LSQFullEvents")
122        .desc("Number of times rename has blocked due to LSQ full")
123        .prereq(renameLSQFullEvents);
124    renameFullRegistersEvents
125        .name(name() + ".RENAME:FullRegisterEvents")
126        .desc("Number of times there has been no free registers")
127        .prereq(renameFullRegistersEvents);
128    renameRenamedOperands
129        .name(name() + ".RENAME:RenamedOperands")
130        .desc("Number of destination operands rename has renamed")
131        .prereq(renameRenamedOperands);
132    renameRenameLookups
133        .name(name() + ".RENAME:RenameLookups")
134        .desc("Number of register rename lookups that rename has made")
135        .prereq(renameRenameLookups);
136    renameCommittedMaps
137        .name(name() + ".RENAME:CommittedMaps")
138        .desc("Number of HB maps that are committed")
139        .prereq(renameCommittedMaps);
140    renameUndoneMaps
141        .name(name() + ".RENAME:UndoneMaps")
142        .desc("Number of HB maps that are undone due to squashing")
143        .prereq(renameUndoneMaps);
144    renamedSerializing
145        .name(name() + ".RENAME:serializingInsts")
146        .desc("count of serializing insts renamed")
147        .flags(Stats::total)
148        ;
149    renamedTempSerializing
150        .name(name() + ".RENAME:tempSerializingInsts")
151        .desc("count of temporary serializing insts renamed")
152        .flags(Stats::total)
153        ;
154    renameSkidInsts
155        .name(name() + ".RENAME:skidInsts")
156        .desc("count of insts added to the skid buffer")
157        .flags(Stats::total)
158        ;
159}
160
161template <class Impl>
162void
163DefaultRename<Impl>::setCPU(FullCPU *cpu_ptr)
164{
165    DPRINTF(Rename, "Setting CPU pointer.\n");
166    cpu = cpu_ptr;
167}
168
169template <class Impl>
170void
171DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
172{
173    DPRINTF(Rename, "Setting time buffer pointer.\n");
174    timeBuffer = tb_ptr;
175
176    // Setup wire to read information from time buffer, from IEW stage.
177    fromIEW = timeBuffer->getWire(-iewToRenameDelay);
178
179    // Setup wire to read infromation from time buffer, from commit stage.
180    fromCommit = timeBuffer->getWire(-commitToRenameDelay);
181
182    // Setup wire to write information to previous stages.
183    toDecode = timeBuffer->getWire(0);
184}
185
186template <class Impl>
187void
188DefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
189{
190    DPRINTF(Rename, "Setting rename queue pointer.\n");
191    renameQueue = rq_ptr;
192
193    // Setup wire to write information to future stages.
194    toIEW = renameQueue->getWire(0);
195}
196
197template <class Impl>
198void
199DefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr)
200{
201    DPRINTF(Rename, "Setting decode queue pointer.\n");
202    decodeQueue = dq_ptr;
203
204    // Setup wire to get information from decode.
205    fromDecode = decodeQueue->getWire(-decodeToRenameDelay);
206}
207
208template <class Impl>
209void
210DefaultRename<Impl>::initStage()
211{
212    for (int tid=0; tid < numThreads; tid++) {
213        freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
214        freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
215        freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
216        emptyROB[tid] = true;
217    }
218
219    // Clear these pointers so they are not accidentally used in
220    // non-initialization code.
221//    iew_ptr = NULL;
222//    commit_ptr = NULL;
223}
224
225template<class Impl>
226void
227DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
228{
229    DPRINTF(Rename, "Setting active threads list pointer.\n");
230    activeThreads = at_ptr;
231}
232
233
234template <class Impl>
235void
236DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
237{
238    DPRINTF(Rename, "Setting rename map pointers.\n");
239
240    for (int i=0; i<numThreads; i++) {
241        renameMap[i] = &rm_ptr[i];
242    }
243}
244
245template <class Impl>
246void
247DefaultRename<Impl>::setFreeList(FreeList *fl_ptr)
248{
249    DPRINTF(Rename, "Setting free list pointer.\n");
250    freeList = fl_ptr;
251}
252
253template<class Impl>
254void
255DefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard)
256{
257    DPRINTF(Rename, "Setting scoreboard pointer.\n");
258    scoreboard = _scoreboard;
259}
260
261template <class Impl>
262void
263DefaultRename<Impl>::switchOut()
264{
265    cpu->signalSwitched();
266}
267
268template <class Impl>
269void
270DefaultRename<Impl>::doSwitchOut()
271{
272    for (int i = 0; i < numThreads; i++) {
273        typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
274
275        while (!historyBuffer[i].empty()) {
276            assert(hb_it != historyBuffer[i].end());
277
278            DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
279                    "number %i.\n", i, (*hb_it).instSeqNum);
280
281            // Tell the rename map to set the architected register to the
282            // previous physical register that it was renamed to.
283            renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
284
285            // Put the renamed physical register back on the free list.
286            freeList->addReg(hb_it->newPhysReg);
287
288            historyBuffer[i].erase(hb_it++);
289        }
290        insts[i].clear();
291        skidBuffer[i].clear();
292    }
293}
294
295template <class Impl>
296void
297DefaultRename<Impl>::takeOverFrom()
298{
299    _status = Inactive;
300    initStage();
301
302    for (int i=0; i< numThreads; i++) {
303        renameStatus[i] = Idle;
304
305        stalls[i].iew = false;
306        stalls[i].commit = false;
307        serializeInst[i] = NULL;
308
309        instsInProgress[i] = 0;
310
311        emptyROB[i] = true;
312
313        serializeOnNextInst[i] = false;
314    }
315}
316
317template <class Impl>
318void
319DefaultRename<Impl>::squash(unsigned tid)
320{
321    DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
322
323    // Clear the stall signal if rename was blocked or unblocking before.
324    // If it still needs to block, the blocking should happen the next
325    // cycle and there should be space to hold everything due to the squash.
326    if (renameStatus[tid] == Blocked ||
327        renameStatus[tid] == Unblocking ||
328        renameStatus[tid] == SerializeStall) {
329#if !FULL_SYSTEM
330        // In syscall emulation, we can have both a block and a squash due
331        // to a syscall in the same cycle.  This would cause both signals to
332        // be high.  This shouldn't happen in full system.
333        if (toDecode->renameBlock[tid]) {
334            toDecode->renameBlock[tid] = 0;
335        } else {
336            toDecode->renameUnblock[tid] = 1;
337        }
338#else
339        toDecode->renameUnblock[tid] = 1;
340#endif
341        serializeInst[tid] = NULL;
342    }
343
344    // Set the status to Squashing.
345    renameStatus[tid] = Squashing;
346
347    // Clear the skid buffer in case it has any data in it.
348    unsigned squashCount = 0;
349
350    for (int i=0; i<fromDecode->size; i++) {
351        if (fromDecode->insts[i]->threadNumber == tid) {
352            fromDecode->insts[i]->squashed = true;
353            wroteToTimeBuffer = true;
354            squashCount++;
355        }
356    }
357
358    insts[tid].clear();
359
360    // Clear the skid buffer in case it has any data in it.
361    skidBuffer[tid].clear();
362
363    doSquash(tid);
364}
365
366template <class Impl>
367void
368DefaultRename<Impl>::tick()
369{
370    // Rename will need to try to rename as many instructions as it
371    // has bandwidth, unless it is blocked.
372
373    wroteToTimeBuffer = false;
374
375    blockThisCycle = false;
376
377    bool status_change = false;
378
379    toIEWIndex = 0;
380
381    sortInsts();
382
383    list<unsigned>::iterator threads = (*activeThreads).begin();
384
385    // Check stall and squash signals.
386    while (threads != (*activeThreads).end()) {
387        unsigned tid = *threads++;
388
389        DPRINTF(Rename, "Processing [tid:%i]\n", tid);
390
391        status_change = checkSignalsAndUpdate(tid) || status_change;
392
393        rename(status_change, tid);
394    }
395
396    if (status_change) {
397        updateStatus();
398    }
399
400    if (wroteToTimeBuffer) {
401        DPRINTF(Activity, "Activity this cycle.\n");
402        cpu->activityThisCycle();
403    }
404
405    threads = (*activeThreads).begin();
406
407    while (threads != (*activeThreads).end()) {
408        unsigned tid = *threads++;
409
410        // If we committed this cycle then doneSeqNum will be > 0
411        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
412            !fromCommit->commitInfo[tid].squash &&
413            renameStatus[tid] != Squashing) {
414
415            removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum,
416                                  tid);
417        }
418    }
419
420    // @todo: make into updateProgress function
421    for (int tid=0; tid < numThreads; tid++) {
422        instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
423
424        assert(instsInProgress[tid] >=0);
425    }
426
427}
428
429template<class Impl>
430void
431DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
432{
433    // If status is Running or idle,
434    //     call renameInsts()
435    // If status is Unblocking,
436    //     buffer any instructions coming from decode
437    //     continue trying to empty skid buffer
438    //     check if stall conditions have passed
439
440    if (renameStatus[tid] == Blocked) {
441        ++renameBlockCycles;
442    } else if (renameStatus[tid] == Squashing) {
443        ++renameSquashCycles;
444    } else if (renameStatus[tid] == SerializeStall) {
445        ++renameSerializeStallCycles;
446    }
447
448    if (renameStatus[tid] == Running ||
449        renameStatus[tid] == Idle) {
450        DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run "
451                "stage.\n", tid);
452
453        renameInsts(tid);
454    } else if (renameStatus[tid] == Unblocking) {
455        renameInsts(tid);
456
457//        ++renameUnblockCycles;
458
459        if (validInsts()) {
460            // Add the current inputs to the skid buffer so they can be
461            // reprocessed when this stage unblocks.
462            skidInsert(tid);
463        }
464
465        // If we switched over to blocking, then there's a potential for
466        // an overall status change.
467        status_change = unblock(tid) || status_change || blockThisCycle;
468    }
469}
470
471template <class Impl>
472void
473DefaultRename<Impl>::renameInsts(unsigned tid)
474{
475    // Instructions can be either in the skid buffer or the queue of
476    // instructions coming from decode, depending on the status.
477    int insts_available = renameStatus[tid] == Unblocking ?
478        skidBuffer[tid].size() : insts[tid].size();
479
480    // Check the decode queue to see if instructions are available.
481    // If there are no available instructions to rename, then do nothing.
482    if (insts_available == 0) {
483        DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n",
484                tid);
485        // Should I change status to idle?
486        ++renameIdleCycles;
487        return;
488    } else if (renameStatus[tid] == Unblocking) {
489        ++renameUnblockCycles;
490    } else if (renameStatus[tid] == Running) {
491        ++renameRunCycles;
492    }
493
494    DynInstPtr inst;
495
496    // Will have to do a different calculation for the number of free
497    // entries.
498    int free_rob_entries = calcFreeROBEntries(tid);
499    int free_iq_entries  = calcFreeIQEntries(tid);
500    int free_lsq_entries = calcFreeLSQEntries(tid);
501    int min_free_entries = free_rob_entries;
502
503    FullSource source = ROB;
504
505    if (free_iq_entries < min_free_entries) {
506        min_free_entries = free_iq_entries;
507        source = IQ;
508    }
509
510    if (free_lsq_entries < min_free_entries) {
511        min_free_entries = free_lsq_entries;
512        source = LSQ;
513    }
514
515    // Check if there's any space left.
516    if (min_free_entries <= 0) {
517        DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ "
518                "entries.\n"
519                "ROB has %i free entries.\n"
520                "IQ has %i free entries.\n"
521                "LSQ has %i free entries.\n",
522                tid,
523                free_rob_entries,
524                free_iq_entries,
525                free_lsq_entries);
526
527        blockThisCycle = true;
528
529        block(tid);
530
531        incrFullStat(source);
532
533        return;
534    } else if (min_free_entries < insts_available) {
535        DPRINTF(Rename, "[tid:%u]: Will have to block this cycle."
536                "%i insts available, but only %i insts can be "
537                "renamed due to ROB/IQ/LSQ limits.\n",
538                tid, insts_available, min_free_entries);
539
540        insts_available = min_free_entries;
541
542        blockThisCycle = true;
543
544        incrFullStat(source);
545    }
546
547    InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ?
548        skidBuffer[tid] : insts[tid];
549
550    DPRINTF(Rename, "[tid:%u]: %i available instructions to "
551            "send iew.\n", tid, insts_available);
552
553    DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts "
554            "dispatched to IQ last cycle.\n",
555            tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched);
556
557    // Handle serializing the next instruction if necessary.
558    if (serializeOnNextInst[tid]) {
559        if (emptyROB[tid] && instsInProgress[tid] == 0) {
560            // ROB already empty; no need to serialize.
561            serializeOnNextInst[tid] = false;
562        } else if (!insts_to_rename.empty()) {
563            insts_to_rename.front()->setSerializeBefore();
564        }
565    }
566
567    int renamed_insts = 0;
568
569    while (insts_available > 0 &&  toIEWIndex < renameWidth) {
570        DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid);
571
572        assert(!insts_to_rename.empty());
573
574        inst = insts_to_rename.front();
575
576        insts_to_rename.pop_front();
577
578        //Use skidBuffer with oldest instructions
579        if (renameStatus[tid] == Unblocking) {
580            DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%#x from rename "
581                    "skidBuffer\n",
582                    tid, inst->seqNum, inst->readPC());
583        }
584
585        if (inst->isSquashed()) {
586            DPRINTF(Rename, "[tid:%u]: instruction %i with PC %#x is "
587                    "squashed, skipping.\n",
588                    tid, inst->seqNum, inst->threadNumber,inst->readPC());
589
590            ++renameSquashedInsts;
591
592            // Decrement how many instructions are available.
593            --insts_available;
594
595            continue;
596        }
597
598        DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with "
599                "PC %#x.\n",
600                tid, inst->seqNum, inst->readPC());
601
602        // Handle serializeAfter/serializeBefore instructions.
603        // serializeAfter marks the next instruction as serializeBefore.
604        // serializeBefore makes the instruction wait in rename until the ROB
605        // is empty.
606        if (inst->isSerializeBefore() && !inst->isSerializeHandled()) {
607            DPRINTF(Rename, "Serialize before instruction encountered.\n");
608
609            if (!inst->isTempSerializeBefore()) {
610                renamedSerializing++;
611                inst->setSerializeHandled();
612            } else {
613                renamedTempSerializing++;
614            }
615
616            // Change status over to SerializeStall so that other stages know
617            // what this is blocked on.
618            renameStatus[tid] = SerializeStall;
619
620            serializeInst[tid] = inst;
621
622            blockThisCycle = true;
623
624            break;
625        } else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) {
626            DPRINTF(Rename, "Serialize after instruction encountered.\n");
627
628            renamedSerializing++;
629
630            inst->setSerializeHandled();
631
632            serializeAfter(insts_to_rename, tid);
633        }
634
635        // Check here to make sure there are enough destination registers
636        // to rename to.  Otherwise block.
637        if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) {
638            DPRINTF(Rename, "Blocking due to lack of free "
639                    "physical registers to rename to.\n");
640            blockThisCycle = true;
641
642            ++renameFullRegistersEvents;
643
644            break;
645        }
646
647        renameSrcRegs(inst, inst->threadNumber);
648
649        renameDestRegs(inst, inst->threadNumber);
650
651        ++renamed_insts;
652
653        // Put instruction in rename queue.
654        toIEW->insts[toIEWIndex] = inst;
655        ++(toIEW->size);
656
657        // Increment which instruction we're on.
658        ++toIEWIndex;
659
660        // Decrement how many instructions are available.
661        --insts_available;
662    }
663
664    instsInProgress[tid] += renamed_insts;
665    renameRenamedInsts += renamed_insts;
666
667    // If we wrote to the time buffer, record this.
668    if (toIEWIndex) {
669        wroteToTimeBuffer = true;
670    }
671
672    // Check if there's any instructions left that haven't yet been renamed.
673    // If so then block.
674    if (insts_available) {
675        blockThisCycle = true;
676    }
677
678    if (blockThisCycle) {
679        block(tid);
680        toDecode->renameUnblock[tid] = false;
681    }
682}
683
684template<class Impl>
685void
686DefaultRename<Impl>::skidInsert(unsigned tid)
687{
688    DynInstPtr inst = NULL;
689
690    while (!insts[tid].empty()) {
691        inst = insts[tid].front();
692
693        insts[tid].pop_front();
694
695        assert(tid == inst->threadNumber);
696
697        DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC:%#x into Rename "
698                "skidBuffer\n", tid, inst->seqNum, inst->readPC());
699
700        ++renameSkidInsts;
701
702        skidBuffer[tid].push_back(inst);
703    }
704
705    if (skidBuffer[tid].size() > skidBufferMax)
706        panic("Skidbuffer Exceeded Max Size");
707}
708
709template <class Impl>
710void
711DefaultRename<Impl>::sortInsts()
712{
713    int insts_from_decode = fromDecode->size;
714
715    for (int i=0; i < numThreads; i++)
716        assert(insts[i].empty());
717
718    for (int i = 0; i < insts_from_decode; ++i) {
719        DynInstPtr inst = fromDecode->insts[i];
720        insts[inst->threadNumber].push_back(inst);
721    }
722}
723
724template<class Impl>
725bool
726DefaultRename<Impl>::skidsEmpty()
727{
728    list<unsigned>::iterator threads = (*activeThreads).begin();
729
730    while (threads != (*activeThreads).end()) {
731        if (!skidBuffer[*threads++].empty())
732            return false;
733    }
734
735    return true;
736}
737
738template<class Impl>
739void
740DefaultRename<Impl>::updateStatus()
741{
742    bool any_unblocking = false;
743
744    list<unsigned>::iterator threads = (*activeThreads).begin();
745
746    threads = (*activeThreads).begin();
747
748    while (threads != (*activeThreads).end()) {
749        unsigned tid = *threads++;
750
751        if (renameStatus[tid] == Unblocking) {
752            any_unblocking = true;
753            break;
754        }
755    }
756
757    // Rename will have activity if it's unblocking.
758    if (any_unblocking) {
759        if (_status == Inactive) {
760            _status = Active;
761
762            DPRINTF(Activity, "Activating stage.\n");
763
764            cpu->activateStage(FullCPU::RenameIdx);
765        }
766    } else {
767        // If it's not unblocking, then rename will not have any internal
768        // activity.  Switch it to inactive.
769        if (_status == Active) {
770            _status = Inactive;
771            DPRINTF(Activity, "Deactivating stage.\n");
772
773            cpu->deactivateStage(FullCPU::RenameIdx);
774        }
775    }
776}
777
778template <class Impl>
779bool
780DefaultRename<Impl>::block(unsigned tid)
781{
782    DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
783
784    // Add the current inputs onto the skid buffer, so they can be
785    // reprocessed when this stage unblocks.
786    skidInsert(tid);
787
788    // Only signal backwards to block if the previous stages do not think
789    // rename is already blocked.
790    if (renameStatus[tid] != Blocked) {
791        if (renameStatus[tid] != Unblocking) {
792            toDecode->renameBlock[tid] = true;
793            toDecode->renameUnblock[tid] = false;
794            wroteToTimeBuffer = true;
795        }
796
797        // Rename can not go from SerializeStall to Blocked, otherwise it would
798        // not know to complete the serialize stall.
799        if (renameStatus[tid] != SerializeStall) {
800            // Set status to Blocked.
801            renameStatus[tid] = Blocked;
802            return true;
803        }
804    }
805
806    return false;
807}
808
809template <class Impl>
810bool
811DefaultRename<Impl>::unblock(unsigned tid)
812{
813    DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
814
815    // Rename is done unblocking if the skid buffer is empty.
816    if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) {
817
818        DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid);
819
820        toDecode->renameUnblock[tid] = true;
821        wroteToTimeBuffer = true;
822
823        renameStatus[tid] = Running;
824        return true;
825    }
826
827    return false;
828}
829
830template <class Impl>
831void
832DefaultRename<Impl>::doSquash(unsigned tid)
833{
834    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
835
836    InstSeqNum squashed_seq_num = fromCommit->commitInfo[tid].doneSeqNum;
837
838//#if FULL_SYSTEM
839//    assert(!historyBuffer[tid].empty());
840//#else
841    // After a syscall squashes everything, the history buffer may be empty
842    // but the ROB may still be squashing instructions.
843    if (historyBuffer[tid].empty()) {
844        return;
845    }
846//#endif // FULL_SYSTEM
847
848    // Go through the most recent instructions, undoing the mappings
849    // they did and freeing up the registers.
850    while (!historyBuffer[tid].empty() &&
851           (*hb_it).instSeqNum > squashed_seq_num) {
852        assert(hb_it != historyBuffer[tid].end());
853
854        DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
855                "number %i.\n", tid, (*hb_it).instSeqNum);
856
857        // Tell the rename map to set the architected register to the
858        // previous physical register that it was renamed to.
859        renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
860
861        // Put the renamed physical register back on the free list.
862        freeList->addReg(hb_it->newPhysReg);
863
864        historyBuffer[tid].erase(hb_it++);
865
866        ++renameUndoneMaps;
867    }
868}
869
870template<class Impl>
871void
872DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
873{
874    DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
875            "history buffer %u (size=%i), until [sn:%lli].\n",
876            tid, tid, historyBuffer[tid].size(), inst_seq_num);
877
878    typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
879
880    --hb_it;
881
882    if (historyBuffer[tid].empty()) {
883        DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid);
884        return;
885    } else if (hb_it->instSeqNum > inst_seq_num) {
886        DPRINTF(Rename, "[tid:%u]: Old sequence number encountered.  Ensure "
887                "that a syscall happened recently.\n", tid);
888        return;
889    }
890
891    // Commit all the renames up until (and including) the committed sequence
892    // number. Some or even all of the committed instructions may not have
893    // rename histories if they did not have destination registers that were
894    // renamed.
895    while (!historyBuffer[tid].empty() &&
896           hb_it != historyBuffer[tid].end() &&
897           (*hb_it).instSeqNum <= inst_seq_num) {
898
899        DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, sequence"
900                " number %i.\n",
901                tid, (*hb_it).prevPhysReg, (*hb_it).instSeqNum);
902
903        freeList->addReg((*hb_it).prevPhysReg);
904        ++renameCommittedMaps;
905
906        historyBuffer[tid].erase(hb_it--);
907    }
908}
909
910template <class Impl>
911inline void
912DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
913{
914    assert(renameMap[tid] != 0);
915
916    unsigned num_src_regs = inst->numSrcRegs();
917
918    // Get the architectual register numbers from the source and
919    // destination operands, and redirect them to the right register.
920    // Will need to mark dependencies though.
921    for (int src_idx = 0; src_idx < num_src_regs; src_idx++) {
922        RegIndex src_reg = inst->srcRegIdx(src_idx);
923
924        // Look up the source registers to get the phys. register they've
925        // been renamed to, and set the sources to those registers.
926        PhysRegIndex renamed_reg = renameMap[tid]->lookup(src_reg);
927
928        DPRINTF(Rename, "[tid:%u]: Looking up arch reg %i, got "
929                "physical reg %i.\n", tid, (int)src_reg,
930                (int)renamed_reg);
931
932        inst->renameSrcReg(src_idx, renamed_reg);
933
934        // See if the register is ready or not.
935        if (scoreboard->getReg(renamed_reg) == true) {
936            DPRINTF(Rename, "[tid:%u]: Register is ready.\n", tid);
937
938            inst->markSrcRegReady(src_idx);
939        }
940
941        ++renameRenameLookups;
942    }
943}
944
945template <class Impl>
946inline void
947DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
948{
949    typename RenameMap::RenameInfo rename_result;
950
951    unsigned num_dest_regs = inst->numDestRegs();
952
953    // Rename the destination registers.
954    for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) {
955        RegIndex dest_reg = inst->destRegIdx(dest_idx);
956
957        // Get the physical register that the destination will be
958        // renamed to.
959        rename_result = renameMap[tid]->rename(dest_reg);
960
961        //Mark Scoreboard entry as not ready
962        scoreboard->unsetReg(rename_result.first);
963
964        DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical "
965                "reg %i.\n", tid, (int)dest_reg,
966                (int)rename_result.first);
967
968        // Record the rename information so that a history can be kept.
969        RenameHistory hb_entry(inst->seqNum, dest_reg,
970                               rename_result.first,
971                               rename_result.second);
972
973        historyBuffer[tid].push_front(hb_entry);
974
975        DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer, "
976                "[sn:%lli].\n",tid,
977                (*historyBuffer[tid].begin()).instSeqNum);
978
979        // Tell the instruction to rename the appropriate destination
980        // register (dest_idx) to the new physical register
981        // (rename_result.first), and record the previous physical
982        // register that the same logical register was renamed to
983        // (rename_result.second).
984        inst->renameDestReg(dest_idx,
985                            rename_result.first,
986                            rename_result.second);
987
988        ++renameRenamedOperands;
989    }
990}
991
992template <class Impl>
993inline int
994DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
995{
996    int num_free = freeEntries[tid].robEntries -
997                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
998
999    //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free);
1000
1001    return num_free;
1002}
1003
1004template <class Impl>
1005inline int
1006DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
1007{
1008    int num_free = freeEntries[tid].iqEntries -
1009                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
1010
1011    //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free);
1012
1013    return num_free;
1014}
1015
1016template <class Impl>
1017inline int
1018DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
1019{
1020    int num_free = freeEntries[tid].lsqEntries -
1021                  (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
1022
1023    //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free);
1024
1025    return num_free;
1026}
1027
1028template <class Impl>
1029unsigned
1030DefaultRename<Impl>::validInsts()
1031{
1032    unsigned inst_count = 0;
1033
1034    for (int i=0; i<fromDecode->size; i++) {
1035        if (!fromDecode->insts[i]->squashed)
1036            inst_count++;
1037    }
1038
1039    return inst_count;
1040}
1041
1042template <class Impl>
1043void
1044DefaultRename<Impl>::readStallSignals(unsigned tid)
1045{
1046    if (fromIEW->iewBlock[tid]) {
1047        stalls[tid].iew = true;
1048    }
1049
1050    if (fromIEW->iewUnblock[tid]) {
1051        assert(stalls[tid].iew);
1052        stalls[tid].iew = false;
1053    }
1054
1055    if (fromCommit->commitBlock[tid]) {
1056        stalls[tid].commit = true;
1057    }
1058
1059    if (fromCommit->commitUnblock[tid]) {
1060        assert(stalls[tid].commit);
1061        stalls[tid].commit = false;
1062    }
1063}
1064
1065template <class Impl>
1066bool
1067DefaultRename<Impl>::checkStall(unsigned tid)
1068{
1069    bool ret_val = false;
1070
1071    if (stalls[tid].iew) {
1072        DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid);
1073        ret_val = true;
1074    } else if (stalls[tid].commit) {
1075        DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid);
1076        ret_val = true;
1077    } else if (calcFreeROBEntries(tid) <= 0) {
1078        DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid);
1079        ret_val = true;
1080    } else if (calcFreeIQEntries(tid) <= 0) {
1081        DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid);
1082        ret_val = true;
1083    } else if (calcFreeLSQEntries(tid) <= 0) {
1084        DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid);
1085        ret_val = true;
1086    } else if (renameMap[tid]->numFreeEntries() <= 0) {
1087        DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid);
1088        ret_val = true;
1089    } else if (renameStatus[tid] == SerializeStall &&
1090               (!emptyROB[tid] || instsInProgress[tid])) {
1091        DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not "
1092                "empty.\n",
1093                tid);
1094        ret_val = true;
1095    }
1096
1097    return ret_val;
1098}
1099
1100template <class Impl>
1101void
1102DefaultRename<Impl>::readFreeEntries(unsigned tid)
1103{
1104    bool updated = false;
1105    if (fromIEW->iewInfo[tid].usedIQ) {
1106        freeEntries[tid].iqEntries =
1107            fromIEW->iewInfo[tid].freeIQEntries;
1108        updated = true;
1109    }
1110
1111    if (fromIEW->iewInfo[tid].usedLSQ) {
1112        freeEntries[tid].lsqEntries =
1113            fromIEW->iewInfo[tid].freeLSQEntries;
1114        updated = true;
1115    }
1116
1117    if (fromCommit->commitInfo[tid].usedROB) {
1118        freeEntries[tid].robEntries =
1119            fromCommit->commitInfo[tid].freeROBEntries;
1120        emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
1121        updated = true;
1122    }
1123
1124    DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",
1125            tid,
1126            freeEntries[tid].iqEntries,
1127            freeEntries[tid].robEntries,
1128            freeEntries[tid].lsqEntries);
1129
1130    DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n",
1131            tid, instsInProgress[tid]);
1132}
1133
1134template <class Impl>
1135bool
1136DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
1137{
1138    // Check if there's a squash signal, squash if there is
1139    // Check stall signals, block if necessary.
1140    // If status was blocked
1141    //     check if stall conditions have passed
1142    //         if so then go to unblocking
1143    // If status was Squashing
1144    //     check if squashing is not high.  Switch to running this cycle.
1145    // If status was serialize stall
1146    //     check if ROB is empty and no insts are in flight to the ROB
1147
1148    readFreeEntries(tid);
1149    readStallSignals(tid);
1150
1151    if (fromCommit->commitInfo[tid].squash) {
1152        DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from "
1153                "commit.\n", tid);
1154
1155        squash(tid);
1156
1157        return true;
1158    }
1159
1160    if (fromCommit->commitInfo[tid].robSquashing) {
1161        DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid);
1162
1163        renameStatus[tid] = Squashing;
1164
1165        return true;
1166    }
1167
1168    if (checkStall(tid)) {
1169        return block(tid);
1170    }
1171
1172    if (renameStatus[tid] == Blocked) {
1173        DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n",
1174                tid);
1175
1176        renameStatus[tid] = Unblocking;
1177
1178        unblock(tid);
1179
1180        return true;
1181    }
1182
1183    if (renameStatus[tid] == Squashing) {
1184        // Switch status to running if rename isn't being told to block or
1185        // squash this cycle.
1186        DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n",
1187                tid);
1188
1189        renameStatus[tid] = Running;
1190
1191        return false;
1192    }
1193
1194    if (renameStatus[tid] == SerializeStall) {
1195        // Stall ends once the ROB is free.
1196        DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to "
1197                "unblocking.\n", tid);
1198
1199        DynInstPtr serial_inst = serializeInst[tid];
1200
1201        renameStatus[tid] = Unblocking;
1202
1203        unblock(tid);
1204
1205        DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with "
1206                "PC %#x.\n",
1207                tid, serial_inst->seqNum, serial_inst->readPC());
1208
1209        // Put instruction into queue here.
1210        serial_inst->clearSerializeBefore();
1211
1212        if (!skidBuffer[tid].empty()) {
1213            skidBuffer[tid].push_front(serial_inst);
1214        } else {
1215            insts[tid].push_front(serial_inst);
1216        }
1217
1218        DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename."
1219                " Adding to front of list.", tid);
1220
1221        serializeInst[tid] = NULL;
1222
1223        return true;
1224    }
1225
1226    // If we've reached this point, we have not gotten any signals that
1227    // cause rename to change its status.  Rename remains the same as before.
1228    return false;
1229}
1230
1231template<class Impl>
1232void
1233DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
1234                                   unsigned tid)
1235{
1236    if (inst_list.empty()) {
1237        // Mark a bit to say that I must serialize on the next instruction.
1238        serializeOnNextInst[tid] = true;
1239        return;
1240    }
1241
1242    // Set the next instruction as serializing.
1243    inst_list.front()->setSerializeBefore();
1244}
1245
1246template <class Impl>
1247inline void
1248DefaultRename<Impl>::incrFullStat(const FullSource &source)
1249{
1250    switch (source) {
1251      case ROB:
1252        ++renameROBFullEvents;
1253        break;
1254      case IQ:
1255        ++renameIQFullEvents;
1256        break;
1257      case LSQ:
1258        ++renameLSQFullEvents;
1259        break;
1260      default:
1261        panic("Rename full stall stat should be incremented for a reason!");
1262        break;
1263    }
1264}
1265
1266template <class Impl>
1267void
1268DefaultRename<Impl>::dumpHistory()
1269{
1270    typename list<RenameHistory>::iterator buf_it;
1271
1272    for (int i = 0; i < numThreads; i++) {
1273
1274        buf_it = historyBuffer[i].begin();
1275
1276        while (buf_it != historyBuffer[i].end()) {
1277            cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
1278                    "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
1279                    (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);
1280
1281            buf_it++;
1282        }
1283    }
1284}
1285