rename_impl.hh revision 13652
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 7012109SRekai.GonzalezAlberquilla@arm.com numThreads(params->numThreads) 711060SN/A{ 7210172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7310172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610172Sdam.sunwoo@arm.com 772292SN/A // @todo: Make into a parameter. 7810328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 7913453Srekai.gonzalezalberquilla@arm.com for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 8013453Srekai.gonzalezalberquilla@arm.com renameStatus[tid] = Idle; 8113453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 8213453Srekai.gonzalezalberquilla@arm.com instsInProgress[tid] = 0; 8313453Srekai.gonzalezalberquilla@arm.com loadsInProgress[tid] = 0; 8413453Srekai.gonzalezalberquilla@arm.com storesInProgress[tid] = 0; 8513453Srekai.gonzalezalberquilla@arm.com freeEntries[tid] = {0, 0, 0, 0}; 8613453Srekai.gonzalezalberquilla@arm.com emptyROB[tid] = true; 8713453Srekai.gonzalezalberquilla@arm.com stalls[tid] = {false, false}; 8813453Srekai.gonzalezalberquilla@arm.com serializeInst[tid] = nullptr; 8913453Srekai.gonzalezalberquilla@arm.com serializeOnNextInst[tid] = false; 9013453Srekai.gonzalezalberquilla@arm.com } 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 942292SN/Astd::string 952292SN/ADefaultRename<Impl>::name() const 962292SN/A{ 972292SN/A return cpu->name() + ".rename"; 981060SN/A} 991060SN/A 1001061SN/Atemplate <class Impl> 1011060SN/Avoid 1022292SN/ADefaultRename<Impl>::regStats() 1031062SN/A{ 1041062SN/A renameSquashCycles 1058240Snate@binkert.org .name(name() + ".SquashCycles") 1061062SN/A .desc("Number of cycles rename is squashing") 1071062SN/A .prereq(renameSquashCycles); 1081062SN/A renameIdleCycles 1098240Snate@binkert.org .name(name() + ".IdleCycles") 1101062SN/A .desc("Number of cycles rename is idle") 1111062SN/A .prereq(renameIdleCycles); 1121062SN/A renameBlockCycles 1138240Snate@binkert.org .name(name() + ".BlockCycles") 1141062SN/A .desc("Number of cycles rename is blocking") 1151062SN/A .prereq(renameBlockCycles); 1162301SN/A renameSerializeStallCycles 1178240Snate@binkert.org .name(name() + ".serializeStallCycles") 1182301SN/A .desc("count of cycles rename stalled for serializing inst") 1192301SN/A .flags(Stats::total); 1202292SN/A renameRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles rename is running") 1232292SN/A .prereq(renameIdleCycles); 1241062SN/A renameUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles rename is unblocking") 1271062SN/A .prereq(renameUnblockCycles); 1281062SN/A renameRenamedInsts 1298240Snate@binkert.org .name(name() + ".RenamedInsts") 1301062SN/A .desc("Number of instructions processed by rename") 1311062SN/A .prereq(renameRenamedInsts); 1321062SN/A renameSquashedInsts 1338240Snate@binkert.org .name(name() + ".SquashedInsts") 1341062SN/A .desc("Number of squashed instructions processed by rename") 1351062SN/A .prereq(renameSquashedInsts); 1361062SN/A renameROBFullEvents 1378240Snate@binkert.org .name(name() + ".ROBFullEvents") 1382292SN/A .desc("Number of times rename has blocked due to ROB full") 1391062SN/A .prereq(renameROBFullEvents); 1401062SN/A renameIQFullEvents 1418240Snate@binkert.org .name(name() + ".IQFullEvents") 1422292SN/A .desc("Number of times rename has blocked due to IQ full") 1431062SN/A .prereq(renameIQFullEvents); 14410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 14510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 14610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 14710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 14810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 14910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 15010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 15110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1521062SN/A renameFullRegistersEvents 1538240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1541062SN/A .desc("Number of times there has been no free registers") 1551062SN/A .prereq(renameFullRegistersEvents); 1561062SN/A renameRenamedOperands 1578240Snate@binkert.org .name(name() + ".RenamedOperands") 1581062SN/A .desc("Number of destination operands rename has renamed") 1591062SN/A .prereq(renameRenamedOperands); 1601062SN/A renameRenameLookups 1618240Snate@binkert.org .name(name() + ".RenameLookups") 1621062SN/A .desc("Number of register rename lookups that rename has made") 1631062SN/A .prereq(renameRenameLookups); 1641062SN/A renameCommittedMaps 1658240Snate@binkert.org .name(name() + ".CommittedMaps") 1661062SN/A .desc("Number of HB maps that are committed") 1671062SN/A .prereq(renameCommittedMaps); 1681062SN/A renameUndoneMaps 1698240Snate@binkert.org .name(name() + ".UndoneMaps") 1701062SN/A .desc("Number of HB maps that are undone due to squashing") 1711062SN/A .prereq(renameUndoneMaps); 1722301SN/A renamedSerializing 1738240Snate@binkert.org .name(name() + ".serializingInsts") 1742301SN/A .desc("count of serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772301SN/A renamedTempSerializing 1788240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1792301SN/A .desc("count of temporary serializing insts renamed") 1802301SN/A .flags(Stats::total) 1812301SN/A ; 1822307SN/A renameSkidInsts 1838240Snate@binkert.org .name(name() + ".skidInsts") 1842307SN/A .desc("count of insts added to the skid buffer") 1852307SN/A .flags(Stats::total) 1862307SN/A ; 1877897Shestness@cs.utexas.edu intRenameLookups 1888240Snate@binkert.org .name(name() + ".int_rename_lookups") 1897897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1907897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1917897Shestness@cs.utexas.edu fpRenameLookups 1928240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1937897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1947897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 19512109SRekai.GonzalezAlberquilla@arm.com vecRenameLookups 19612109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_rename_lookups") 19712109SRekai.GonzalezAlberquilla@arm.com .desc("Number of vector rename lookups") 19812109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRenameLookups); 19913610Sgiacomo.gabrielli@arm.com vecPredRenameLookups 20013610Sgiacomo.gabrielli@arm.com .name(name() + ".vec_pred_rename_lookups") 20113610Sgiacomo.gabrielli@arm.com .desc("Number of vector predicate rename lookups") 20213610Sgiacomo.gabrielli@arm.com .prereq(vecPredRenameLookups); 2031062SN/A} 2041062SN/A 2051062SN/Atemplate <class Impl> 2061062SN/Avoid 20711246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 20811246Sradhika.jagtap@ARM.com{ 20911246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 21011246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 21111246Sradhika.jagtap@ARM.com "SquashInRename"); 21211246Sradhika.jagtap@ARM.com} 21311246Sradhika.jagtap@ARM.com 21411246Sradhika.jagtap@ARM.comtemplate <class Impl> 21511246Sradhika.jagtap@ARM.comvoid 2162292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2171060SN/A{ 2181060SN/A timeBuffer = tb_ptr; 2191060SN/A 2201060SN/A // Setup wire to read information from time buffer, from IEW stage. 2211060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2221060SN/A 2231060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2241060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2251060SN/A 2261060SN/A // Setup wire to write information to previous stages. 2271060SN/A toDecode = timeBuffer->getWire(0); 2281060SN/A} 2291060SN/A 2301061SN/Atemplate <class Impl> 2311060SN/Avoid 2322292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2331060SN/A{ 2341060SN/A renameQueue = rq_ptr; 2351060SN/A 2361060SN/A // Setup wire to write information to future stages. 2371060SN/A toIEW = renameQueue->getWire(0); 2381060SN/A} 2391060SN/A 2401061SN/Atemplate <class Impl> 2411060SN/Avoid 2422292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2431060SN/A{ 2441060SN/A decodeQueue = dq_ptr; 2451060SN/A 2461060SN/A // Setup wire to get information from decode. 2471060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2481060SN/A} 2491060SN/A 2501061SN/Atemplate <class Impl> 2511060SN/Avoid 2529427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2531060SN/A{ 2549444SAndreas.Sandberg@ARM.com resetStage(); 2559444SAndreas.Sandberg@ARM.com} 2569444SAndreas.Sandberg@ARM.com 2579444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2589444SAndreas.Sandberg@ARM.comvoid 25913641Sqtt2@cornell.eduDefaultRename<Impl>::clearStates(ThreadID tid) 26013641Sqtt2@cornell.edu{ 26113641Sqtt2@cornell.edu renameStatus[tid] = Idle; 26213641Sqtt2@cornell.edu 26313641Sqtt2@cornell.edu freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 26413641Sqtt2@cornell.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 26513641Sqtt2@cornell.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 26613641Sqtt2@cornell.edu freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 26713641Sqtt2@cornell.edu emptyROB[tid] = true; 26813641Sqtt2@cornell.edu 26913641Sqtt2@cornell.edu stalls[tid].iew = false; 27013641Sqtt2@cornell.edu serializeInst[tid] = NULL; 27113641Sqtt2@cornell.edu 27213641Sqtt2@cornell.edu instsInProgress[tid] = 0; 27313641Sqtt2@cornell.edu loadsInProgress[tid] = 0; 27413641Sqtt2@cornell.edu storesInProgress[tid] = 0; 27513641Sqtt2@cornell.edu 27613641Sqtt2@cornell.edu serializeOnNextInst[tid] = false; 27713641Sqtt2@cornell.edu} 27813641Sqtt2@cornell.edu 27913641Sqtt2@cornell.edutemplate <class Impl> 28013641Sqtt2@cornell.eduvoid 2819444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2829444SAndreas.Sandberg@ARM.com{ 2839444SAndreas.Sandberg@ARM.com _status = Inactive; 2849444SAndreas.Sandberg@ARM.com 2859444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2869444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2879444SAndreas.Sandberg@ARM.com 2882329SN/A // Grab the number of free entries directly from the stages. 2896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2909444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2919444SAndreas.Sandberg@ARM.com 2922292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 29310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 29410239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2952292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2962292SN/A emptyROB[tid] = true; 2979444SAndreas.Sandberg@ARM.com 2989444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2999444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 3009444SAndreas.Sandberg@ARM.com 3019444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 30210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 30310239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 3049444SAndreas.Sandberg@ARM.com 3059444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 3062292SN/A } 3071060SN/A} 3081060SN/A 3092292SN/Atemplate<class Impl> 3102292SN/Avoid 3116221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3122292SN/A{ 3132292SN/A activeThreads = at_ptr; 3142292SN/A} 3152292SN/A 3162292SN/A 3171061SN/Atemplate <class Impl> 3181060SN/Avoid 3192292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 3201060SN/A{ 3216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3226221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3231060SN/A} 3241060SN/A 3251061SN/Atemplate <class Impl> 3261060SN/Avoid 3272292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 3281060SN/A{ 3292292SN/A freeList = fl_ptr; 3302292SN/A} 3311060SN/A 3322292SN/Atemplate<class Impl> 3332292SN/Avoid 3342292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 3352292SN/A{ 3362292SN/A scoreboard = _scoreboard; 3371060SN/A} 3381060SN/A 3391061SN/Atemplate <class Impl> 3402863Sktlim@umich.edubool 3419444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3421060SN/A{ 3439444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3449444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3459444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3469444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 34711650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 34811650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3499444SAndreas.Sandberg@ARM.com return false; 3509444SAndreas.Sandberg@ARM.com } 3512863Sktlim@umich.edu return true; 3522316SN/A} 3531060SN/A 3542316SN/Atemplate <class Impl> 3552316SN/Avoid 3562307SN/ADefaultRename<Impl>::takeOverFrom() 3571060SN/A{ 3589444SAndreas.Sandberg@ARM.com resetStage(); 3599444SAndreas.Sandberg@ARM.com} 3601060SN/A 3619444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3629444SAndreas.Sandberg@ARM.comvoid 3639444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3649444SAndreas.Sandberg@ARM.com{ 3656221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3669444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3679444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3689444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3699444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3702307SN/A } 3712307SN/A} 3722307SN/A 3732307SN/Atemplate <class Impl> 3742307SN/Avoid 3756221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3761858SN/A{ 3772292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3781858SN/A 3792292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3802292SN/A // If it still needs to block, the blocking should happen the next 3812292SN/A // cycle and there should be space to hold everything due to the squash. 3822292SN/A if (renameStatus[tid] == Blocked || 3833788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3842292SN/A toDecode->renameUnblock[tid] = 1; 3852698Sktlim@umich.edu 3863788Sgblack@eecs.umich.edu resumeSerialize = false; 3872301SN/A serializeInst[tid] = NULL; 3883788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3893788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3903788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3913788Sgblack@eecs.umich.edu resumeSerialize = true; 3923788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3933788Sgblack@eecs.umich.edu } else { 3943788Sgblack@eecs.umich.edu resumeSerialize = false; 3953788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3963788Sgblack@eecs.umich.edu 3973788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3983788Sgblack@eecs.umich.edu } 3992292SN/A } 4002292SN/A 4012292SN/A // Set the status to Squashing. 4022292SN/A renameStatus[tid] = Squashing; 4032292SN/A 4042329SN/A // Squash any instructions from decode. 4052292SN/A for (int i=0; i<fromDecode->size; i++) { 4062935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 4072935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 4082731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 4092292SN/A wroteToTimeBuffer = true; 4102292SN/A } 4112935Sksewell@umich.edu 4122292SN/A } 4132292SN/A 4142935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 4154632Sgblack@eecs.umich.edu // insts in them. 4163093Sksewell@umich.edu insts[tid].clear(); 4172292SN/A 4182292SN/A // Clear the skid buffer in case it has any data in it. 4193093Sksewell@umich.edu skidBuffer[tid].clear(); 4204632Sgblack@eecs.umich.edu 4212935Sksewell@umich.edu doSquash(squash_seq_num, tid); 4222292SN/A} 4232292SN/A 4242292SN/Atemplate <class Impl> 4252292SN/Avoid 4262292SN/ADefaultRename<Impl>::tick() 4272292SN/A{ 4282292SN/A wroteToTimeBuffer = false; 4292292SN/A 4302292SN/A blockThisCycle = false; 4312292SN/A 4322292SN/A bool status_change = false; 4332292SN/A 4342292SN/A toIEWIndex = 0; 4352292SN/A 4362292SN/A sortInsts(); 4372292SN/A 4386221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4396221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4402292SN/A 4412292SN/A // Check stall and squash signals. 4423867Sbinkertn@umich.edu while (threads != end) { 4436221Snate@binkert.org ThreadID tid = *threads++; 4442292SN/A 4452292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4462292SN/A 4472292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4482292SN/A 4492292SN/A rename(status_change, tid); 4502292SN/A } 4512292SN/A 4522292SN/A if (status_change) { 4532292SN/A updateStatus(); 4542292SN/A } 4552292SN/A 4562292SN/A if (wroteToTimeBuffer) { 4572292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4582292SN/A cpu->activityThisCycle(); 4592292SN/A } 4602292SN/A 4613867Sbinkertn@umich.edu threads = activeThreads->begin(); 4622292SN/A 4633867Sbinkertn@umich.edu while (threads != end) { 4646221Snate@binkert.org ThreadID tid = *threads++; 4652292SN/A 4662292SN/A // If we committed this cycle then doneSeqNum will be > 0 4672292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4682292SN/A !fromCommit->commitInfo[tid].squash && 4692292SN/A renameStatus[tid] != Squashing) { 4702292SN/A 4712292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4722292SN/A tid); 4732292SN/A } 4742292SN/A } 4752292SN/A 4762292SN/A // @todo: make into updateProgress function 4776221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4782292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 47910239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 48010239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 48110239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 48210239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4832292SN/A assert(instsInProgress[tid] >=0); 4842292SN/A } 4852292SN/A 4862292SN/A} 4872292SN/A 4882292SN/Atemplate<class Impl> 4892292SN/Avoid 4906221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4912292SN/A{ 4922292SN/A // If status is Running or idle, 4932292SN/A // call renameInsts() 4942292SN/A // If status is Unblocking, 4952292SN/A // buffer any instructions coming from decode 4962292SN/A // continue trying to empty skid buffer 4972292SN/A // check if stall conditions have passed 4982292SN/A 4992292SN/A if (renameStatus[tid] == Blocked) { 5002292SN/A ++renameBlockCycles; 5012292SN/A } else if (renameStatus[tid] == Squashing) { 5022292SN/A ++renameSquashCycles; 5032301SN/A } else if (renameStatus[tid] == SerializeStall) { 5042301SN/A ++renameSerializeStallCycles; 5053788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 5063788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 5073788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 5083788Sgblack@eecs.umich.edu if (resumeSerialize) { 5093788Sgblack@eecs.umich.edu resumeSerialize = false; 5103788Sgblack@eecs.umich.edu block(tid); 5113788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5123788Sgblack@eecs.umich.edu } 5133798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 5143798Sgblack@eecs.umich.edu if (resumeUnblocking) { 5153798Sgblack@eecs.umich.edu block(tid); 5163798Sgblack@eecs.umich.edu resumeUnblocking = false; 5173798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 5183798Sgblack@eecs.umich.edu } 5192292SN/A } 5202292SN/A 5212292SN/A if (renameStatus[tid] == Running || 5222292SN/A renameStatus[tid] == Idle) { 5232292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 5242292SN/A "stage.\n", tid); 5252292SN/A 5262292SN/A renameInsts(tid); 5272292SN/A } else if (renameStatus[tid] == Unblocking) { 5282292SN/A renameInsts(tid); 5292292SN/A 5302292SN/A if (validInsts()) { 5312292SN/A // Add the current inputs to the skid buffer so they can be 5322292SN/A // reprocessed when this stage unblocks. 5332292SN/A skidInsert(tid); 5342292SN/A } 5352292SN/A 5362292SN/A // If we switched over to blocking, then there's a potential for 5372292SN/A // an overall status change. 5382292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5391858SN/A } 5401858SN/A} 5411858SN/A 5421858SN/Atemplate <class Impl> 5431858SN/Avoid 5446221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5451858SN/A{ 5462292SN/A // Instructions can be either in the skid buffer or the queue of 5472292SN/A // instructions coming from decode, depending on the status. 5482292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5492292SN/A skidBuffer[tid].size() : insts[tid].size(); 5501858SN/A 5512292SN/A // Check the decode queue to see if instructions are available. 5522292SN/A // If there are no available instructions to rename, then do nothing. 5532292SN/A if (insts_available == 0) { 5542292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5552292SN/A tid); 5562292SN/A // Should I change status to idle? 5572292SN/A ++renameIdleCycles; 5582292SN/A return; 5592292SN/A } else if (renameStatus[tid] == Unblocking) { 5602292SN/A ++renameUnblockCycles; 5612292SN/A } else if (renameStatus[tid] == Running) { 5622292SN/A ++renameRunCycles; 5632292SN/A } 5641858SN/A 5652292SN/A // Will have to do a different calculation for the number of free 5662292SN/A // entries. 5672292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5682292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5692292SN/A int min_free_entries = free_rob_entries; 5702292SN/A 5712292SN/A FullSource source = ROB; 5722292SN/A 5732292SN/A if (free_iq_entries < min_free_entries) { 5742292SN/A min_free_entries = free_iq_entries; 5752292SN/A source = IQ; 5762292SN/A } 5772292SN/A 5782292SN/A // Check if there's any space left. 5792292SN/A if (min_free_entries <= 0) { 58010239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5812292SN/A "entries.\n" 5822292SN/A "ROB has %i free entries.\n" 58310239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5842292SN/A tid, 5852292SN/A free_rob_entries, 58610239Sbinhpham@cs.rutgers.edu free_iq_entries); 5872292SN/A 5882292SN/A blockThisCycle = true; 5892292SN/A 5902292SN/A block(tid); 5912292SN/A 5922292SN/A incrFullStat(source); 5932292SN/A 5942292SN/A return; 5952292SN/A } else if (min_free_entries < insts_available) { 5962292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5972292SN/A "%i insts available, but only %i insts can be " 5982292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5992292SN/A tid, insts_available, min_free_entries); 6002292SN/A 6012292SN/A insts_available = min_free_entries; 6022292SN/A 6032292SN/A blockThisCycle = true; 6042292SN/A 6052292SN/A incrFullStat(source); 6062292SN/A } 6072292SN/A 6082292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 6092292SN/A skidBuffer[tid] : insts[tid]; 6102292SN/A 6112292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 6122292SN/A "send iew.\n", tid, insts_available); 6132292SN/A 6142292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 6152292SN/A "dispatched to IQ last cycle.\n", 6162292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 6172292SN/A 6182292SN/A // Handle serializing the next instruction if necessary. 6192292SN/A if (serializeOnNextInst[tid]) { 6202292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 6212292SN/A // ROB already empty; no need to serialize. 6222292SN/A serializeOnNextInst[tid] = false; 6232292SN/A } else if (!insts_to_rename.empty()) { 6242292SN/A insts_to_rename.front()->setSerializeBefore(); 6252292SN/A } 6262292SN/A } 6272292SN/A 6282292SN/A int renamed_insts = 0; 6292292SN/A 6302292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6312292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6322292SN/A 6332292SN/A assert(!insts_to_rename.empty()); 6342292SN/A 63513429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = insts_to_rename.front(); 6362292SN/A 63710239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 63810239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 63910239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 64010239Sbinhpham@cs.rutgers.edu 64110239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 64210933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 64310933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 64410933Snilay@cs.wisc.edu source = LQ; 64510933Snilay@cs.wisc.edu incrFullStat(source); 64610933Snilay@cs.wisc.edu break; 64710933Snilay@cs.wisc.edu } 64810239Sbinhpham@cs.rutgers.edu } 64910239Sbinhpham@cs.rutgers.edu 65013652Sqtt2@cornell.edu if (inst->isStore() || inst->isAtomic()) { 65110933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 65210933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 65310933Snilay@cs.wisc.edu source = SQ; 65410933Snilay@cs.wisc.edu incrFullStat(source); 65510933Snilay@cs.wisc.edu break; 65610933Snilay@cs.wisc.edu } 65710239Sbinhpham@cs.rutgers.edu } 65810239Sbinhpham@cs.rutgers.edu 6592292SN/A insts_to_rename.pop_front(); 6602292SN/A 6612292SN/A if (renameStatus[tid] == Unblocking) { 6627720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6637720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6642292SN/A } 6652292SN/A 6662292SN/A if (inst->isSquashed()) { 6677720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6687720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6697720Sgblack@eecs.umich.edu inst->pcState()); 6702292SN/A 6712292SN/A ++renameSquashedInsts; 6722292SN/A 6732292SN/A // Decrement how many instructions are available. 6742292SN/A --insts_available; 6752292SN/A 6762292SN/A continue; 6772292SN/A } 6782292SN/A 6792292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6807720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6812292SN/A 6829531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6839531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 68410715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 68510715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 68612109SRekai.GonzalezAlberquilla@arm.com inst->numVecDestRegs(), 68712109SRekai.GonzalezAlberquilla@arm.com inst->numVecElemDestRegs(), 68813610Sgiacomo.gabrielli@arm.com inst->numVecPredDestRegs(), 68910935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 6909531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6919531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6929531Sgeoffrey.blake@arm.com blockThisCycle = true; 6939531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6949531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6959531Sgeoffrey.blake@arm.com 6969531Sgeoffrey.blake@arm.com break; 6979531Sgeoffrey.blake@arm.com } 6989531Sgeoffrey.blake@arm.com 6992292SN/A // Handle serializeAfter/serializeBefore instructions. 7002292SN/A // serializeAfter marks the next instruction as serializeBefore. 7012292SN/A // serializeBefore makes the instruction wait in rename until the ROB 7022292SN/A // is empty. 7032336SN/A 7042336SN/A // In this model, IPR accesses are serialize before 7052336SN/A // instructions, and store conditionals are serialize after 7062336SN/A // instructions. This is mainly due to lack of support for 7072336SN/A // out-of-order operations of either of those classes of 7082336SN/A // instructions. 7092336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 7102336SN/A !inst->isSerializeHandled()) { 7112292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 7122292SN/A 7132301SN/A if (!inst->isTempSerializeBefore()) { 7142301SN/A renamedSerializing++; 7152292SN/A inst->setSerializeHandled(); 7162301SN/A } else { 7172301SN/A renamedTempSerializing++; 7182301SN/A } 7192292SN/A 7202301SN/A // Change status over to SerializeStall so that other stages know 7212292SN/A // what this is blocked on. 7222301SN/A renameStatus[tid] = SerializeStall; 7232292SN/A 7242301SN/A serializeInst[tid] = inst; 7252292SN/A 7262292SN/A blockThisCycle = true; 7272292SN/A 7282292SN/A break; 7292336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 7302336SN/A !inst->isSerializeHandled()) { 7312292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 7322292SN/A 7332307SN/A renamedSerializing++; 7342307SN/A 7352292SN/A inst->setSerializeHandled(); 7362292SN/A 7372292SN/A serializeAfter(insts_to_rename, tid); 7382292SN/A } 7392292SN/A 7402292SN/A renameSrcRegs(inst, inst->threadNumber); 7412292SN/A 7422292SN/A renameDestRegs(inst, inst->threadNumber); 7432292SN/A 74413652Sqtt2@cornell.edu if (inst->isAtomic() || inst->isStore()) { 74513652Sqtt2@cornell.edu storesInProgress[tid]++; 74613652Sqtt2@cornell.edu } else if (inst->isLoad()) { 74713652Sqtt2@cornell.edu loadsInProgress[tid]++; 74810239Sbinhpham@cs.rutgers.edu } 74913652Sqtt2@cornell.edu 7502292SN/A ++renamed_insts; 75111246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 75211246Sradhika.jagtap@ARM.com // this instruction have been renamed. 75311246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7548471SGiacomo.Gabrielli@arm.com 7552292SN/A // Put instruction in rename queue. 7562292SN/A toIEW->insts[toIEWIndex] = inst; 7572292SN/A ++(toIEW->size); 7582292SN/A 7592292SN/A // Increment which instruction we're on. 7602292SN/A ++toIEWIndex; 7612292SN/A 7622292SN/A // Decrement how many instructions are available. 7632292SN/A --insts_available; 7642292SN/A } 7652292SN/A 7662292SN/A instsInProgress[tid] += renamed_insts; 7672307SN/A renameRenamedInsts += renamed_insts; 7682292SN/A 7692292SN/A // If we wrote to the time buffer, record this. 7702292SN/A if (toIEWIndex) { 7712292SN/A wroteToTimeBuffer = true; 7722292SN/A } 7732292SN/A 7742292SN/A // Check if there's any instructions left that haven't yet been renamed. 7752292SN/A // If so then block. 7762292SN/A if (insts_available) { 7772292SN/A blockThisCycle = true; 7782292SN/A } 7792292SN/A 7802292SN/A if (blockThisCycle) { 7812292SN/A block(tid); 7822292SN/A toDecode->renameUnblock[tid] = false; 7832292SN/A } 7842292SN/A} 7852292SN/A 7862292SN/Atemplate<class Impl> 7872292SN/Avoid 7886221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7892292SN/A{ 7902292SN/A DynInstPtr inst = NULL; 7912292SN/A 7922292SN/A while (!insts[tid].empty()) { 7932292SN/A inst = insts[tid].front(); 7942292SN/A 7952292SN/A insts[tid].pop_front(); 7962292SN/A 7972292SN/A assert(tid == inst->threadNumber); 7982292SN/A 7997720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 8007720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 8012292SN/A 8022307SN/A ++renameSkidInsts; 8032307SN/A 8042292SN/A skidBuffer[tid].push_back(inst); 8052292SN/A } 8062292SN/A 8072292SN/A if (skidBuffer[tid].size() > skidBufferMax) 8083798Sgblack@eecs.umich.edu { 8093798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 8103798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 81111321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 8123798Sgblack@eecs.umich.edu { 8133798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 8147720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 8153798Sgblack@eecs.umich.edu (*it)->seqNum); 8163798Sgblack@eecs.umich.edu } 8172292SN/A panic("Skidbuffer Exceeded Max Size"); 8183798Sgblack@eecs.umich.edu } 8192292SN/A} 8202292SN/A 8212292SN/Atemplate <class Impl> 8222292SN/Avoid 8232292SN/ADefaultRename<Impl>::sortInsts() 8242292SN/A{ 8252292SN/A int insts_from_decode = fromDecode->size; 8262292SN/A for (int i = 0; i < insts_from_decode; ++i) { 82713429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromDecode->insts[i]; 8282292SN/A insts[inst->threadNumber].push_back(inst); 8299527SMatt.Horsnell@arm.com#if TRACING_ON 8309527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 8319527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 8329527SMatt.Horsnell@arm.com } 8339527SMatt.Horsnell@arm.com#endif 8342292SN/A } 8352292SN/A} 8362292SN/A 8372292SN/Atemplate<class Impl> 8382292SN/Abool 8392292SN/ADefaultRename<Impl>::skidsEmpty() 8402292SN/A{ 8416221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8426221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8432292SN/A 8443867Sbinkertn@umich.edu while (threads != end) { 8456221Snate@binkert.org ThreadID tid = *threads++; 8463867Sbinkertn@umich.edu 8473867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8482292SN/A return false; 8492292SN/A } 8502292SN/A 8512292SN/A return true; 8522292SN/A} 8532292SN/A 8542292SN/Atemplate<class Impl> 8552292SN/Avoid 8562292SN/ADefaultRename<Impl>::updateStatus() 8572292SN/A{ 8582292SN/A bool any_unblocking = false; 8592292SN/A 8606221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8616221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8622292SN/A 8633867Sbinkertn@umich.edu while (threads != end) { 8646221Snate@binkert.org ThreadID tid = *threads++; 8652292SN/A 8662292SN/A if (renameStatus[tid] == Unblocking) { 8672292SN/A any_unblocking = true; 8682292SN/A break; 8692292SN/A } 8702292SN/A } 8712292SN/A 8722292SN/A // Rename will have activity if it's unblocking. 8732292SN/A if (any_unblocking) { 8742292SN/A if (_status == Inactive) { 8752292SN/A _status = Active; 8762292SN/A 8772292SN/A DPRINTF(Activity, "Activating stage.\n"); 8782292SN/A 8792733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8802292SN/A } 8812292SN/A } else { 8822292SN/A // If it's not unblocking, then rename will not have any internal 8832292SN/A // activity. Switch it to inactive. 8842292SN/A if (_status == Active) { 8852292SN/A _status = Inactive; 8862292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8872292SN/A 8882733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8892292SN/A } 8902292SN/A } 8912292SN/A} 8922292SN/A 8932292SN/Atemplate <class Impl> 8942292SN/Abool 8956221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8962292SN/A{ 8972292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8982292SN/A 8992292SN/A // Add the current inputs onto the skid buffer, so they can be 9002292SN/A // reprocessed when this stage unblocks. 9012292SN/A skidInsert(tid); 9022292SN/A 9032292SN/A // Only signal backwards to block if the previous stages do not think 9042292SN/A // rename is already blocked. 9052292SN/A if (renameStatus[tid] != Blocked) { 9063798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 9073798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 9083798Sgblack@eecs.umich.edu // stages to block. 9093798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 9102292SN/A toDecode->renameBlock[tid] = true; 9112292SN/A toDecode->renameUnblock[tid] = false; 9122292SN/A wroteToTimeBuffer = true; 9132292SN/A } 9142292SN/A 9152329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 9162329SN/A // it would not know to complete the serialize stall. 9172301SN/A if (renameStatus[tid] != SerializeStall) { 9182292SN/A // Set status to Blocked. 9192292SN/A renameStatus[tid] = Blocked; 9202292SN/A return true; 9212292SN/A } 9222292SN/A } 9232292SN/A 9242292SN/A return false; 9252292SN/A} 9262292SN/A 9272292SN/Atemplate <class Impl> 9282292SN/Abool 9296221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 9302292SN/A{ 9312292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 9322292SN/A 9332292SN/A // Rename is done unblocking if the skid buffer is empty. 9342301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 9352292SN/A 9362292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 9372292SN/A 9382292SN/A toDecode->renameUnblock[tid] = true; 9392292SN/A wroteToTimeBuffer = true; 9402292SN/A 9412292SN/A renameStatus[tid] = Running; 9422292SN/A return true; 9432292SN/A } 9442292SN/A 9452292SN/A return false; 9462292SN/A} 9472292SN/A 9482292SN/Atemplate <class Impl> 9492292SN/Avoid 9506221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9512292SN/A{ 9522980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9532980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9542292SN/A 9551060SN/A // After a syscall squashes everything, the history buffer may be empty 9561060SN/A // but the ROB may still be squashing instructions. 9571060SN/A // Go through the most recent instructions, undoing the mappings 9581060SN/A // they did and freeing up the registers. 9592292SN/A while (!historyBuffer[tid].empty() && 9609919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9612292SN/A assert(hb_it != historyBuffer[tid].end()); 9621062SN/A 9632292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9649919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9651060SN/A 9669919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9679919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9689919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9699919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9709919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9719919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9729919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9739919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9749919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9759919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9761060SN/A 9779919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9789919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9799919Ssteve.reinhardt@amd.com } 9801062SN/A 98111246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 98211246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 98311246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 98411246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 98511246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 98611246Sradhika.jagtap@ARM.com 9872292SN/A historyBuffer[tid].erase(hb_it++); 9881061SN/A 9891062SN/A ++renameUndoneMaps; 9901060SN/A } 99113601Sgiacomo.travaglini@arm.com 99213601Sgiacomo.travaglini@arm.com // Check if we need to change vector renaming mode after squashing 99313601Sgiacomo.travaglini@arm.com cpu->switchRenameMode(tid, freeList); 9941060SN/A} 9951060SN/A 9961060SN/Atemplate<class Impl> 9971060SN/Avoid 9986221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9991060SN/A{ 10002292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 10012292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 10022292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 10032292SN/A 10042980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 10052980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 10061060SN/A 10071061SN/A --hb_it; 10081060SN/A 10092292SN/A if (historyBuffer[tid].empty()) { 10102292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 10112292SN/A return; 10122292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 10132292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 10142292SN/A "that a syscall happened recently.\n", tid); 10151060SN/A return; 10161060SN/A } 10171060SN/A 10182292SN/A // Commit all the renames up until (and including) the committed sequence 10192292SN/A // number. Some or even all of the committed instructions may not have 10202292SN/A // rename histories if they did not have destination registers that were 10212292SN/A // renamed. 10222292SN/A while (!historyBuffer[tid].empty() && 10232292SN/A hb_it != historyBuffer[tid].end() && 10249919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 10251060SN/A 102612105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 10272329SN/A "[sn:%lli].\n", 102812106SRekai.GonzalezAlberquilla@arm.com tid, hb_it->prevPhysReg->index(), 102912106SRekai.GonzalezAlberquilla@arm.com hb_it->prevPhysReg->className(), 103012105Snathanael.premillieu@arm.com hb_it->instSeqNum); 10311061SN/A 10329919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 10339919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 10349919Ssteve.reinhardt@amd.com // the old one. 10359919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 10369919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 10379919Ssteve.reinhardt@amd.com } 10389919Ssteve.reinhardt@amd.com 10392292SN/A ++renameCommittedMaps; 10401061SN/A 10412292SN/A historyBuffer[tid].erase(hb_it--); 10421060SN/A } 10431060SN/A} 10441060SN/A 10451061SN/Atemplate <class Impl> 10461061SN/Ainline void 104713429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 10481061SN/A{ 10499919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10509919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10511061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10521061SN/A 10531061SN/A // Get the architectual register numbers from the source and 10549919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10552292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 105612106SRekai.GonzalezAlberquilla@arm.com const RegId& src_reg = inst->srcRegIdx(src_idx); 105712105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 10589919Ssteve.reinhardt@amd.com 105912106SRekai.GonzalezAlberquilla@arm.com renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 106012106SRekai.GonzalezAlberquilla@arm.com switch (src_reg.classValue()) { 10619913Ssteve.reinhardt@amd.com case IntRegClass: 10629919Ssteve.reinhardt@amd.com intRenameLookups++; 10639913Ssteve.reinhardt@amd.com break; 10649913Ssteve.reinhardt@amd.com case FloatRegClass: 10659919Ssteve.reinhardt@amd.com fpRenameLookups++; 10669913Ssteve.reinhardt@amd.com break; 106712144Srekai.gonzalezalberquilla@arm.com case VecRegClass: 106813598Sgiacomo.travaglini@arm.com case VecElemClass: 106912144Srekai.gonzalezalberquilla@arm.com vecRenameLookups++; 107012144Srekai.gonzalezalberquilla@arm.com break; 107113610Sgiacomo.gabrielli@arm.com case VecPredRegClass: 107213610Sgiacomo.gabrielli@arm.com vecPredRenameLookups++; 107313610Sgiacomo.gabrielli@arm.com break; 10749920Syasuko.eckert@amd.com case CCRegClass: 10759913Ssteve.reinhardt@amd.com case MiscRegClass: 10769913Ssteve.reinhardt@amd.com break; 10779913Ssteve.reinhardt@amd.com 10789913Ssteve.reinhardt@amd.com default: 107912106SRekai.GonzalezAlberquilla@arm.com panic("Invalid register class: %d.", src_reg.classValue()); 10803773Sgblack@eecs.umich.edu } 10814352Sgblack@eecs.umich.edu 108212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 108312106SRekai.GonzalezAlberquilla@arm.com ", got phys reg %i (%s)\n", tid, 108412106SRekai.GonzalezAlberquilla@arm.com src_reg.className(), src_reg.index(), 108512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->index(), 108612106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10871061SN/A 10881061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10891061SN/A 10902292SN/A // See if the register is ready or not. 10919919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 109212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 109312106SRekai.GonzalezAlberquilla@arm.com " is ready.\n", tid, renamed_reg->index(), 109412106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 109512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10961061SN/A 10971061SN/A inst->markSrcRegReady(src_idx); 10984636Sgblack@eecs.umich.edu } else { 109912105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 110012106SRekai.GonzalezAlberquilla@arm.com " is not ready.\n", tid, renamed_reg->index(), 110112106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 110212106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 11031061SN/A } 11041062SN/A 11051062SN/A ++renameRenameLookups; 11061061SN/A } 11071061SN/A} 11081061SN/A 11091061SN/Atemplate <class Impl> 11101061SN/Ainline void 111113429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 11121061SN/A{ 11139919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 11149919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 11151061SN/A unsigned num_dest_regs = inst->numDestRegs(); 11161061SN/A 11172292SN/A // Rename the destination registers. 11182292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 111912106SRekai.GonzalezAlberquilla@arm.com const RegId& dest_reg = inst->destRegIdx(dest_idx); 11209919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 11219919Ssteve.reinhardt@amd.com 112212106SRekai.GonzalezAlberquilla@arm.com RegId flat_dest_regid = tc->flattenRegId(dest_reg); 11239913Ssteve.reinhardt@amd.com 112412106SRekai.GonzalezAlberquilla@arm.com rename_result = map->rename(flat_dest_regid); 11259913Ssteve.reinhardt@amd.com 112612106SRekai.GonzalezAlberquilla@arm.com inst->flattenDestReg(dest_idx, flat_dest_regid); 11271061SN/A 11289919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 11299916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11301062SN/A 113112105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 113212106SRekai.GonzalezAlberquilla@arm.com "reg %i (%i).\n", tid, dest_reg.index(), 113312106SRekai.GonzalezAlberquilla@arm.com dest_reg.className(), 113412106SRekai.GonzalezAlberquilla@arm.com rename_result.first->index(), 113512106SRekai.GonzalezAlberquilla@arm.com rename_result.first->flatIndex()); 11361062SN/A 11372292SN/A // Record the rename information so that a history can be kept. 113812106SRekai.GonzalezAlberquilla@arm.com RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 11392292SN/A rename_result.first, 11402292SN/A rename_result.second); 11411062SN/A 11422292SN/A historyBuffer[tid].push_front(hb_entry); 11431062SN/A 11442935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11452935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11462935Sksewell@umich.edu historyBuffer[tid].size(), 11472292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11481062SN/A 11492292SN/A // Tell the instruction to rename the appropriate destination 11502292SN/A // register (dest_idx) to the new physical register 11512292SN/A // (rename_result.first), and record the previous physical 11522292SN/A // register that the same logical register was renamed to 11532292SN/A // (rename_result.second). 11542292SN/A inst->renameDestReg(dest_idx, 11552292SN/A rename_result.first, 11562292SN/A rename_result.second); 11571062SN/A 11582292SN/A ++renameRenamedOperands; 11591061SN/A } 11601061SN/A} 11611061SN/A 11621061SN/Atemplate <class Impl> 11631061SN/Ainline int 11646221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11651061SN/A{ 11662292SN/A int num_free = freeEntries[tid].robEntries - 11672292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11682292SN/A 11692292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11702292SN/A 11712292SN/A return num_free; 11721061SN/A} 11731061SN/A 11741061SN/Atemplate <class Impl> 11751061SN/Ainline int 11766221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11771061SN/A{ 11782292SN/A int num_free = freeEntries[tid].iqEntries - 11792292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11802292SN/A 11812292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11822292SN/A 11832292SN/A return num_free; 11842292SN/A} 11852292SN/A 11862292SN/Atemplate <class Impl> 11872292SN/Ainline int 118810239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11892292SN/A{ 119010239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 119110935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 119210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 119310239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 119410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 119510239Sbinhpham@cs.rutgers.edu return num_free; 119610239Sbinhpham@cs.rutgers.edu} 11972292SN/A 119810239Sbinhpham@cs.rutgers.edutemplate <class Impl> 119910239Sbinhpham@cs.rutgers.eduinline int 120010239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 120110239Sbinhpham@cs.rutgers.edu{ 120210239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 120310935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 120410239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 120510239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 120610239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 120710239Sbinhpham@cs.rutgers.edu return num_free; 12082292SN/A} 12092292SN/A 12102292SN/Atemplate <class Impl> 12112292SN/Aunsigned 12122292SN/ADefaultRename<Impl>::validInsts() 12132292SN/A{ 12142292SN/A unsigned inst_count = 0; 12152292SN/A 12162292SN/A for (int i=0; i<fromDecode->size; i++) { 12172731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 12182292SN/A inst_count++; 12192292SN/A } 12202292SN/A 12212292SN/A return inst_count; 12222292SN/A} 12232292SN/A 12242292SN/Atemplate <class Impl> 12252292SN/Avoid 12266221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 12272292SN/A{ 12282292SN/A if (fromIEW->iewBlock[tid]) { 12292292SN/A stalls[tid].iew = true; 12302292SN/A } 12312292SN/A 12322292SN/A if (fromIEW->iewUnblock[tid]) { 12332292SN/A assert(stalls[tid].iew); 12342292SN/A stalls[tid].iew = false; 12352292SN/A } 12362292SN/A} 12372292SN/A 12382292SN/Atemplate <class Impl> 12392292SN/Abool 12406221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12412292SN/A{ 12422292SN/A bool ret_val = false; 12432292SN/A 12442292SN/A if (stalls[tid].iew) { 12452292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12462292SN/A ret_val = true; 12472292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12482292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12492292SN/A ret_val = true; 12502292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12512292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12522292SN/A ret_val = true; 125310239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12542292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12552292SN/A ret_val = true; 12562292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12572292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12582292SN/A ret_val = true; 12592301SN/A } else if (renameStatus[tid] == SerializeStall && 12602292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12612301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12622292SN/A "empty.\n", 12632292SN/A tid); 12642292SN/A ret_val = true; 12652292SN/A } 12662292SN/A 12672292SN/A return ret_val; 12682292SN/A} 12692292SN/A 12702292SN/Atemplate <class Impl> 12712292SN/Avoid 12726221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12732292SN/A{ 12748607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12758607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12762292SN/A 127710239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 127810239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 127910239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 128010239Sbinhpham@cs.rutgers.edu } 12812292SN/A 12822292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12832292SN/A freeEntries[tid].robEntries = 12842292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12852292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12862292SN/A } 12872292SN/A 128810239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 128913610Sgiacomo.gabrielli@arm.com "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n", 12902292SN/A tid, 12912292SN/A freeEntries[tid].iqEntries, 12922292SN/A freeEntries[tid].robEntries, 129310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 129412109SRekai.GonzalezAlberquilla@arm.com freeEntries[tid].sqEntries, 129512109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeEntries(), 129612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeIntEntries(), 129712109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeFloatEntries(), 129812109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeVecEntries(), 129913610Sgiacomo.gabrielli@arm.com renameMap[tid]->numFreePredEntries(), 130012109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeCCEntries()); 13012292SN/A 13022292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 13032292SN/A tid, instsInProgress[tid]); 13042292SN/A} 13052292SN/A 13062292SN/Atemplate <class Impl> 13072292SN/Abool 13086221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 13092292SN/A{ 13102292SN/A // Check if there's a squash signal, squash if there is 13112292SN/A // Check stall signals, block if necessary. 13122292SN/A // If status was blocked 13132292SN/A // check if stall conditions have passed 13142292SN/A // if so then go to unblocking 13152292SN/A // If status was Squashing 13162292SN/A // check if squashing is not high. Switch to running this cycle. 13172301SN/A // If status was serialize stall 13182292SN/A // check if ROB is empty and no insts are in flight to the ROB 13192292SN/A 13202292SN/A readFreeEntries(tid); 13212292SN/A readStallSignals(tid); 13222292SN/A 13232292SN/A if (fromCommit->commitInfo[tid].squash) { 13242292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 13252292SN/A "commit.\n", tid); 13262292SN/A 13274632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 13282292SN/A 13292292SN/A return true; 13302292SN/A } 13312292SN/A 13322292SN/A if (checkStall(tid)) { 13332292SN/A return block(tid); 13342292SN/A } 13352292SN/A 13362292SN/A if (renameStatus[tid] == Blocked) { 13372292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 13382292SN/A tid); 13392292SN/A 13402292SN/A renameStatus[tid] = Unblocking; 13412292SN/A 13422292SN/A unblock(tid); 13432292SN/A 13442292SN/A return true; 13452292SN/A } 13462292SN/A 13472292SN/A if (renameStatus[tid] == Squashing) { 13482292SN/A // Switch status to running if rename isn't being told to block or 13492292SN/A // squash this cycle. 13503798Sgblack@eecs.umich.edu if (resumeSerialize) { 13513798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13523798Sgblack@eecs.umich.edu tid); 13532292SN/A 13543798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13553798Sgblack@eecs.umich.edu return true; 13563798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13573798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13583798Sgblack@eecs.umich.edu tid); 13593798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13603798Sgblack@eecs.umich.edu return true; 13613798Sgblack@eecs.umich.edu } else { 13623788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13633788Sgblack@eecs.umich.edu tid); 13642292SN/A 13653788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13663788Sgblack@eecs.umich.edu return false; 13673788Sgblack@eecs.umich.edu } 13682292SN/A } 13692292SN/A 13702301SN/A if (renameStatus[tid] == SerializeStall) { 13712292SN/A // Stall ends once the ROB is free. 13722301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13732292SN/A "unblocking.\n", tid); 13742292SN/A 13752301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13762292SN/A 13772292SN/A renameStatus[tid] = Unblocking; 13782292SN/A 13792292SN/A unblock(tid); 13802292SN/A 13812292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13827720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13832292SN/A 13842292SN/A // Put instruction into queue here. 13852301SN/A serial_inst->clearSerializeBefore(); 13862292SN/A 13872292SN/A if (!skidBuffer[tid].empty()) { 13882301SN/A skidBuffer[tid].push_front(serial_inst); 13892292SN/A } else { 13902301SN/A insts[tid].push_front(serial_inst); 13912292SN/A } 13922292SN/A 13932292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13942703Sktlim@umich.edu " Adding to front of list.\n", tid); 13952292SN/A 13962301SN/A serializeInst[tid] = NULL; 13972292SN/A 13982292SN/A return true; 13992292SN/A } 14002292SN/A 14012292SN/A // If we've reached this point, we have not gotten any signals that 14022292SN/A // cause rename to change its status. Rename remains the same as before. 14032292SN/A return false; 14041061SN/A} 14051061SN/A 14061060SN/Atemplate<class Impl> 14071060SN/Avoid 14086221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 14091060SN/A{ 14102292SN/A if (inst_list.empty()) { 14112292SN/A // Mark a bit to say that I must serialize on the next instruction. 14122292SN/A serializeOnNextInst[tid] = true; 14131060SN/A return; 14141060SN/A } 14151060SN/A 14162292SN/A // Set the next instruction as serializing. 14172292SN/A inst_list.front()->setSerializeBefore(); 14182292SN/A} 14192292SN/A 14202292SN/Atemplate <class Impl> 14212292SN/Ainline void 14222292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 14232292SN/A{ 14242292SN/A switch (source) { 14252292SN/A case ROB: 14262292SN/A ++renameROBFullEvents; 14272292SN/A break; 14282292SN/A case IQ: 14292292SN/A ++renameIQFullEvents; 14302292SN/A break; 143110239Sbinhpham@cs.rutgers.edu case LQ: 143210239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 143310239Sbinhpham@cs.rutgers.edu break; 143410239Sbinhpham@cs.rutgers.edu case SQ: 143510239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 14362292SN/A break; 14372292SN/A default: 14382292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14392292SN/A break; 14401060SN/A } 14412292SN/A} 14421060SN/A 14432292SN/Atemplate <class Impl> 14442292SN/Avoid 14452292SN/ADefaultRename<Impl>::dumpHistory() 14462292SN/A{ 14472980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14481060SN/A 14496221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14501060SN/A 14516221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14521060SN/A 14536221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 145412105Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 145512105Snathanael.premillieu@arm.com " %i[%s] Old phys reg: %i[%s]\n", 145612105Snathanael.premillieu@arm.com (*buf_it).instSeqNum, 145712106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.className(), 145812106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.index(), 145912106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->index(), 146012106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->className(), 146112106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->index(), 146212106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->className()); 14631060SN/A 14642292SN/A buf_it++; 14651062SN/A } 14661060SN/A } 14671060SN/A} 14689944Smatt.horsnell@ARM.com 14699944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1470