rename_impl.hh revision 13610
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 7012109SRekai.GonzalezAlberquilla@arm.com numThreads(params->numThreads) 711060SN/A{ 7210172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7310172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610172Sdam.sunwoo@arm.com 772292SN/A // @todo: Make into a parameter. 7810328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 7913453Srekai.gonzalezalberquilla@arm.com for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) { 8013453Srekai.gonzalezalberquilla@arm.com renameStatus[tid] = Idle; 8113453Srekai.gonzalezalberquilla@arm.com renameMap[tid] = nullptr; 8213453Srekai.gonzalezalberquilla@arm.com instsInProgress[tid] = 0; 8313453Srekai.gonzalezalberquilla@arm.com loadsInProgress[tid] = 0; 8413453Srekai.gonzalezalberquilla@arm.com storesInProgress[tid] = 0; 8513453Srekai.gonzalezalberquilla@arm.com freeEntries[tid] = {0, 0, 0, 0}; 8613453Srekai.gonzalezalberquilla@arm.com emptyROB[tid] = true; 8713453Srekai.gonzalezalberquilla@arm.com stalls[tid] = {false, false}; 8813453Srekai.gonzalezalberquilla@arm.com serializeInst[tid] = nullptr; 8913453Srekai.gonzalezalberquilla@arm.com serializeOnNextInst[tid] = false; 9013453Srekai.gonzalezalberquilla@arm.com } 912292SN/A} 922292SN/A 932292SN/Atemplate <class Impl> 942292SN/Astd::string 952292SN/ADefaultRename<Impl>::name() const 962292SN/A{ 972292SN/A return cpu->name() + ".rename"; 981060SN/A} 991060SN/A 1001061SN/Atemplate <class Impl> 1011060SN/Avoid 1022292SN/ADefaultRename<Impl>::regStats() 1031062SN/A{ 1041062SN/A renameSquashCycles 1058240Snate@binkert.org .name(name() + ".SquashCycles") 1061062SN/A .desc("Number of cycles rename is squashing") 1071062SN/A .prereq(renameSquashCycles); 1081062SN/A renameIdleCycles 1098240Snate@binkert.org .name(name() + ".IdleCycles") 1101062SN/A .desc("Number of cycles rename is idle") 1111062SN/A .prereq(renameIdleCycles); 1121062SN/A renameBlockCycles 1138240Snate@binkert.org .name(name() + ".BlockCycles") 1141062SN/A .desc("Number of cycles rename is blocking") 1151062SN/A .prereq(renameBlockCycles); 1162301SN/A renameSerializeStallCycles 1178240Snate@binkert.org .name(name() + ".serializeStallCycles") 1182301SN/A .desc("count of cycles rename stalled for serializing inst") 1192301SN/A .flags(Stats::total); 1202292SN/A renameRunCycles 1218240Snate@binkert.org .name(name() + ".RunCycles") 1222292SN/A .desc("Number of cycles rename is running") 1232292SN/A .prereq(renameIdleCycles); 1241062SN/A renameUnblockCycles 1258240Snate@binkert.org .name(name() + ".UnblockCycles") 1261062SN/A .desc("Number of cycles rename is unblocking") 1271062SN/A .prereq(renameUnblockCycles); 1281062SN/A renameRenamedInsts 1298240Snate@binkert.org .name(name() + ".RenamedInsts") 1301062SN/A .desc("Number of instructions processed by rename") 1311062SN/A .prereq(renameRenamedInsts); 1321062SN/A renameSquashedInsts 1338240Snate@binkert.org .name(name() + ".SquashedInsts") 1341062SN/A .desc("Number of squashed instructions processed by rename") 1351062SN/A .prereq(renameSquashedInsts); 1361062SN/A renameROBFullEvents 1378240Snate@binkert.org .name(name() + ".ROBFullEvents") 1382292SN/A .desc("Number of times rename has blocked due to ROB full") 1391062SN/A .prereq(renameROBFullEvents); 1401062SN/A renameIQFullEvents 1418240Snate@binkert.org .name(name() + ".IQFullEvents") 1422292SN/A .desc("Number of times rename has blocked due to IQ full") 1431062SN/A .prereq(renameIQFullEvents); 14410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 14510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 14610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 14710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 14810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 14910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 15010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 15110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1521062SN/A renameFullRegistersEvents 1538240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1541062SN/A .desc("Number of times there has been no free registers") 1551062SN/A .prereq(renameFullRegistersEvents); 1561062SN/A renameRenamedOperands 1578240Snate@binkert.org .name(name() + ".RenamedOperands") 1581062SN/A .desc("Number of destination operands rename has renamed") 1591062SN/A .prereq(renameRenamedOperands); 1601062SN/A renameRenameLookups 1618240Snate@binkert.org .name(name() + ".RenameLookups") 1621062SN/A .desc("Number of register rename lookups that rename has made") 1631062SN/A .prereq(renameRenameLookups); 1641062SN/A renameCommittedMaps 1658240Snate@binkert.org .name(name() + ".CommittedMaps") 1661062SN/A .desc("Number of HB maps that are committed") 1671062SN/A .prereq(renameCommittedMaps); 1681062SN/A renameUndoneMaps 1698240Snate@binkert.org .name(name() + ".UndoneMaps") 1701062SN/A .desc("Number of HB maps that are undone due to squashing") 1711062SN/A .prereq(renameUndoneMaps); 1722301SN/A renamedSerializing 1738240Snate@binkert.org .name(name() + ".serializingInsts") 1742301SN/A .desc("count of serializing insts renamed") 1752301SN/A .flags(Stats::total) 1762301SN/A ; 1772301SN/A renamedTempSerializing 1788240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1792301SN/A .desc("count of temporary serializing insts renamed") 1802301SN/A .flags(Stats::total) 1812301SN/A ; 1822307SN/A renameSkidInsts 1838240Snate@binkert.org .name(name() + ".skidInsts") 1842307SN/A .desc("count of insts added to the skid buffer") 1852307SN/A .flags(Stats::total) 1862307SN/A ; 1877897Shestness@cs.utexas.edu intRenameLookups 1888240Snate@binkert.org .name(name() + ".int_rename_lookups") 1897897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1907897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1917897Shestness@cs.utexas.edu fpRenameLookups 1928240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1937897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1947897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 19512109SRekai.GonzalezAlberquilla@arm.com vecRenameLookups 19612109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_rename_lookups") 19712109SRekai.GonzalezAlberquilla@arm.com .desc("Number of vector rename lookups") 19812109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRenameLookups); 19913610Sgiacomo.gabrielli@arm.com vecPredRenameLookups 20013610Sgiacomo.gabrielli@arm.com .name(name() + ".vec_pred_rename_lookups") 20113610Sgiacomo.gabrielli@arm.com .desc("Number of vector predicate rename lookups") 20213610Sgiacomo.gabrielli@arm.com .prereq(vecPredRenameLookups); 2031062SN/A} 2041062SN/A 2051062SN/Atemplate <class Impl> 2061062SN/Avoid 20711246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 20811246Sradhika.jagtap@ARM.com{ 20911246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 21011246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 21111246Sradhika.jagtap@ARM.com "SquashInRename"); 21211246Sradhika.jagtap@ARM.com} 21311246Sradhika.jagtap@ARM.com 21411246Sradhika.jagtap@ARM.comtemplate <class Impl> 21511246Sradhika.jagtap@ARM.comvoid 2162292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2171060SN/A{ 2181060SN/A timeBuffer = tb_ptr; 2191060SN/A 2201060SN/A // Setup wire to read information from time buffer, from IEW stage. 2211060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2221060SN/A 2231060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2241060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2251060SN/A 2261060SN/A // Setup wire to write information to previous stages. 2271060SN/A toDecode = timeBuffer->getWire(0); 2281060SN/A} 2291060SN/A 2301061SN/Atemplate <class Impl> 2311060SN/Avoid 2322292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2331060SN/A{ 2341060SN/A renameQueue = rq_ptr; 2351060SN/A 2361060SN/A // Setup wire to write information to future stages. 2371060SN/A toIEW = renameQueue->getWire(0); 2381060SN/A} 2391060SN/A 2401061SN/Atemplate <class Impl> 2411060SN/Avoid 2422292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2431060SN/A{ 2441060SN/A decodeQueue = dq_ptr; 2451060SN/A 2461060SN/A // Setup wire to get information from decode. 2471060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2481060SN/A} 2491060SN/A 2501061SN/Atemplate <class Impl> 2511060SN/Avoid 2529427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2531060SN/A{ 2549444SAndreas.Sandberg@ARM.com resetStage(); 2559444SAndreas.Sandberg@ARM.com} 2569444SAndreas.Sandberg@ARM.com 2579444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2589444SAndreas.Sandberg@ARM.comvoid 2599444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2609444SAndreas.Sandberg@ARM.com{ 2619444SAndreas.Sandberg@ARM.com _status = Inactive; 2629444SAndreas.Sandberg@ARM.com 2639444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2649444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2659444SAndreas.Sandberg@ARM.com 2662329SN/A // Grab the number of free entries directly from the stages. 2676221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2689444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2699444SAndreas.Sandberg@ARM.com 2702292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 27110239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 27210239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2732292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2742292SN/A emptyROB[tid] = true; 2759444SAndreas.Sandberg@ARM.com 2769444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2779444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2789444SAndreas.Sandberg@ARM.com 2799444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 28010239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 28110239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 2829444SAndreas.Sandberg@ARM.com 2839444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2842292SN/A } 2851060SN/A} 2861060SN/A 2872292SN/Atemplate<class Impl> 2882292SN/Avoid 2896221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2902292SN/A{ 2912292SN/A activeThreads = at_ptr; 2922292SN/A} 2932292SN/A 2942292SN/A 2951061SN/Atemplate <class Impl> 2961060SN/Avoid 2972292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2981060SN/A{ 2996221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 3006221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 3011060SN/A} 3021060SN/A 3031061SN/Atemplate <class Impl> 3041060SN/Avoid 3052292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 3061060SN/A{ 3072292SN/A freeList = fl_ptr; 3082292SN/A} 3091060SN/A 3102292SN/Atemplate<class Impl> 3112292SN/Avoid 3122292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 3132292SN/A{ 3142292SN/A scoreboard = _scoreboard; 3151060SN/A} 3161060SN/A 3171061SN/Atemplate <class Impl> 3182863Sktlim@umich.edubool 3199444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3201060SN/A{ 3219444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3229444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3239444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3249444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 32511650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 32611650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3279444SAndreas.Sandberg@ARM.com return false; 3289444SAndreas.Sandberg@ARM.com } 3292863Sktlim@umich.edu return true; 3302316SN/A} 3311060SN/A 3322316SN/Atemplate <class Impl> 3332316SN/Avoid 3342307SN/ADefaultRename<Impl>::takeOverFrom() 3351060SN/A{ 3369444SAndreas.Sandberg@ARM.com resetStage(); 3379444SAndreas.Sandberg@ARM.com} 3381060SN/A 3399444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3409444SAndreas.Sandberg@ARM.comvoid 3419444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3429444SAndreas.Sandberg@ARM.com{ 3436221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3449444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3459444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3469444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3479444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3482307SN/A } 3492307SN/A} 3502307SN/A 3512307SN/Atemplate <class Impl> 3522307SN/Avoid 3536221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3541858SN/A{ 3552292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3561858SN/A 3572292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3582292SN/A // If it still needs to block, the blocking should happen the next 3592292SN/A // cycle and there should be space to hold everything due to the squash. 3602292SN/A if (renameStatus[tid] == Blocked || 3613788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3622292SN/A toDecode->renameUnblock[tid] = 1; 3632698Sktlim@umich.edu 3643788Sgblack@eecs.umich.edu resumeSerialize = false; 3652301SN/A serializeInst[tid] = NULL; 3663788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3673788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3683788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3693788Sgblack@eecs.umich.edu resumeSerialize = true; 3703788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3713788Sgblack@eecs.umich.edu } else { 3723788Sgblack@eecs.umich.edu resumeSerialize = false; 3733788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3743788Sgblack@eecs.umich.edu 3753788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3763788Sgblack@eecs.umich.edu } 3772292SN/A } 3782292SN/A 3792292SN/A // Set the status to Squashing. 3802292SN/A renameStatus[tid] = Squashing; 3812292SN/A 3822329SN/A // Squash any instructions from decode. 3832292SN/A for (int i=0; i<fromDecode->size; i++) { 3842935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3852935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3862731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3872292SN/A wroteToTimeBuffer = true; 3882292SN/A } 3892935Sksewell@umich.edu 3902292SN/A } 3912292SN/A 3922935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3934632Sgblack@eecs.umich.edu // insts in them. 3943093Sksewell@umich.edu insts[tid].clear(); 3952292SN/A 3962292SN/A // Clear the skid buffer in case it has any data in it. 3973093Sksewell@umich.edu skidBuffer[tid].clear(); 3984632Sgblack@eecs.umich.edu 3992935Sksewell@umich.edu doSquash(squash_seq_num, tid); 4002292SN/A} 4012292SN/A 4022292SN/Atemplate <class Impl> 4032292SN/Avoid 4042292SN/ADefaultRename<Impl>::tick() 4052292SN/A{ 4062292SN/A wroteToTimeBuffer = false; 4072292SN/A 4082292SN/A blockThisCycle = false; 4092292SN/A 4102292SN/A bool status_change = false; 4112292SN/A 4122292SN/A toIEWIndex = 0; 4132292SN/A 4142292SN/A sortInsts(); 4152292SN/A 4166221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4176221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4182292SN/A 4192292SN/A // Check stall and squash signals. 4203867Sbinkertn@umich.edu while (threads != end) { 4216221Snate@binkert.org ThreadID tid = *threads++; 4222292SN/A 4232292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4242292SN/A 4252292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4262292SN/A 4272292SN/A rename(status_change, tid); 4282292SN/A } 4292292SN/A 4302292SN/A if (status_change) { 4312292SN/A updateStatus(); 4322292SN/A } 4332292SN/A 4342292SN/A if (wroteToTimeBuffer) { 4352292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4362292SN/A cpu->activityThisCycle(); 4372292SN/A } 4382292SN/A 4393867Sbinkertn@umich.edu threads = activeThreads->begin(); 4402292SN/A 4413867Sbinkertn@umich.edu while (threads != end) { 4426221Snate@binkert.org ThreadID tid = *threads++; 4432292SN/A 4442292SN/A // If we committed this cycle then doneSeqNum will be > 0 4452292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4462292SN/A !fromCommit->commitInfo[tid].squash && 4472292SN/A renameStatus[tid] != Squashing) { 4482292SN/A 4492292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4502292SN/A tid); 4512292SN/A } 4522292SN/A } 4532292SN/A 4542292SN/A // @todo: make into updateProgress function 4556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4562292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 45710239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 45810239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 45910239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 46010239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4612292SN/A assert(instsInProgress[tid] >=0); 4622292SN/A } 4632292SN/A 4642292SN/A} 4652292SN/A 4662292SN/Atemplate<class Impl> 4672292SN/Avoid 4686221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4692292SN/A{ 4702292SN/A // If status is Running or idle, 4712292SN/A // call renameInsts() 4722292SN/A // If status is Unblocking, 4732292SN/A // buffer any instructions coming from decode 4742292SN/A // continue trying to empty skid buffer 4752292SN/A // check if stall conditions have passed 4762292SN/A 4772292SN/A if (renameStatus[tid] == Blocked) { 4782292SN/A ++renameBlockCycles; 4792292SN/A } else if (renameStatus[tid] == Squashing) { 4802292SN/A ++renameSquashCycles; 4812301SN/A } else if (renameStatus[tid] == SerializeStall) { 4822301SN/A ++renameSerializeStallCycles; 4833788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4843788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4853788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4863788Sgblack@eecs.umich.edu if (resumeSerialize) { 4873788Sgblack@eecs.umich.edu resumeSerialize = false; 4883788Sgblack@eecs.umich.edu block(tid); 4893788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4903788Sgblack@eecs.umich.edu } 4913798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4923798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4933798Sgblack@eecs.umich.edu block(tid); 4943798Sgblack@eecs.umich.edu resumeUnblocking = false; 4953798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4963798Sgblack@eecs.umich.edu } 4972292SN/A } 4982292SN/A 4992292SN/A if (renameStatus[tid] == Running || 5002292SN/A renameStatus[tid] == Idle) { 5012292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 5022292SN/A "stage.\n", tid); 5032292SN/A 5042292SN/A renameInsts(tid); 5052292SN/A } else if (renameStatus[tid] == Unblocking) { 5062292SN/A renameInsts(tid); 5072292SN/A 5082292SN/A if (validInsts()) { 5092292SN/A // Add the current inputs to the skid buffer so they can be 5102292SN/A // reprocessed when this stage unblocks. 5112292SN/A skidInsert(tid); 5122292SN/A } 5132292SN/A 5142292SN/A // If we switched over to blocking, then there's a potential for 5152292SN/A // an overall status change. 5162292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5171858SN/A } 5181858SN/A} 5191858SN/A 5201858SN/Atemplate <class Impl> 5211858SN/Avoid 5226221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5231858SN/A{ 5242292SN/A // Instructions can be either in the skid buffer or the queue of 5252292SN/A // instructions coming from decode, depending on the status. 5262292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5272292SN/A skidBuffer[tid].size() : insts[tid].size(); 5281858SN/A 5292292SN/A // Check the decode queue to see if instructions are available. 5302292SN/A // If there are no available instructions to rename, then do nothing. 5312292SN/A if (insts_available == 0) { 5322292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5332292SN/A tid); 5342292SN/A // Should I change status to idle? 5352292SN/A ++renameIdleCycles; 5362292SN/A return; 5372292SN/A } else if (renameStatus[tid] == Unblocking) { 5382292SN/A ++renameUnblockCycles; 5392292SN/A } else if (renameStatus[tid] == Running) { 5402292SN/A ++renameRunCycles; 5412292SN/A } 5421858SN/A 5432292SN/A // Will have to do a different calculation for the number of free 5442292SN/A // entries. 5452292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5462292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5472292SN/A int min_free_entries = free_rob_entries; 5482292SN/A 5492292SN/A FullSource source = ROB; 5502292SN/A 5512292SN/A if (free_iq_entries < min_free_entries) { 5522292SN/A min_free_entries = free_iq_entries; 5532292SN/A source = IQ; 5542292SN/A } 5552292SN/A 5562292SN/A // Check if there's any space left. 5572292SN/A if (min_free_entries <= 0) { 55810239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5592292SN/A "entries.\n" 5602292SN/A "ROB has %i free entries.\n" 56110239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5622292SN/A tid, 5632292SN/A free_rob_entries, 56410239Sbinhpham@cs.rutgers.edu free_iq_entries); 5652292SN/A 5662292SN/A blockThisCycle = true; 5672292SN/A 5682292SN/A block(tid); 5692292SN/A 5702292SN/A incrFullStat(source); 5712292SN/A 5722292SN/A return; 5732292SN/A } else if (min_free_entries < insts_available) { 5742292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5752292SN/A "%i insts available, but only %i insts can be " 5762292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5772292SN/A tid, insts_available, min_free_entries); 5782292SN/A 5792292SN/A insts_available = min_free_entries; 5802292SN/A 5812292SN/A blockThisCycle = true; 5822292SN/A 5832292SN/A incrFullStat(source); 5842292SN/A } 5852292SN/A 5862292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5872292SN/A skidBuffer[tid] : insts[tid]; 5882292SN/A 5892292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5902292SN/A "send iew.\n", tid, insts_available); 5912292SN/A 5922292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5932292SN/A "dispatched to IQ last cycle.\n", 5942292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5952292SN/A 5962292SN/A // Handle serializing the next instruction if necessary. 5972292SN/A if (serializeOnNextInst[tid]) { 5982292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5992292SN/A // ROB already empty; no need to serialize. 6002292SN/A serializeOnNextInst[tid] = false; 6012292SN/A } else if (!insts_to_rename.empty()) { 6022292SN/A insts_to_rename.front()->setSerializeBefore(); 6032292SN/A } 6042292SN/A } 6052292SN/A 6062292SN/A int renamed_insts = 0; 6072292SN/A 6082292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 6092292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 6102292SN/A 6112292SN/A assert(!insts_to_rename.empty()); 6122292SN/A 61313429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = insts_to_rename.front(); 6142292SN/A 61510239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 61610239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 61710239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 61810239Sbinhpham@cs.rutgers.edu 61910239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 62010933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 62110933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 62210933Snilay@cs.wisc.edu source = LQ; 62310933Snilay@cs.wisc.edu incrFullStat(source); 62410933Snilay@cs.wisc.edu break; 62510933Snilay@cs.wisc.edu } 62610239Sbinhpham@cs.rutgers.edu } 62710239Sbinhpham@cs.rutgers.edu 62810239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 62910933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 63010933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 63110933Snilay@cs.wisc.edu source = SQ; 63210933Snilay@cs.wisc.edu incrFullStat(source); 63310933Snilay@cs.wisc.edu break; 63410933Snilay@cs.wisc.edu } 63510239Sbinhpham@cs.rutgers.edu } 63610239Sbinhpham@cs.rutgers.edu 6372292SN/A insts_to_rename.pop_front(); 6382292SN/A 6392292SN/A if (renameStatus[tid] == Unblocking) { 6407720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6417720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6422292SN/A } 6432292SN/A 6442292SN/A if (inst->isSquashed()) { 6457720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6467720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6477720Sgblack@eecs.umich.edu inst->pcState()); 6482292SN/A 6492292SN/A ++renameSquashedInsts; 6502292SN/A 6512292SN/A // Decrement how many instructions are available. 6522292SN/A --insts_available; 6532292SN/A 6542292SN/A continue; 6552292SN/A } 6562292SN/A 6572292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6587720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6592292SN/A 6609531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6619531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 66210715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 66310715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 66412109SRekai.GonzalezAlberquilla@arm.com inst->numVecDestRegs(), 66512109SRekai.GonzalezAlberquilla@arm.com inst->numVecElemDestRegs(), 66613610Sgiacomo.gabrielli@arm.com inst->numVecPredDestRegs(), 66710935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 6689531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6699531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6709531Sgeoffrey.blake@arm.com blockThisCycle = true; 6719531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6729531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6739531Sgeoffrey.blake@arm.com 6749531Sgeoffrey.blake@arm.com break; 6759531Sgeoffrey.blake@arm.com } 6769531Sgeoffrey.blake@arm.com 6772292SN/A // Handle serializeAfter/serializeBefore instructions. 6782292SN/A // serializeAfter marks the next instruction as serializeBefore. 6792292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6802292SN/A // is empty. 6812336SN/A 6822336SN/A // In this model, IPR accesses are serialize before 6832336SN/A // instructions, and store conditionals are serialize after 6842336SN/A // instructions. This is mainly due to lack of support for 6852336SN/A // out-of-order operations of either of those classes of 6862336SN/A // instructions. 6872336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6882336SN/A !inst->isSerializeHandled()) { 6892292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6902292SN/A 6912301SN/A if (!inst->isTempSerializeBefore()) { 6922301SN/A renamedSerializing++; 6932292SN/A inst->setSerializeHandled(); 6942301SN/A } else { 6952301SN/A renamedTempSerializing++; 6962301SN/A } 6972292SN/A 6982301SN/A // Change status over to SerializeStall so that other stages know 6992292SN/A // what this is blocked on. 7002301SN/A renameStatus[tid] = SerializeStall; 7012292SN/A 7022301SN/A serializeInst[tid] = inst; 7032292SN/A 7042292SN/A blockThisCycle = true; 7052292SN/A 7062292SN/A break; 7072336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 7082336SN/A !inst->isSerializeHandled()) { 7092292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 7102292SN/A 7112307SN/A renamedSerializing++; 7122307SN/A 7132292SN/A inst->setSerializeHandled(); 7142292SN/A 7152292SN/A serializeAfter(insts_to_rename, tid); 7162292SN/A } 7172292SN/A 7182292SN/A renameSrcRegs(inst, inst->threadNumber); 7192292SN/A 7202292SN/A renameDestRegs(inst, inst->threadNumber); 7212292SN/A 72210239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 72310239Sbinhpham@cs.rutgers.edu loadsInProgress[tid]++; 72410239Sbinhpham@cs.rutgers.edu } 72510239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 72610239Sbinhpham@cs.rutgers.edu storesInProgress[tid]++; 72710239Sbinhpham@cs.rutgers.edu } 7282292SN/A ++renamed_insts; 72911246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 73011246Sradhika.jagtap@ARM.com // this instruction have been renamed. 73111246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7328471SGiacomo.Gabrielli@arm.com 7332292SN/A // Put instruction in rename queue. 7342292SN/A toIEW->insts[toIEWIndex] = inst; 7352292SN/A ++(toIEW->size); 7362292SN/A 7372292SN/A // Increment which instruction we're on. 7382292SN/A ++toIEWIndex; 7392292SN/A 7402292SN/A // Decrement how many instructions are available. 7412292SN/A --insts_available; 7422292SN/A } 7432292SN/A 7442292SN/A instsInProgress[tid] += renamed_insts; 7452307SN/A renameRenamedInsts += renamed_insts; 7462292SN/A 7472292SN/A // If we wrote to the time buffer, record this. 7482292SN/A if (toIEWIndex) { 7492292SN/A wroteToTimeBuffer = true; 7502292SN/A } 7512292SN/A 7522292SN/A // Check if there's any instructions left that haven't yet been renamed. 7532292SN/A // If so then block. 7542292SN/A if (insts_available) { 7552292SN/A blockThisCycle = true; 7562292SN/A } 7572292SN/A 7582292SN/A if (blockThisCycle) { 7592292SN/A block(tid); 7602292SN/A toDecode->renameUnblock[tid] = false; 7612292SN/A } 7622292SN/A} 7632292SN/A 7642292SN/Atemplate<class Impl> 7652292SN/Avoid 7666221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7672292SN/A{ 7682292SN/A DynInstPtr inst = NULL; 7692292SN/A 7702292SN/A while (!insts[tid].empty()) { 7712292SN/A inst = insts[tid].front(); 7722292SN/A 7732292SN/A insts[tid].pop_front(); 7742292SN/A 7752292SN/A assert(tid == inst->threadNumber); 7762292SN/A 7777720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7787720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7792292SN/A 7802307SN/A ++renameSkidInsts; 7812307SN/A 7822292SN/A skidBuffer[tid].push_back(inst); 7832292SN/A } 7842292SN/A 7852292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7863798Sgblack@eecs.umich.edu { 7873798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7883798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 78911321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7903798Sgblack@eecs.umich.edu { 7913798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7927720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7933798Sgblack@eecs.umich.edu (*it)->seqNum); 7943798Sgblack@eecs.umich.edu } 7952292SN/A panic("Skidbuffer Exceeded Max Size"); 7963798Sgblack@eecs.umich.edu } 7972292SN/A} 7982292SN/A 7992292SN/Atemplate <class Impl> 8002292SN/Avoid 8012292SN/ADefaultRename<Impl>::sortInsts() 8022292SN/A{ 8032292SN/A int insts_from_decode = fromDecode->size; 8042292SN/A for (int i = 0; i < insts_from_decode; ++i) { 80513429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst = fromDecode->insts[i]; 8062292SN/A insts[inst->threadNumber].push_back(inst); 8079527SMatt.Horsnell@arm.com#if TRACING_ON 8089527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 8099527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 8109527SMatt.Horsnell@arm.com } 8119527SMatt.Horsnell@arm.com#endif 8122292SN/A } 8132292SN/A} 8142292SN/A 8152292SN/Atemplate<class Impl> 8162292SN/Abool 8172292SN/ADefaultRename<Impl>::skidsEmpty() 8182292SN/A{ 8196221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8206221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8212292SN/A 8223867Sbinkertn@umich.edu while (threads != end) { 8236221Snate@binkert.org ThreadID tid = *threads++; 8243867Sbinkertn@umich.edu 8253867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8262292SN/A return false; 8272292SN/A } 8282292SN/A 8292292SN/A return true; 8302292SN/A} 8312292SN/A 8322292SN/Atemplate<class Impl> 8332292SN/Avoid 8342292SN/ADefaultRename<Impl>::updateStatus() 8352292SN/A{ 8362292SN/A bool any_unblocking = false; 8372292SN/A 8386221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8396221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8402292SN/A 8413867Sbinkertn@umich.edu while (threads != end) { 8426221Snate@binkert.org ThreadID tid = *threads++; 8432292SN/A 8442292SN/A if (renameStatus[tid] == Unblocking) { 8452292SN/A any_unblocking = true; 8462292SN/A break; 8472292SN/A } 8482292SN/A } 8492292SN/A 8502292SN/A // Rename will have activity if it's unblocking. 8512292SN/A if (any_unblocking) { 8522292SN/A if (_status == Inactive) { 8532292SN/A _status = Active; 8542292SN/A 8552292SN/A DPRINTF(Activity, "Activating stage.\n"); 8562292SN/A 8572733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8582292SN/A } 8592292SN/A } else { 8602292SN/A // If it's not unblocking, then rename will not have any internal 8612292SN/A // activity. Switch it to inactive. 8622292SN/A if (_status == Active) { 8632292SN/A _status = Inactive; 8642292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8652292SN/A 8662733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8672292SN/A } 8682292SN/A } 8692292SN/A} 8702292SN/A 8712292SN/Atemplate <class Impl> 8722292SN/Abool 8736221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8742292SN/A{ 8752292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8762292SN/A 8772292SN/A // Add the current inputs onto the skid buffer, so they can be 8782292SN/A // reprocessed when this stage unblocks. 8792292SN/A skidInsert(tid); 8802292SN/A 8812292SN/A // Only signal backwards to block if the previous stages do not think 8822292SN/A // rename is already blocked. 8832292SN/A if (renameStatus[tid] != Blocked) { 8843798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8853798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8863798Sgblack@eecs.umich.edu // stages to block. 8873798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8882292SN/A toDecode->renameBlock[tid] = true; 8892292SN/A toDecode->renameUnblock[tid] = false; 8902292SN/A wroteToTimeBuffer = true; 8912292SN/A } 8922292SN/A 8932329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8942329SN/A // it would not know to complete the serialize stall. 8952301SN/A if (renameStatus[tid] != SerializeStall) { 8962292SN/A // Set status to Blocked. 8972292SN/A renameStatus[tid] = Blocked; 8982292SN/A return true; 8992292SN/A } 9002292SN/A } 9012292SN/A 9022292SN/A return false; 9032292SN/A} 9042292SN/A 9052292SN/Atemplate <class Impl> 9062292SN/Abool 9076221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 9082292SN/A{ 9092292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 9102292SN/A 9112292SN/A // Rename is done unblocking if the skid buffer is empty. 9122301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 9132292SN/A 9142292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 9152292SN/A 9162292SN/A toDecode->renameUnblock[tid] = true; 9172292SN/A wroteToTimeBuffer = true; 9182292SN/A 9192292SN/A renameStatus[tid] = Running; 9202292SN/A return true; 9212292SN/A } 9222292SN/A 9232292SN/A return false; 9242292SN/A} 9252292SN/A 9262292SN/Atemplate <class Impl> 9272292SN/Avoid 9286221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9292292SN/A{ 9302980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9312980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9322292SN/A 9331060SN/A // After a syscall squashes everything, the history buffer may be empty 9341060SN/A // but the ROB may still be squashing instructions. 9351060SN/A // Go through the most recent instructions, undoing the mappings 9361060SN/A // they did and freeing up the registers. 9372292SN/A while (!historyBuffer[tid].empty() && 9389919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9392292SN/A assert(hb_it != historyBuffer[tid].end()); 9401062SN/A 9412292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9429919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9431060SN/A 9449919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9459919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9469919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9479919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9489919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9499919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9509919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9519919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9529919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9539919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9541060SN/A 9559919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9569919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9579919Ssteve.reinhardt@amd.com } 9581062SN/A 95911246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 96011246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 96111246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 96211246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 96311246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 96411246Sradhika.jagtap@ARM.com 9652292SN/A historyBuffer[tid].erase(hb_it++); 9661061SN/A 9671062SN/A ++renameUndoneMaps; 9681060SN/A } 96913601Sgiacomo.travaglini@arm.com 97013601Sgiacomo.travaglini@arm.com // Check if we need to change vector renaming mode after squashing 97113601Sgiacomo.travaglini@arm.com cpu->switchRenameMode(tid, freeList); 9721060SN/A} 9731060SN/A 9741060SN/Atemplate<class Impl> 9751060SN/Avoid 9766221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9771060SN/A{ 9782292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9792292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9802292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9812292SN/A 9822980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9832980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9841060SN/A 9851061SN/A --hb_it; 9861060SN/A 9872292SN/A if (historyBuffer[tid].empty()) { 9882292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9892292SN/A return; 9902292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9912292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9922292SN/A "that a syscall happened recently.\n", tid); 9931060SN/A return; 9941060SN/A } 9951060SN/A 9962292SN/A // Commit all the renames up until (and including) the committed sequence 9972292SN/A // number. Some or even all of the committed instructions may not have 9982292SN/A // rename histories if they did not have destination registers that were 9992292SN/A // renamed. 10002292SN/A while (!historyBuffer[tid].empty() && 10012292SN/A hb_it != historyBuffer[tid].end() && 10029919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 10031060SN/A 100412105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 10052329SN/A "[sn:%lli].\n", 100612106SRekai.GonzalezAlberquilla@arm.com tid, hb_it->prevPhysReg->index(), 100712106SRekai.GonzalezAlberquilla@arm.com hb_it->prevPhysReg->className(), 100812105Snathanael.premillieu@arm.com hb_it->instSeqNum); 10091061SN/A 10109919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 10119919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 10129919Ssteve.reinhardt@amd.com // the old one. 10139919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 10149919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 10159919Ssteve.reinhardt@amd.com } 10169919Ssteve.reinhardt@amd.com 10172292SN/A ++renameCommittedMaps; 10181061SN/A 10192292SN/A historyBuffer[tid].erase(hb_it--); 10201060SN/A } 10211060SN/A} 10221060SN/A 10231061SN/Atemplate <class Impl> 10241061SN/Ainline void 102513429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameSrcRegs(const DynInstPtr &inst, ThreadID tid) 10261061SN/A{ 10279919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10289919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10291061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10301061SN/A 10311061SN/A // Get the architectual register numbers from the source and 10329919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10332292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 103412106SRekai.GonzalezAlberquilla@arm.com const RegId& src_reg = inst->srcRegIdx(src_idx); 103512105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 10369919Ssteve.reinhardt@amd.com 103712106SRekai.GonzalezAlberquilla@arm.com renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 103812106SRekai.GonzalezAlberquilla@arm.com switch (src_reg.classValue()) { 10399913Ssteve.reinhardt@amd.com case IntRegClass: 10409919Ssteve.reinhardt@amd.com intRenameLookups++; 10419913Ssteve.reinhardt@amd.com break; 10429913Ssteve.reinhardt@amd.com case FloatRegClass: 10439919Ssteve.reinhardt@amd.com fpRenameLookups++; 10449913Ssteve.reinhardt@amd.com break; 104512144Srekai.gonzalezalberquilla@arm.com case VecRegClass: 104613598Sgiacomo.travaglini@arm.com case VecElemClass: 104712144Srekai.gonzalezalberquilla@arm.com vecRenameLookups++; 104812144Srekai.gonzalezalberquilla@arm.com break; 104913610Sgiacomo.gabrielli@arm.com case VecPredRegClass: 105013610Sgiacomo.gabrielli@arm.com vecPredRenameLookups++; 105113610Sgiacomo.gabrielli@arm.com break; 10529920Syasuko.eckert@amd.com case CCRegClass: 10539913Ssteve.reinhardt@amd.com case MiscRegClass: 10549913Ssteve.reinhardt@amd.com break; 10559913Ssteve.reinhardt@amd.com 10569913Ssteve.reinhardt@amd.com default: 105712106SRekai.GonzalezAlberquilla@arm.com panic("Invalid register class: %d.", src_reg.classValue()); 10583773Sgblack@eecs.umich.edu } 10594352Sgblack@eecs.umich.edu 106012105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 106112106SRekai.GonzalezAlberquilla@arm.com ", got phys reg %i (%s)\n", tid, 106212106SRekai.GonzalezAlberquilla@arm.com src_reg.className(), src_reg.index(), 106312106SRekai.GonzalezAlberquilla@arm.com renamed_reg->index(), 106412106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10651061SN/A 10661061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10671061SN/A 10682292SN/A // See if the register is ready or not. 10699919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 107012105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 107112106SRekai.GonzalezAlberquilla@arm.com " is ready.\n", tid, renamed_reg->index(), 107212106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 107312106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10741061SN/A 10751061SN/A inst->markSrcRegReady(src_idx); 10764636Sgblack@eecs.umich.edu } else { 107712105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 107812106SRekai.GonzalezAlberquilla@arm.com " is not ready.\n", tid, renamed_reg->index(), 107912106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 108012106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10811061SN/A } 10821062SN/A 10831062SN/A ++renameRenameLookups; 10841061SN/A } 10851061SN/A} 10861061SN/A 10871061SN/Atemplate <class Impl> 10881061SN/Ainline void 108913429Srekai.gonzalezalberquilla@arm.comDefaultRename<Impl>::renameDestRegs(const DynInstPtr &inst, ThreadID tid) 10901061SN/A{ 10919919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10929919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10931061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10941061SN/A 10952292SN/A // Rename the destination registers. 10962292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 109712106SRekai.GonzalezAlberquilla@arm.com const RegId& dest_reg = inst->destRegIdx(dest_idx); 10989919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10999919Ssteve.reinhardt@amd.com 110012106SRekai.GonzalezAlberquilla@arm.com RegId flat_dest_regid = tc->flattenRegId(dest_reg); 11019913Ssteve.reinhardt@amd.com 110212106SRekai.GonzalezAlberquilla@arm.com rename_result = map->rename(flat_dest_regid); 11039913Ssteve.reinhardt@amd.com 110412106SRekai.GonzalezAlberquilla@arm.com inst->flattenDestReg(dest_idx, flat_dest_regid); 11051061SN/A 11069919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 11079916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11081062SN/A 110912105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 111012106SRekai.GonzalezAlberquilla@arm.com "reg %i (%i).\n", tid, dest_reg.index(), 111112106SRekai.GonzalezAlberquilla@arm.com dest_reg.className(), 111212106SRekai.GonzalezAlberquilla@arm.com rename_result.first->index(), 111312106SRekai.GonzalezAlberquilla@arm.com rename_result.first->flatIndex()); 11141062SN/A 11152292SN/A // Record the rename information so that a history can be kept. 111612106SRekai.GonzalezAlberquilla@arm.com RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 11172292SN/A rename_result.first, 11182292SN/A rename_result.second); 11191062SN/A 11202292SN/A historyBuffer[tid].push_front(hb_entry); 11211062SN/A 11222935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11232935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11242935Sksewell@umich.edu historyBuffer[tid].size(), 11252292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11261062SN/A 11272292SN/A // Tell the instruction to rename the appropriate destination 11282292SN/A // register (dest_idx) to the new physical register 11292292SN/A // (rename_result.first), and record the previous physical 11302292SN/A // register that the same logical register was renamed to 11312292SN/A // (rename_result.second). 11322292SN/A inst->renameDestReg(dest_idx, 11332292SN/A rename_result.first, 11342292SN/A rename_result.second); 11351062SN/A 11362292SN/A ++renameRenamedOperands; 11371061SN/A } 11381061SN/A} 11391061SN/A 11401061SN/Atemplate <class Impl> 11411061SN/Ainline int 11426221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11431061SN/A{ 11442292SN/A int num_free = freeEntries[tid].robEntries - 11452292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11462292SN/A 11472292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11482292SN/A 11492292SN/A return num_free; 11501061SN/A} 11511061SN/A 11521061SN/Atemplate <class Impl> 11531061SN/Ainline int 11546221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11551061SN/A{ 11562292SN/A int num_free = freeEntries[tid].iqEntries - 11572292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11582292SN/A 11592292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11602292SN/A 11612292SN/A return num_free; 11622292SN/A} 11632292SN/A 11642292SN/Atemplate <class Impl> 11652292SN/Ainline int 116610239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11672292SN/A{ 116810239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 116910935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 117010239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 117110239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 117210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 117310239Sbinhpham@cs.rutgers.edu return num_free; 117410239Sbinhpham@cs.rutgers.edu} 11752292SN/A 117610239Sbinhpham@cs.rutgers.edutemplate <class Impl> 117710239Sbinhpham@cs.rutgers.eduinline int 117810239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 117910239Sbinhpham@cs.rutgers.edu{ 118010239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 118110935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 118210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 118310239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 118410239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 118510239Sbinhpham@cs.rutgers.edu return num_free; 11862292SN/A} 11872292SN/A 11882292SN/Atemplate <class Impl> 11892292SN/Aunsigned 11902292SN/ADefaultRename<Impl>::validInsts() 11912292SN/A{ 11922292SN/A unsigned inst_count = 0; 11932292SN/A 11942292SN/A for (int i=0; i<fromDecode->size; i++) { 11952731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11962292SN/A inst_count++; 11972292SN/A } 11982292SN/A 11992292SN/A return inst_count; 12002292SN/A} 12012292SN/A 12022292SN/Atemplate <class Impl> 12032292SN/Avoid 12046221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 12052292SN/A{ 12062292SN/A if (fromIEW->iewBlock[tid]) { 12072292SN/A stalls[tid].iew = true; 12082292SN/A } 12092292SN/A 12102292SN/A if (fromIEW->iewUnblock[tid]) { 12112292SN/A assert(stalls[tid].iew); 12122292SN/A stalls[tid].iew = false; 12132292SN/A } 12142292SN/A} 12152292SN/A 12162292SN/Atemplate <class Impl> 12172292SN/Abool 12186221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12192292SN/A{ 12202292SN/A bool ret_val = false; 12212292SN/A 12222292SN/A if (stalls[tid].iew) { 12232292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12242292SN/A ret_val = true; 12252292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12262292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12272292SN/A ret_val = true; 12282292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12292292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12302292SN/A ret_val = true; 123110239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12322292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12332292SN/A ret_val = true; 12342292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12352292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12362292SN/A ret_val = true; 12372301SN/A } else if (renameStatus[tid] == SerializeStall && 12382292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12392301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12402292SN/A "empty.\n", 12412292SN/A tid); 12422292SN/A ret_val = true; 12432292SN/A } 12442292SN/A 12452292SN/A return ret_val; 12462292SN/A} 12472292SN/A 12482292SN/Atemplate <class Impl> 12492292SN/Avoid 12506221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12512292SN/A{ 12528607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12538607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12542292SN/A 125510239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 125610239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 125710239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 125810239Sbinhpham@cs.rutgers.edu } 12592292SN/A 12602292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12612292SN/A freeEntries[tid].robEntries = 12622292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12632292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12642292SN/A } 12652292SN/A 126610239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 126713610Sgiacomo.gabrielli@arm.com "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i %i)\n", 12682292SN/A tid, 12692292SN/A freeEntries[tid].iqEntries, 12702292SN/A freeEntries[tid].robEntries, 127110239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 127212109SRekai.GonzalezAlberquilla@arm.com freeEntries[tid].sqEntries, 127312109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeEntries(), 127412109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeIntEntries(), 127512109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeFloatEntries(), 127612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeVecEntries(), 127713610Sgiacomo.gabrielli@arm.com renameMap[tid]->numFreePredEntries(), 127812109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeCCEntries()); 12792292SN/A 12802292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12812292SN/A tid, instsInProgress[tid]); 12822292SN/A} 12832292SN/A 12842292SN/Atemplate <class Impl> 12852292SN/Abool 12866221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12872292SN/A{ 12882292SN/A // Check if there's a squash signal, squash if there is 12892292SN/A // Check stall signals, block if necessary. 12902292SN/A // If status was blocked 12912292SN/A // check if stall conditions have passed 12922292SN/A // if so then go to unblocking 12932292SN/A // If status was Squashing 12942292SN/A // check if squashing is not high. Switch to running this cycle. 12952301SN/A // If status was serialize stall 12962292SN/A // check if ROB is empty and no insts are in flight to the ROB 12972292SN/A 12982292SN/A readFreeEntries(tid); 12992292SN/A readStallSignals(tid); 13002292SN/A 13012292SN/A if (fromCommit->commitInfo[tid].squash) { 13022292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 13032292SN/A "commit.\n", tid); 13042292SN/A 13054632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 13062292SN/A 13072292SN/A return true; 13082292SN/A } 13092292SN/A 13102292SN/A if (checkStall(tid)) { 13112292SN/A return block(tid); 13122292SN/A } 13132292SN/A 13142292SN/A if (renameStatus[tid] == Blocked) { 13152292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 13162292SN/A tid); 13172292SN/A 13182292SN/A renameStatus[tid] = Unblocking; 13192292SN/A 13202292SN/A unblock(tid); 13212292SN/A 13222292SN/A return true; 13232292SN/A } 13242292SN/A 13252292SN/A if (renameStatus[tid] == Squashing) { 13262292SN/A // Switch status to running if rename isn't being told to block or 13272292SN/A // squash this cycle. 13283798Sgblack@eecs.umich.edu if (resumeSerialize) { 13293798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13303798Sgblack@eecs.umich.edu tid); 13312292SN/A 13323798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13333798Sgblack@eecs.umich.edu return true; 13343798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13353798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13363798Sgblack@eecs.umich.edu tid); 13373798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13383798Sgblack@eecs.umich.edu return true; 13393798Sgblack@eecs.umich.edu } else { 13403788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13413788Sgblack@eecs.umich.edu tid); 13422292SN/A 13433788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13443788Sgblack@eecs.umich.edu return false; 13453788Sgblack@eecs.umich.edu } 13462292SN/A } 13472292SN/A 13482301SN/A if (renameStatus[tid] == SerializeStall) { 13492292SN/A // Stall ends once the ROB is free. 13502301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13512292SN/A "unblocking.\n", tid); 13522292SN/A 13532301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13542292SN/A 13552292SN/A renameStatus[tid] = Unblocking; 13562292SN/A 13572292SN/A unblock(tid); 13582292SN/A 13592292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13607720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13612292SN/A 13622292SN/A // Put instruction into queue here. 13632301SN/A serial_inst->clearSerializeBefore(); 13642292SN/A 13652292SN/A if (!skidBuffer[tid].empty()) { 13662301SN/A skidBuffer[tid].push_front(serial_inst); 13672292SN/A } else { 13682301SN/A insts[tid].push_front(serial_inst); 13692292SN/A } 13702292SN/A 13712292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13722703Sktlim@umich.edu " Adding to front of list.\n", tid); 13732292SN/A 13742301SN/A serializeInst[tid] = NULL; 13752292SN/A 13762292SN/A return true; 13772292SN/A } 13782292SN/A 13792292SN/A // If we've reached this point, we have not gotten any signals that 13802292SN/A // cause rename to change its status. Rename remains the same as before. 13812292SN/A return false; 13821061SN/A} 13831061SN/A 13841060SN/Atemplate<class Impl> 13851060SN/Avoid 13866221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13871060SN/A{ 13882292SN/A if (inst_list.empty()) { 13892292SN/A // Mark a bit to say that I must serialize on the next instruction. 13902292SN/A serializeOnNextInst[tid] = true; 13911060SN/A return; 13921060SN/A } 13931060SN/A 13942292SN/A // Set the next instruction as serializing. 13952292SN/A inst_list.front()->setSerializeBefore(); 13962292SN/A} 13972292SN/A 13982292SN/Atemplate <class Impl> 13992292SN/Ainline void 14002292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 14012292SN/A{ 14022292SN/A switch (source) { 14032292SN/A case ROB: 14042292SN/A ++renameROBFullEvents; 14052292SN/A break; 14062292SN/A case IQ: 14072292SN/A ++renameIQFullEvents; 14082292SN/A break; 140910239Sbinhpham@cs.rutgers.edu case LQ: 141010239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 141110239Sbinhpham@cs.rutgers.edu break; 141210239Sbinhpham@cs.rutgers.edu case SQ: 141310239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 14142292SN/A break; 14152292SN/A default: 14162292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14172292SN/A break; 14181060SN/A } 14192292SN/A} 14201060SN/A 14212292SN/Atemplate <class Impl> 14222292SN/Avoid 14232292SN/ADefaultRename<Impl>::dumpHistory() 14242292SN/A{ 14252980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14261060SN/A 14276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14281060SN/A 14296221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14301060SN/A 14316221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 143212105Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 143312105Snathanael.premillieu@arm.com " %i[%s] Old phys reg: %i[%s]\n", 143412105Snathanael.premillieu@arm.com (*buf_it).instSeqNum, 143512106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.className(), 143612106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.index(), 143712106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->index(), 143812106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->className(), 143912106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->index(), 144012106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->className()); 14411060SN/A 14422292SN/A buf_it++; 14431062SN/A } 14441060SN/A } 14451060SN/A} 14469944Smatt.horsnell@ARM.com 14479944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1448