rename_impl.hh revision 12144
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2016 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 7012109SRekai.GonzalezAlberquilla@arm.com numThreads(params->numThreads) 711060SN/A{ 7210172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7310172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7410172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7510172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7610172Sdam.sunwoo@arm.com 772292SN/A // @todo: Make into a parameter. 7810328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 792292SN/A} 802292SN/A 812292SN/Atemplate <class Impl> 822292SN/Astd::string 832292SN/ADefaultRename<Impl>::name() const 842292SN/A{ 852292SN/A return cpu->name() + ".rename"; 861060SN/A} 871060SN/A 881061SN/Atemplate <class Impl> 891060SN/Avoid 902292SN/ADefaultRename<Impl>::regStats() 911062SN/A{ 921062SN/A renameSquashCycles 938240Snate@binkert.org .name(name() + ".SquashCycles") 941062SN/A .desc("Number of cycles rename is squashing") 951062SN/A .prereq(renameSquashCycles); 961062SN/A renameIdleCycles 978240Snate@binkert.org .name(name() + ".IdleCycles") 981062SN/A .desc("Number of cycles rename is idle") 991062SN/A .prereq(renameIdleCycles); 1001062SN/A renameBlockCycles 1018240Snate@binkert.org .name(name() + ".BlockCycles") 1021062SN/A .desc("Number of cycles rename is blocking") 1031062SN/A .prereq(renameBlockCycles); 1042301SN/A renameSerializeStallCycles 1058240Snate@binkert.org .name(name() + ".serializeStallCycles") 1062301SN/A .desc("count of cycles rename stalled for serializing inst") 1072301SN/A .flags(Stats::total); 1082292SN/A renameRunCycles 1098240Snate@binkert.org .name(name() + ".RunCycles") 1102292SN/A .desc("Number of cycles rename is running") 1112292SN/A .prereq(renameIdleCycles); 1121062SN/A renameUnblockCycles 1138240Snate@binkert.org .name(name() + ".UnblockCycles") 1141062SN/A .desc("Number of cycles rename is unblocking") 1151062SN/A .prereq(renameUnblockCycles); 1161062SN/A renameRenamedInsts 1178240Snate@binkert.org .name(name() + ".RenamedInsts") 1181062SN/A .desc("Number of instructions processed by rename") 1191062SN/A .prereq(renameRenamedInsts); 1201062SN/A renameSquashedInsts 1218240Snate@binkert.org .name(name() + ".SquashedInsts") 1221062SN/A .desc("Number of squashed instructions processed by rename") 1231062SN/A .prereq(renameSquashedInsts); 1241062SN/A renameROBFullEvents 1258240Snate@binkert.org .name(name() + ".ROBFullEvents") 1262292SN/A .desc("Number of times rename has blocked due to ROB full") 1271062SN/A .prereq(renameROBFullEvents); 1281062SN/A renameIQFullEvents 1298240Snate@binkert.org .name(name() + ".IQFullEvents") 1302292SN/A .desc("Number of times rename has blocked due to IQ full") 1311062SN/A .prereq(renameIQFullEvents); 13210239Sbinhpham@cs.rutgers.edu renameLQFullEvents 13310239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 13410239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 13510239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 13610239Sbinhpham@cs.rutgers.edu renameSQFullEvents 13710239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 13810239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 13910239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1401062SN/A renameFullRegistersEvents 1418240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1421062SN/A .desc("Number of times there has been no free registers") 1431062SN/A .prereq(renameFullRegistersEvents); 1441062SN/A renameRenamedOperands 1458240Snate@binkert.org .name(name() + ".RenamedOperands") 1461062SN/A .desc("Number of destination operands rename has renamed") 1471062SN/A .prereq(renameRenamedOperands); 1481062SN/A renameRenameLookups 1498240Snate@binkert.org .name(name() + ".RenameLookups") 1501062SN/A .desc("Number of register rename lookups that rename has made") 1511062SN/A .prereq(renameRenameLookups); 1521062SN/A renameCommittedMaps 1538240Snate@binkert.org .name(name() + ".CommittedMaps") 1541062SN/A .desc("Number of HB maps that are committed") 1551062SN/A .prereq(renameCommittedMaps); 1561062SN/A renameUndoneMaps 1578240Snate@binkert.org .name(name() + ".UndoneMaps") 1581062SN/A .desc("Number of HB maps that are undone due to squashing") 1591062SN/A .prereq(renameUndoneMaps); 1602301SN/A renamedSerializing 1618240Snate@binkert.org .name(name() + ".serializingInsts") 1622301SN/A .desc("count of serializing insts renamed") 1632301SN/A .flags(Stats::total) 1642301SN/A ; 1652301SN/A renamedTempSerializing 1668240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1672301SN/A .desc("count of temporary serializing insts renamed") 1682301SN/A .flags(Stats::total) 1692301SN/A ; 1702307SN/A renameSkidInsts 1718240Snate@binkert.org .name(name() + ".skidInsts") 1722307SN/A .desc("count of insts added to the skid buffer") 1732307SN/A .flags(Stats::total) 1742307SN/A ; 1757897Shestness@cs.utexas.edu intRenameLookups 1768240Snate@binkert.org .name(name() + ".int_rename_lookups") 1777897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1787897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1797897Shestness@cs.utexas.edu fpRenameLookups 1808240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1817897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1827897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 18312109SRekai.GonzalezAlberquilla@arm.com vecRenameLookups 18412109SRekai.GonzalezAlberquilla@arm.com .name(name() + ".vec_rename_lookups") 18512109SRekai.GonzalezAlberquilla@arm.com .desc("Number of vector rename lookups") 18612109SRekai.GonzalezAlberquilla@arm.com .prereq(vecRenameLookups); 1871062SN/A} 1881062SN/A 1891062SN/Atemplate <class Impl> 1901062SN/Avoid 19111246Sradhika.jagtap@ARM.comDefaultRename<Impl>::regProbePoints() 19211246Sradhika.jagtap@ARM.com{ 19311246Sradhika.jagtap@ARM.com ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); 19411246Sradhika.jagtap@ARM.com ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), 19511246Sradhika.jagtap@ARM.com "SquashInRename"); 19611246Sradhika.jagtap@ARM.com} 19711246Sradhika.jagtap@ARM.com 19811246Sradhika.jagtap@ARM.comtemplate <class Impl> 19911246Sradhika.jagtap@ARM.comvoid 2002292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2011060SN/A{ 2021060SN/A timeBuffer = tb_ptr; 2031060SN/A 2041060SN/A // Setup wire to read information from time buffer, from IEW stage. 2051060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 2061060SN/A 2071060SN/A // Setup wire to read infromation from time buffer, from commit stage. 2081060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 2091060SN/A 2101060SN/A // Setup wire to write information to previous stages. 2111060SN/A toDecode = timeBuffer->getWire(0); 2121060SN/A} 2131060SN/A 2141061SN/Atemplate <class Impl> 2151060SN/Avoid 2162292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2171060SN/A{ 2181060SN/A renameQueue = rq_ptr; 2191060SN/A 2201060SN/A // Setup wire to write information to future stages. 2211060SN/A toIEW = renameQueue->getWire(0); 2221060SN/A} 2231060SN/A 2241061SN/Atemplate <class Impl> 2251060SN/Avoid 2262292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2271060SN/A{ 2281060SN/A decodeQueue = dq_ptr; 2291060SN/A 2301060SN/A // Setup wire to get information from decode. 2311060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2321060SN/A} 2331060SN/A 2341061SN/Atemplate <class Impl> 2351060SN/Avoid 2369427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2371060SN/A{ 2389444SAndreas.Sandberg@ARM.com resetStage(); 2399444SAndreas.Sandberg@ARM.com} 2409444SAndreas.Sandberg@ARM.com 2419444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2429444SAndreas.Sandberg@ARM.comvoid 2439444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2449444SAndreas.Sandberg@ARM.com{ 2459444SAndreas.Sandberg@ARM.com _status = Inactive; 2469444SAndreas.Sandberg@ARM.com 2479444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2489444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2499444SAndreas.Sandberg@ARM.com 2502329SN/A // Grab the number of free entries directly from the stages. 2516221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2529444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2539444SAndreas.Sandberg@ARM.com 2542292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 25510239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 25610239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2572292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2582292SN/A emptyROB[tid] = true; 2599444SAndreas.Sandberg@ARM.com 2609444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2619444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2629444SAndreas.Sandberg@ARM.com 2639444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 26410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 26510239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 2669444SAndreas.Sandberg@ARM.com 2679444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2682292SN/A } 2691060SN/A} 2701060SN/A 2712292SN/Atemplate<class Impl> 2722292SN/Avoid 2736221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2742292SN/A{ 2752292SN/A activeThreads = at_ptr; 2762292SN/A} 2772292SN/A 2782292SN/A 2791061SN/Atemplate <class Impl> 2801060SN/Avoid 2812292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2821060SN/A{ 2836221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2846221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2851060SN/A} 2861060SN/A 2871061SN/Atemplate <class Impl> 2881060SN/Avoid 2892292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2901060SN/A{ 2912292SN/A freeList = fl_ptr; 2922292SN/A} 2931060SN/A 2942292SN/Atemplate<class Impl> 2952292SN/Avoid 2962292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2972292SN/A{ 2982292SN/A scoreboard = _scoreboard; 2991060SN/A} 3001060SN/A 3011061SN/Atemplate <class Impl> 3022863Sktlim@umich.edubool 3039444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 3041060SN/A{ 3059444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3069444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 3079444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 3089444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 30911650Srekai.gonzalezalberquilla@arm.com !insts[tid].empty() || 31011650Srekai.gonzalezalberquilla@arm.com (renameStatus[tid] != Idle && renameStatus[tid] != Running)) 3119444SAndreas.Sandberg@ARM.com return false; 3129444SAndreas.Sandberg@ARM.com } 3132863Sktlim@umich.edu return true; 3142316SN/A} 3151060SN/A 3162316SN/Atemplate <class Impl> 3172316SN/Avoid 3182307SN/ADefaultRename<Impl>::takeOverFrom() 3191060SN/A{ 3209444SAndreas.Sandberg@ARM.com resetStage(); 3219444SAndreas.Sandberg@ARM.com} 3221060SN/A 3239444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3249444SAndreas.Sandberg@ARM.comvoid 3259444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3269444SAndreas.Sandberg@ARM.com{ 3276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3289444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3299444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3309444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3319444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3322307SN/A } 3332307SN/A} 3342307SN/A 3352307SN/Atemplate <class Impl> 3362307SN/Avoid 3376221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3381858SN/A{ 3392292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3401858SN/A 3412292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3422292SN/A // If it still needs to block, the blocking should happen the next 3432292SN/A // cycle and there should be space to hold everything due to the squash. 3442292SN/A if (renameStatus[tid] == Blocked || 3453788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3462292SN/A toDecode->renameUnblock[tid] = 1; 3472698Sktlim@umich.edu 3483788Sgblack@eecs.umich.edu resumeSerialize = false; 3492301SN/A serializeInst[tid] = NULL; 3503788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3513788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3523788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3533788Sgblack@eecs.umich.edu resumeSerialize = true; 3543788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3553788Sgblack@eecs.umich.edu } else { 3563788Sgblack@eecs.umich.edu resumeSerialize = false; 3573788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3583788Sgblack@eecs.umich.edu 3593788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3603788Sgblack@eecs.umich.edu } 3612292SN/A } 3622292SN/A 3632292SN/A // Set the status to Squashing. 3642292SN/A renameStatus[tid] = Squashing; 3652292SN/A 3662329SN/A // Squash any instructions from decode. 3672292SN/A for (int i=0; i<fromDecode->size; i++) { 3682935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3692935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3702731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3712292SN/A wroteToTimeBuffer = true; 3722292SN/A } 3732935Sksewell@umich.edu 3742292SN/A } 3752292SN/A 3762935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3774632Sgblack@eecs.umich.edu // insts in them. 3783093Sksewell@umich.edu insts[tid].clear(); 3792292SN/A 3802292SN/A // Clear the skid buffer in case it has any data in it. 3813093Sksewell@umich.edu skidBuffer[tid].clear(); 3824632Sgblack@eecs.umich.edu 3832935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3842292SN/A} 3852292SN/A 3862292SN/Atemplate <class Impl> 3872292SN/Avoid 3882292SN/ADefaultRename<Impl>::tick() 3892292SN/A{ 3902292SN/A wroteToTimeBuffer = false; 3912292SN/A 3922292SN/A blockThisCycle = false; 3932292SN/A 3942292SN/A bool status_change = false; 3952292SN/A 3962292SN/A toIEWIndex = 0; 3972292SN/A 3982292SN/A sortInsts(); 3992292SN/A 4006221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4016221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4022292SN/A 4032292SN/A // Check stall and squash signals. 4043867Sbinkertn@umich.edu while (threads != end) { 4056221Snate@binkert.org ThreadID tid = *threads++; 4062292SN/A 4072292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 4082292SN/A 4092292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 4102292SN/A 4112292SN/A rename(status_change, tid); 4122292SN/A } 4132292SN/A 4142292SN/A if (status_change) { 4152292SN/A updateStatus(); 4162292SN/A } 4172292SN/A 4182292SN/A if (wroteToTimeBuffer) { 4192292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4202292SN/A cpu->activityThisCycle(); 4212292SN/A } 4222292SN/A 4233867Sbinkertn@umich.edu threads = activeThreads->begin(); 4242292SN/A 4253867Sbinkertn@umich.edu while (threads != end) { 4266221Snate@binkert.org ThreadID tid = *threads++; 4272292SN/A 4282292SN/A // If we committed this cycle then doneSeqNum will be > 0 4292292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4302292SN/A !fromCommit->commitInfo[tid].squash && 4312292SN/A renameStatus[tid] != Squashing) { 4322292SN/A 4332292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4342292SN/A tid); 4352292SN/A } 4362292SN/A } 4372292SN/A 4382292SN/A // @todo: make into updateProgress function 4396221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4402292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 44110239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 44210239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 44310239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 44410239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4452292SN/A assert(instsInProgress[tid] >=0); 4462292SN/A } 4472292SN/A 4482292SN/A} 4492292SN/A 4502292SN/Atemplate<class Impl> 4512292SN/Avoid 4526221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4532292SN/A{ 4542292SN/A // If status is Running or idle, 4552292SN/A // call renameInsts() 4562292SN/A // If status is Unblocking, 4572292SN/A // buffer any instructions coming from decode 4582292SN/A // continue trying to empty skid buffer 4592292SN/A // check if stall conditions have passed 4602292SN/A 4612292SN/A if (renameStatus[tid] == Blocked) { 4622292SN/A ++renameBlockCycles; 4632292SN/A } else if (renameStatus[tid] == Squashing) { 4642292SN/A ++renameSquashCycles; 4652301SN/A } else if (renameStatus[tid] == SerializeStall) { 4662301SN/A ++renameSerializeStallCycles; 4673788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4683788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4693788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4703788Sgblack@eecs.umich.edu if (resumeSerialize) { 4713788Sgblack@eecs.umich.edu resumeSerialize = false; 4723788Sgblack@eecs.umich.edu block(tid); 4733788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4743788Sgblack@eecs.umich.edu } 4753798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4763798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4773798Sgblack@eecs.umich.edu block(tid); 4783798Sgblack@eecs.umich.edu resumeUnblocking = false; 4793798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4803798Sgblack@eecs.umich.edu } 4812292SN/A } 4822292SN/A 4832292SN/A if (renameStatus[tid] == Running || 4842292SN/A renameStatus[tid] == Idle) { 4852292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4862292SN/A "stage.\n", tid); 4872292SN/A 4882292SN/A renameInsts(tid); 4892292SN/A } else if (renameStatus[tid] == Unblocking) { 4902292SN/A renameInsts(tid); 4912292SN/A 4922292SN/A if (validInsts()) { 4932292SN/A // Add the current inputs to the skid buffer so they can be 4942292SN/A // reprocessed when this stage unblocks. 4952292SN/A skidInsert(tid); 4962292SN/A } 4972292SN/A 4982292SN/A // If we switched over to blocking, then there's a potential for 4992292SN/A // an overall status change. 5002292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 5011858SN/A } 5021858SN/A} 5031858SN/A 5041858SN/Atemplate <class Impl> 5051858SN/Avoid 5066221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 5071858SN/A{ 5082292SN/A // Instructions can be either in the skid buffer or the queue of 5092292SN/A // instructions coming from decode, depending on the status. 5102292SN/A int insts_available = renameStatus[tid] == Unblocking ? 5112292SN/A skidBuffer[tid].size() : insts[tid].size(); 5121858SN/A 5132292SN/A // Check the decode queue to see if instructions are available. 5142292SN/A // If there are no available instructions to rename, then do nothing. 5152292SN/A if (insts_available == 0) { 5162292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5172292SN/A tid); 5182292SN/A // Should I change status to idle? 5192292SN/A ++renameIdleCycles; 5202292SN/A return; 5212292SN/A } else if (renameStatus[tid] == Unblocking) { 5222292SN/A ++renameUnblockCycles; 5232292SN/A } else if (renameStatus[tid] == Running) { 5242292SN/A ++renameRunCycles; 5252292SN/A } 5261858SN/A 5272292SN/A DynInstPtr inst; 5282292SN/A 5292292SN/A // Will have to do a different calculation for the number of free 5302292SN/A // entries. 5312292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5322292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5332292SN/A int min_free_entries = free_rob_entries; 5342292SN/A 5352292SN/A FullSource source = ROB; 5362292SN/A 5372292SN/A if (free_iq_entries < min_free_entries) { 5382292SN/A min_free_entries = free_iq_entries; 5392292SN/A source = IQ; 5402292SN/A } 5412292SN/A 5422292SN/A // Check if there's any space left. 5432292SN/A if (min_free_entries <= 0) { 54410239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5452292SN/A "entries.\n" 5462292SN/A "ROB has %i free entries.\n" 54710239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5482292SN/A tid, 5492292SN/A free_rob_entries, 55010239Sbinhpham@cs.rutgers.edu free_iq_entries); 5512292SN/A 5522292SN/A blockThisCycle = true; 5532292SN/A 5542292SN/A block(tid); 5552292SN/A 5562292SN/A incrFullStat(source); 5572292SN/A 5582292SN/A return; 5592292SN/A } else if (min_free_entries < insts_available) { 5602292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5612292SN/A "%i insts available, but only %i insts can be " 5622292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5632292SN/A tid, insts_available, min_free_entries); 5642292SN/A 5652292SN/A insts_available = min_free_entries; 5662292SN/A 5672292SN/A blockThisCycle = true; 5682292SN/A 5692292SN/A incrFullStat(source); 5702292SN/A } 5712292SN/A 5722292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5732292SN/A skidBuffer[tid] : insts[tid]; 5742292SN/A 5752292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5762292SN/A "send iew.\n", tid, insts_available); 5772292SN/A 5782292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5792292SN/A "dispatched to IQ last cycle.\n", 5802292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5812292SN/A 5822292SN/A // Handle serializing the next instruction if necessary. 5832292SN/A if (serializeOnNextInst[tid]) { 5842292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5852292SN/A // ROB already empty; no need to serialize. 5862292SN/A serializeOnNextInst[tid] = false; 5872292SN/A } else if (!insts_to_rename.empty()) { 5882292SN/A insts_to_rename.front()->setSerializeBefore(); 5892292SN/A } 5902292SN/A } 5912292SN/A 5922292SN/A int renamed_insts = 0; 5932292SN/A 5942292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5952292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5962292SN/A 5972292SN/A assert(!insts_to_rename.empty()); 5982292SN/A 5992292SN/A inst = insts_to_rename.front(); 6002292SN/A 60110239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 60210239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 60310239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 60410239Sbinhpham@cs.rutgers.edu 60510239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 60610933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 60710933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 60810933Snilay@cs.wisc.edu source = LQ; 60910933Snilay@cs.wisc.edu incrFullStat(source); 61010933Snilay@cs.wisc.edu break; 61110933Snilay@cs.wisc.edu } 61210239Sbinhpham@cs.rutgers.edu } 61310239Sbinhpham@cs.rutgers.edu 61410239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 61510933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 61610933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 61710933Snilay@cs.wisc.edu source = SQ; 61810933Snilay@cs.wisc.edu incrFullStat(source); 61910933Snilay@cs.wisc.edu break; 62010933Snilay@cs.wisc.edu } 62110239Sbinhpham@cs.rutgers.edu } 62210239Sbinhpham@cs.rutgers.edu 6232292SN/A insts_to_rename.pop_front(); 6242292SN/A 6252292SN/A if (renameStatus[tid] == Unblocking) { 6267720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6277720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6282292SN/A } 6292292SN/A 6302292SN/A if (inst->isSquashed()) { 6317720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6327720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6337720Sgblack@eecs.umich.edu inst->pcState()); 6342292SN/A 6352292SN/A ++renameSquashedInsts; 6362292SN/A 6372292SN/A // Decrement how many instructions are available. 6382292SN/A --insts_available; 6392292SN/A 6402292SN/A continue; 6412292SN/A } 6422292SN/A 6432292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6447720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6452292SN/A 6469531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6479531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 64810715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 64910715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 65012109SRekai.GonzalezAlberquilla@arm.com inst->numVecDestRegs(), 65112109SRekai.GonzalezAlberquilla@arm.com inst->numVecElemDestRegs(), 65210935Snilay@cs.wisc.edu inst->numCCDestRegs())) { 6539531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6549531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6559531Sgeoffrey.blake@arm.com blockThisCycle = true; 6569531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6579531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6589531Sgeoffrey.blake@arm.com 6599531Sgeoffrey.blake@arm.com break; 6609531Sgeoffrey.blake@arm.com } 6619531Sgeoffrey.blake@arm.com 6622292SN/A // Handle serializeAfter/serializeBefore instructions. 6632292SN/A // serializeAfter marks the next instruction as serializeBefore. 6642292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6652292SN/A // is empty. 6662336SN/A 6672336SN/A // In this model, IPR accesses are serialize before 6682336SN/A // instructions, and store conditionals are serialize after 6692336SN/A // instructions. This is mainly due to lack of support for 6702336SN/A // out-of-order operations of either of those classes of 6712336SN/A // instructions. 6722336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6732336SN/A !inst->isSerializeHandled()) { 6742292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6752292SN/A 6762301SN/A if (!inst->isTempSerializeBefore()) { 6772301SN/A renamedSerializing++; 6782292SN/A inst->setSerializeHandled(); 6792301SN/A } else { 6802301SN/A renamedTempSerializing++; 6812301SN/A } 6822292SN/A 6832301SN/A // Change status over to SerializeStall so that other stages know 6842292SN/A // what this is blocked on. 6852301SN/A renameStatus[tid] = SerializeStall; 6862292SN/A 6872301SN/A serializeInst[tid] = inst; 6882292SN/A 6892292SN/A blockThisCycle = true; 6902292SN/A 6912292SN/A break; 6922336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6932336SN/A !inst->isSerializeHandled()) { 6942292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6952292SN/A 6962307SN/A renamedSerializing++; 6972307SN/A 6982292SN/A inst->setSerializeHandled(); 6992292SN/A 7002292SN/A serializeAfter(insts_to_rename, tid); 7012292SN/A } 7022292SN/A 7032292SN/A renameSrcRegs(inst, inst->threadNumber); 7042292SN/A 7052292SN/A renameDestRegs(inst, inst->threadNumber); 7062292SN/A 70710239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 70810239Sbinhpham@cs.rutgers.edu loadsInProgress[tid]++; 70910239Sbinhpham@cs.rutgers.edu } 71010239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 71110239Sbinhpham@cs.rutgers.edu storesInProgress[tid]++; 71210239Sbinhpham@cs.rutgers.edu } 7132292SN/A ++renamed_insts; 71411246Sradhika.jagtap@ARM.com // Notify potential listeners that source and destination registers for 71511246Sradhika.jagtap@ARM.com // this instruction have been renamed. 71611246Sradhika.jagtap@ARM.com ppRename->notify(inst); 7178471SGiacomo.Gabrielli@arm.com 7182292SN/A // Put instruction in rename queue. 7192292SN/A toIEW->insts[toIEWIndex] = inst; 7202292SN/A ++(toIEW->size); 7212292SN/A 7222292SN/A // Increment which instruction we're on. 7232292SN/A ++toIEWIndex; 7242292SN/A 7252292SN/A // Decrement how many instructions are available. 7262292SN/A --insts_available; 7272292SN/A } 7282292SN/A 7292292SN/A instsInProgress[tid] += renamed_insts; 7302307SN/A renameRenamedInsts += renamed_insts; 7312292SN/A 7322292SN/A // If we wrote to the time buffer, record this. 7332292SN/A if (toIEWIndex) { 7342292SN/A wroteToTimeBuffer = true; 7352292SN/A } 7362292SN/A 7372292SN/A // Check if there's any instructions left that haven't yet been renamed. 7382292SN/A // If so then block. 7392292SN/A if (insts_available) { 7402292SN/A blockThisCycle = true; 7412292SN/A } 7422292SN/A 7432292SN/A if (blockThisCycle) { 7442292SN/A block(tid); 7452292SN/A toDecode->renameUnblock[tid] = false; 7462292SN/A } 7472292SN/A} 7482292SN/A 7492292SN/Atemplate<class Impl> 7502292SN/Avoid 7516221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7522292SN/A{ 7532292SN/A DynInstPtr inst = NULL; 7542292SN/A 7552292SN/A while (!insts[tid].empty()) { 7562292SN/A inst = insts[tid].front(); 7572292SN/A 7582292SN/A insts[tid].pop_front(); 7592292SN/A 7602292SN/A assert(tid == inst->threadNumber); 7612292SN/A 7627720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7637720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7642292SN/A 7652307SN/A ++renameSkidInsts; 7662307SN/A 7672292SN/A skidBuffer[tid].push_back(inst); 7682292SN/A } 7692292SN/A 7702292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7713798Sgblack@eecs.umich.edu { 7723798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7733798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 77411321Ssteve.reinhardt@amd.com for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7753798Sgblack@eecs.umich.edu { 7763798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7777720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7783798Sgblack@eecs.umich.edu (*it)->seqNum); 7793798Sgblack@eecs.umich.edu } 7802292SN/A panic("Skidbuffer Exceeded Max Size"); 7813798Sgblack@eecs.umich.edu } 7822292SN/A} 7832292SN/A 7842292SN/Atemplate <class Impl> 7852292SN/Avoid 7862292SN/ADefaultRename<Impl>::sortInsts() 7872292SN/A{ 7882292SN/A int insts_from_decode = fromDecode->size; 7892292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7902292SN/A DynInstPtr inst = fromDecode->insts[i]; 7912292SN/A insts[inst->threadNumber].push_back(inst); 7929527SMatt.Horsnell@arm.com#if TRACING_ON 7939527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7949527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7959527SMatt.Horsnell@arm.com } 7969527SMatt.Horsnell@arm.com#endif 7972292SN/A } 7982292SN/A} 7992292SN/A 8002292SN/Atemplate<class Impl> 8012292SN/Abool 8022292SN/ADefaultRename<Impl>::skidsEmpty() 8032292SN/A{ 8046221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8056221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8062292SN/A 8073867Sbinkertn@umich.edu while (threads != end) { 8086221Snate@binkert.org ThreadID tid = *threads++; 8093867Sbinkertn@umich.edu 8103867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 8112292SN/A return false; 8122292SN/A } 8132292SN/A 8142292SN/A return true; 8152292SN/A} 8162292SN/A 8172292SN/Atemplate<class Impl> 8182292SN/Avoid 8192292SN/ADefaultRename<Impl>::updateStatus() 8202292SN/A{ 8212292SN/A bool any_unblocking = false; 8222292SN/A 8236221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8246221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8252292SN/A 8263867Sbinkertn@umich.edu while (threads != end) { 8276221Snate@binkert.org ThreadID tid = *threads++; 8282292SN/A 8292292SN/A if (renameStatus[tid] == Unblocking) { 8302292SN/A any_unblocking = true; 8312292SN/A break; 8322292SN/A } 8332292SN/A } 8342292SN/A 8352292SN/A // Rename will have activity if it's unblocking. 8362292SN/A if (any_unblocking) { 8372292SN/A if (_status == Inactive) { 8382292SN/A _status = Active; 8392292SN/A 8402292SN/A DPRINTF(Activity, "Activating stage.\n"); 8412292SN/A 8422733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8432292SN/A } 8442292SN/A } else { 8452292SN/A // If it's not unblocking, then rename will not have any internal 8462292SN/A // activity. Switch it to inactive. 8472292SN/A if (_status == Active) { 8482292SN/A _status = Inactive; 8492292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8502292SN/A 8512733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8522292SN/A } 8532292SN/A } 8542292SN/A} 8552292SN/A 8562292SN/Atemplate <class Impl> 8572292SN/Abool 8586221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8592292SN/A{ 8602292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8612292SN/A 8622292SN/A // Add the current inputs onto the skid buffer, so they can be 8632292SN/A // reprocessed when this stage unblocks. 8642292SN/A skidInsert(tid); 8652292SN/A 8662292SN/A // Only signal backwards to block if the previous stages do not think 8672292SN/A // rename is already blocked. 8682292SN/A if (renameStatus[tid] != Blocked) { 8693798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8703798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8713798Sgblack@eecs.umich.edu // stages to block. 8723798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8732292SN/A toDecode->renameBlock[tid] = true; 8742292SN/A toDecode->renameUnblock[tid] = false; 8752292SN/A wroteToTimeBuffer = true; 8762292SN/A } 8772292SN/A 8782329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8792329SN/A // it would not know to complete the serialize stall. 8802301SN/A if (renameStatus[tid] != SerializeStall) { 8812292SN/A // Set status to Blocked. 8822292SN/A renameStatus[tid] = Blocked; 8832292SN/A return true; 8842292SN/A } 8852292SN/A } 8862292SN/A 8872292SN/A return false; 8882292SN/A} 8892292SN/A 8902292SN/Atemplate <class Impl> 8912292SN/Abool 8926221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8932292SN/A{ 8942292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8952292SN/A 8962292SN/A // Rename is done unblocking if the skid buffer is empty. 8972301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8982292SN/A 8992292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 9002292SN/A 9012292SN/A toDecode->renameUnblock[tid] = true; 9022292SN/A wroteToTimeBuffer = true; 9032292SN/A 9042292SN/A renameStatus[tid] = Running; 9052292SN/A return true; 9062292SN/A } 9072292SN/A 9082292SN/A return false; 9092292SN/A} 9102292SN/A 9112292SN/Atemplate <class Impl> 9122292SN/Avoid 9136221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 9142292SN/A{ 9152980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9162980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9172292SN/A 9181060SN/A // After a syscall squashes everything, the history buffer may be empty 9191060SN/A // but the ROB may still be squashing instructions. 9202292SN/A if (historyBuffer[tid].empty()) { 9211060SN/A return; 9221060SN/A } 9231060SN/A 9241060SN/A // Go through the most recent instructions, undoing the mappings 9251060SN/A // they did and freeing up the registers. 9262292SN/A while (!historyBuffer[tid].empty() && 9279919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9282292SN/A assert(hb_it != historyBuffer[tid].end()); 9291062SN/A 9302292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9319919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9321060SN/A 9339919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9349919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9359919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9369919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9379919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9389919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9399919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9409919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9419919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9429919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9431060SN/A 9449919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9459919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9469919Ssteve.reinhardt@amd.com } 9471062SN/A 94811246Sradhika.jagtap@ARM.com // Notify potential listeners that the register mapping needs to be 94911246Sradhika.jagtap@ARM.com // removed because the instruction it was mapped to got squashed. Note 95011246Sradhika.jagtap@ARM.com // that this is done before hb_it is incremented. 95111246Sradhika.jagtap@ARM.com ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, 95211246Sradhika.jagtap@ARM.com hb_it->newPhysReg)); 95311246Sradhika.jagtap@ARM.com 9542292SN/A historyBuffer[tid].erase(hb_it++); 9551061SN/A 9561062SN/A ++renameUndoneMaps; 9571060SN/A } 9581060SN/A} 9591060SN/A 9601060SN/Atemplate<class Impl> 9611060SN/Avoid 9626221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9631060SN/A{ 9642292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9652292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9662292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9672292SN/A 9682980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9692980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9701060SN/A 9711061SN/A --hb_it; 9721060SN/A 9732292SN/A if (historyBuffer[tid].empty()) { 9742292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9752292SN/A return; 9762292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9772292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9782292SN/A "that a syscall happened recently.\n", tid); 9791060SN/A return; 9801060SN/A } 9811060SN/A 9822292SN/A // Commit all the renames up until (and including) the committed sequence 9832292SN/A // number. Some or even all of the committed instructions may not have 9842292SN/A // rename histories if they did not have destination registers that were 9852292SN/A // renamed. 9862292SN/A while (!historyBuffer[tid].empty() && 9872292SN/A hb_it != historyBuffer[tid].end() && 9889919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9891060SN/A 99012105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i (%s), " 9912329SN/A "[sn:%lli].\n", 99212106SRekai.GonzalezAlberquilla@arm.com tid, hb_it->prevPhysReg->index(), 99312106SRekai.GonzalezAlberquilla@arm.com hb_it->prevPhysReg->className(), 99412105Snathanael.premillieu@arm.com hb_it->instSeqNum); 9951061SN/A 9969919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 9979919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 9989919Ssteve.reinhardt@amd.com // the old one. 9999919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 10009919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 10019919Ssteve.reinhardt@amd.com } 10029919Ssteve.reinhardt@amd.com 10032292SN/A ++renameCommittedMaps; 10041061SN/A 10052292SN/A historyBuffer[tid].erase(hb_it--); 10061060SN/A } 10071060SN/A} 10081060SN/A 10091061SN/Atemplate <class Impl> 10101061SN/Ainline void 10116221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 10121061SN/A{ 10139919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10149919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10151061SN/A unsigned num_src_regs = inst->numSrcRegs(); 10161061SN/A 10171061SN/A // Get the architectual register numbers from the source and 10189919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 10192292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 102012106SRekai.GonzalezAlberquilla@arm.com const RegId& src_reg = inst->srcRegIdx(src_idx); 102112105Snathanael.premillieu@arm.com PhysRegIdPtr renamed_reg; 10229919Ssteve.reinhardt@amd.com 102312106SRekai.GonzalezAlberquilla@arm.com renamed_reg = map->lookup(tc->flattenRegId(src_reg)); 102412106SRekai.GonzalezAlberquilla@arm.com switch (src_reg.classValue()) { 10259913Ssteve.reinhardt@amd.com case IntRegClass: 10269919Ssteve.reinhardt@amd.com intRenameLookups++; 10279913Ssteve.reinhardt@amd.com break; 10289913Ssteve.reinhardt@amd.com case FloatRegClass: 10299919Ssteve.reinhardt@amd.com fpRenameLookups++; 10309913Ssteve.reinhardt@amd.com break; 103112144Srekai.gonzalezalberquilla@arm.com case VecRegClass: 103212144Srekai.gonzalezalberquilla@arm.com vecRenameLookups++; 103312144Srekai.gonzalezalberquilla@arm.com break; 10349920Syasuko.eckert@amd.com case CCRegClass: 10359913Ssteve.reinhardt@amd.com case MiscRegClass: 10369913Ssteve.reinhardt@amd.com break; 10379913Ssteve.reinhardt@amd.com 10389913Ssteve.reinhardt@amd.com default: 103912106SRekai.GonzalezAlberquilla@arm.com panic("Invalid register class: %d.", src_reg.classValue()); 10403773Sgblack@eecs.umich.edu } 10414352Sgblack@eecs.umich.edu 104212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i" 104312106SRekai.GonzalezAlberquilla@arm.com ", got phys reg %i (%s)\n", tid, 104412106SRekai.GonzalezAlberquilla@arm.com src_reg.className(), src_reg.index(), 104512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->index(), 104612106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10471061SN/A 10481061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10491061SN/A 10502292SN/A // See if the register is ready or not. 10519919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 105212105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 105312106SRekai.GonzalezAlberquilla@arm.com " is ready.\n", tid, renamed_reg->index(), 105412106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 105512106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10561061SN/A 10571061SN/A inst->markSrcRegReady(src_idx); 10584636Sgblack@eecs.umich.edu } else { 105912105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Register %d (flat: %d) (%s)" 106012106SRekai.GonzalezAlberquilla@arm.com " is not ready.\n", tid, renamed_reg->index(), 106112106SRekai.GonzalezAlberquilla@arm.com renamed_reg->flatIndex(), 106212106SRekai.GonzalezAlberquilla@arm.com renamed_reg->className()); 10631061SN/A } 10641062SN/A 10651062SN/A ++renameRenameLookups; 10661061SN/A } 10671061SN/A} 10681061SN/A 10691061SN/Atemplate <class Impl> 10701061SN/Ainline void 10716221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10721061SN/A{ 10739919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10749919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10751061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10761061SN/A 10772292SN/A // Rename the destination registers. 10782292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 107912106SRekai.GonzalezAlberquilla@arm.com const RegId& dest_reg = inst->destRegIdx(dest_idx); 10809919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10819919Ssteve.reinhardt@amd.com 108212106SRekai.GonzalezAlberquilla@arm.com RegId flat_dest_regid = tc->flattenRegId(dest_reg); 10839913Ssteve.reinhardt@amd.com 108412106SRekai.GonzalezAlberquilla@arm.com rename_result = map->rename(flat_dest_regid); 10859913Ssteve.reinhardt@amd.com 108612106SRekai.GonzalezAlberquilla@arm.com inst->flattenDestReg(dest_idx, flat_dest_regid); 10871061SN/A 10889919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 10899916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 10901062SN/A 109112105Snathanael.premillieu@arm.com DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i (%s) to physical " 109212106SRekai.GonzalezAlberquilla@arm.com "reg %i (%i).\n", tid, dest_reg.index(), 109312106SRekai.GonzalezAlberquilla@arm.com dest_reg.className(), 109412106SRekai.GonzalezAlberquilla@arm.com rename_result.first->index(), 109512106SRekai.GonzalezAlberquilla@arm.com rename_result.first->flatIndex()); 10961062SN/A 10972292SN/A // Record the rename information so that a history can be kept. 109812106SRekai.GonzalezAlberquilla@arm.com RenameHistory hb_entry(inst->seqNum, flat_dest_regid, 10992292SN/A rename_result.first, 11002292SN/A rename_result.second); 11011062SN/A 11022292SN/A historyBuffer[tid].push_front(hb_entry); 11031062SN/A 11042935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11052935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11062935Sksewell@umich.edu historyBuffer[tid].size(), 11072292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11081062SN/A 11092292SN/A // Tell the instruction to rename the appropriate destination 11102292SN/A // register (dest_idx) to the new physical register 11112292SN/A // (rename_result.first), and record the previous physical 11122292SN/A // register that the same logical register was renamed to 11132292SN/A // (rename_result.second). 11142292SN/A inst->renameDestReg(dest_idx, 11152292SN/A rename_result.first, 11162292SN/A rename_result.second); 11171062SN/A 11182292SN/A ++renameRenamedOperands; 11191061SN/A } 11201061SN/A} 11211061SN/A 11221061SN/Atemplate <class Impl> 11231061SN/Ainline int 11246221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11251061SN/A{ 11262292SN/A int num_free = freeEntries[tid].robEntries - 11272292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11282292SN/A 11292292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11302292SN/A 11312292SN/A return num_free; 11321061SN/A} 11331061SN/A 11341061SN/Atemplate <class Impl> 11351061SN/Ainline int 11366221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11371061SN/A{ 11382292SN/A int num_free = freeEntries[tid].iqEntries - 11392292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11402292SN/A 11412292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11422292SN/A 11432292SN/A return num_free; 11442292SN/A} 11452292SN/A 11462292SN/Atemplate <class Impl> 11472292SN/Ainline int 114810239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11492292SN/A{ 115010239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 115110935Snilay@cs.wisc.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 115210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 115310239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 115410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 115510239Sbinhpham@cs.rutgers.edu return num_free; 115610239Sbinhpham@cs.rutgers.edu} 11572292SN/A 115810239Sbinhpham@cs.rutgers.edutemplate <class Impl> 115910239Sbinhpham@cs.rutgers.eduinline int 116010239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 116110239Sbinhpham@cs.rutgers.edu{ 116210239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 116310935Snilay@cs.wisc.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 116410239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 116510239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 116610239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 116710239Sbinhpham@cs.rutgers.edu return num_free; 11682292SN/A} 11692292SN/A 11702292SN/Atemplate <class Impl> 11712292SN/Aunsigned 11722292SN/ADefaultRename<Impl>::validInsts() 11732292SN/A{ 11742292SN/A unsigned inst_count = 0; 11752292SN/A 11762292SN/A for (int i=0; i<fromDecode->size; i++) { 11772731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11782292SN/A inst_count++; 11792292SN/A } 11802292SN/A 11812292SN/A return inst_count; 11822292SN/A} 11832292SN/A 11842292SN/Atemplate <class Impl> 11852292SN/Avoid 11866221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11872292SN/A{ 11882292SN/A if (fromIEW->iewBlock[tid]) { 11892292SN/A stalls[tid].iew = true; 11902292SN/A } 11912292SN/A 11922292SN/A if (fromIEW->iewUnblock[tid]) { 11932292SN/A assert(stalls[tid].iew); 11942292SN/A stalls[tid].iew = false; 11952292SN/A } 11962292SN/A} 11972292SN/A 11982292SN/Atemplate <class Impl> 11992292SN/Abool 12006221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12012292SN/A{ 12022292SN/A bool ret_val = false; 12032292SN/A 12042292SN/A if (stalls[tid].iew) { 12052292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12062292SN/A ret_val = true; 12072292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12082292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12092292SN/A ret_val = true; 12102292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12112292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12122292SN/A ret_val = true; 121310239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12142292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12152292SN/A ret_val = true; 12162292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12172292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12182292SN/A ret_val = true; 12192301SN/A } else if (renameStatus[tid] == SerializeStall && 12202292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12212301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12222292SN/A "empty.\n", 12232292SN/A tid); 12242292SN/A ret_val = true; 12252292SN/A } 12262292SN/A 12272292SN/A return ret_val; 12282292SN/A} 12292292SN/A 12302292SN/Atemplate <class Impl> 12312292SN/Avoid 12326221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12332292SN/A{ 12348607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12358607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12362292SN/A 123710239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 123810239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 123910239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 124010239Sbinhpham@cs.rutgers.edu } 12412292SN/A 12422292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12432292SN/A freeEntries[tid].robEntries = 12442292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12452292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12462292SN/A } 12472292SN/A 124810239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 124912109SRekai.GonzalezAlberquilla@arm.com "Free LQ: %i, Free SQ: %i, FreeRM %i(%i %i %i %i)\n", 12502292SN/A tid, 12512292SN/A freeEntries[tid].iqEntries, 12522292SN/A freeEntries[tid].robEntries, 125310239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 125412109SRekai.GonzalezAlberquilla@arm.com freeEntries[tid].sqEntries, 125512109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeEntries(), 125612109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeIntEntries(), 125712109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeFloatEntries(), 125812109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeVecEntries(), 125912109SRekai.GonzalezAlberquilla@arm.com renameMap[tid]->numFreeCCEntries()); 12602292SN/A 12612292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12622292SN/A tid, instsInProgress[tid]); 12632292SN/A} 12642292SN/A 12652292SN/Atemplate <class Impl> 12662292SN/Abool 12676221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12682292SN/A{ 12692292SN/A // Check if there's a squash signal, squash if there is 12702292SN/A // Check stall signals, block if necessary. 12712292SN/A // If status was blocked 12722292SN/A // check if stall conditions have passed 12732292SN/A // if so then go to unblocking 12742292SN/A // If status was Squashing 12752292SN/A // check if squashing is not high. Switch to running this cycle. 12762301SN/A // If status was serialize stall 12772292SN/A // check if ROB is empty and no insts are in flight to the ROB 12782292SN/A 12792292SN/A readFreeEntries(tid); 12802292SN/A readStallSignals(tid); 12812292SN/A 12822292SN/A if (fromCommit->commitInfo[tid].squash) { 12832292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12842292SN/A "commit.\n", tid); 12852292SN/A 12864632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12872292SN/A 12882292SN/A return true; 12892292SN/A } 12902292SN/A 12912292SN/A if (checkStall(tid)) { 12922292SN/A return block(tid); 12932292SN/A } 12942292SN/A 12952292SN/A if (renameStatus[tid] == Blocked) { 12962292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12972292SN/A tid); 12982292SN/A 12992292SN/A renameStatus[tid] = Unblocking; 13002292SN/A 13012292SN/A unblock(tid); 13022292SN/A 13032292SN/A return true; 13042292SN/A } 13052292SN/A 13062292SN/A if (renameStatus[tid] == Squashing) { 13072292SN/A // Switch status to running if rename isn't being told to block or 13082292SN/A // squash this cycle. 13093798Sgblack@eecs.umich.edu if (resumeSerialize) { 13103798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13113798Sgblack@eecs.umich.edu tid); 13122292SN/A 13133798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13143798Sgblack@eecs.umich.edu return true; 13153798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13163798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13173798Sgblack@eecs.umich.edu tid); 13183798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13193798Sgblack@eecs.umich.edu return true; 13203798Sgblack@eecs.umich.edu } else { 13213788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13223788Sgblack@eecs.umich.edu tid); 13232292SN/A 13243788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13253788Sgblack@eecs.umich.edu return false; 13263788Sgblack@eecs.umich.edu } 13272292SN/A } 13282292SN/A 13292301SN/A if (renameStatus[tid] == SerializeStall) { 13302292SN/A // Stall ends once the ROB is free. 13312301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13322292SN/A "unblocking.\n", tid); 13332292SN/A 13342301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13352292SN/A 13362292SN/A renameStatus[tid] = Unblocking; 13372292SN/A 13382292SN/A unblock(tid); 13392292SN/A 13402292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13417720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13422292SN/A 13432292SN/A // Put instruction into queue here. 13442301SN/A serial_inst->clearSerializeBefore(); 13452292SN/A 13462292SN/A if (!skidBuffer[tid].empty()) { 13472301SN/A skidBuffer[tid].push_front(serial_inst); 13482292SN/A } else { 13492301SN/A insts[tid].push_front(serial_inst); 13502292SN/A } 13512292SN/A 13522292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13532703Sktlim@umich.edu " Adding to front of list.\n", tid); 13542292SN/A 13552301SN/A serializeInst[tid] = NULL; 13562292SN/A 13572292SN/A return true; 13582292SN/A } 13592292SN/A 13602292SN/A // If we've reached this point, we have not gotten any signals that 13612292SN/A // cause rename to change its status. Rename remains the same as before. 13622292SN/A return false; 13631061SN/A} 13641061SN/A 13651060SN/Atemplate<class Impl> 13661060SN/Avoid 13676221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13681060SN/A{ 13692292SN/A if (inst_list.empty()) { 13702292SN/A // Mark a bit to say that I must serialize on the next instruction. 13712292SN/A serializeOnNextInst[tid] = true; 13721060SN/A return; 13731060SN/A } 13741060SN/A 13752292SN/A // Set the next instruction as serializing. 13762292SN/A inst_list.front()->setSerializeBefore(); 13772292SN/A} 13782292SN/A 13792292SN/Atemplate <class Impl> 13802292SN/Ainline void 13812292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13822292SN/A{ 13832292SN/A switch (source) { 13842292SN/A case ROB: 13852292SN/A ++renameROBFullEvents; 13862292SN/A break; 13872292SN/A case IQ: 13882292SN/A ++renameIQFullEvents; 13892292SN/A break; 139010239Sbinhpham@cs.rutgers.edu case LQ: 139110239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 139210239Sbinhpham@cs.rutgers.edu break; 139310239Sbinhpham@cs.rutgers.edu case SQ: 139410239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 13952292SN/A break; 13962292SN/A default: 13972292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13982292SN/A break; 13991060SN/A } 14002292SN/A} 14011060SN/A 14022292SN/Atemplate <class Impl> 14032292SN/Avoid 14042292SN/ADefaultRename<Impl>::dumpHistory() 14052292SN/A{ 14062980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14071060SN/A 14086221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14091060SN/A 14106221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14111060SN/A 14126221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 141312105Snathanael.premillieu@arm.com cprintf("Seq num: %i\nArch reg[%s]: %i New phys reg:" 141412105Snathanael.premillieu@arm.com " %i[%s] Old phys reg: %i[%s]\n", 141512105Snathanael.premillieu@arm.com (*buf_it).instSeqNum, 141612106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.className(), 141712106SRekai.GonzalezAlberquilla@arm.com (*buf_it).archReg.index(), 141812106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->index(), 141912106SRekai.GonzalezAlberquilla@arm.com (*buf_it).newPhysReg->className(), 142012106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->index(), 142112106SRekai.GonzalezAlberquilla@arm.com (*buf_it).prevPhysReg->className()); 14221060SN/A 14232292SN/A buf_it++; 14241062SN/A } 14251060SN/A } 14261060SN/A} 14279944Smatt.horsnell@ARM.com 14289944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1429