rename_impl.hh revision 10933
11689SN/A/* 210715SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2010-2012, 2014-2015 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 705529Snate@binkert.org numThreads(params->numThreads), 719920Syasuko.eckert@amd.com maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 729920Syasuko.eckert@amd.com + params->numPhysCCRegs) 731060SN/A{ 7410172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7510172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7710172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7810172Sdam.sunwoo@arm.com 792292SN/A // @todo: Make into a parameter. 8010328Smitch.hayenga@arm.com skidBufferMax = (decodeToRenameDelay + 1) * params->decodeWidth; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 842292SN/Astd::string 852292SN/ADefaultRename<Impl>::name() const 862292SN/A{ 872292SN/A return cpu->name() + ".rename"; 881060SN/A} 891060SN/A 901061SN/Atemplate <class Impl> 911060SN/Avoid 922292SN/ADefaultRename<Impl>::regStats() 931062SN/A{ 941062SN/A renameSquashCycles 958240Snate@binkert.org .name(name() + ".SquashCycles") 961062SN/A .desc("Number of cycles rename is squashing") 971062SN/A .prereq(renameSquashCycles); 981062SN/A renameIdleCycles 998240Snate@binkert.org .name(name() + ".IdleCycles") 1001062SN/A .desc("Number of cycles rename is idle") 1011062SN/A .prereq(renameIdleCycles); 1021062SN/A renameBlockCycles 1038240Snate@binkert.org .name(name() + ".BlockCycles") 1041062SN/A .desc("Number of cycles rename is blocking") 1051062SN/A .prereq(renameBlockCycles); 1062301SN/A renameSerializeStallCycles 1078240Snate@binkert.org .name(name() + ".serializeStallCycles") 1082301SN/A .desc("count of cycles rename stalled for serializing inst") 1092301SN/A .flags(Stats::total); 1102292SN/A renameRunCycles 1118240Snate@binkert.org .name(name() + ".RunCycles") 1122292SN/A .desc("Number of cycles rename is running") 1132292SN/A .prereq(renameIdleCycles); 1141062SN/A renameUnblockCycles 1158240Snate@binkert.org .name(name() + ".UnblockCycles") 1161062SN/A .desc("Number of cycles rename is unblocking") 1171062SN/A .prereq(renameUnblockCycles); 1181062SN/A renameRenamedInsts 1198240Snate@binkert.org .name(name() + ".RenamedInsts") 1201062SN/A .desc("Number of instructions processed by rename") 1211062SN/A .prereq(renameRenamedInsts); 1221062SN/A renameSquashedInsts 1238240Snate@binkert.org .name(name() + ".SquashedInsts") 1241062SN/A .desc("Number of squashed instructions processed by rename") 1251062SN/A .prereq(renameSquashedInsts); 1261062SN/A renameROBFullEvents 1278240Snate@binkert.org .name(name() + ".ROBFullEvents") 1282292SN/A .desc("Number of times rename has blocked due to ROB full") 1291062SN/A .prereq(renameROBFullEvents); 1301062SN/A renameIQFullEvents 1318240Snate@binkert.org .name(name() + ".IQFullEvents") 1322292SN/A .desc("Number of times rename has blocked due to IQ full") 1331062SN/A .prereq(renameIQFullEvents); 13410239Sbinhpham@cs.rutgers.edu renameLQFullEvents 13510239Sbinhpham@cs.rutgers.edu .name(name() + ".LQFullEvents") 13610239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to LQ full") 13710239Sbinhpham@cs.rutgers.edu .prereq(renameLQFullEvents); 13810239Sbinhpham@cs.rutgers.edu renameSQFullEvents 13910239Sbinhpham@cs.rutgers.edu .name(name() + ".SQFullEvents") 14010239Sbinhpham@cs.rutgers.edu .desc("Number of times rename has blocked due to SQ full") 14110239Sbinhpham@cs.rutgers.edu .prereq(renameSQFullEvents); 1421062SN/A renameFullRegistersEvents 1438240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1441062SN/A .desc("Number of times there has been no free registers") 1451062SN/A .prereq(renameFullRegistersEvents); 1461062SN/A renameRenamedOperands 1478240Snate@binkert.org .name(name() + ".RenamedOperands") 1481062SN/A .desc("Number of destination operands rename has renamed") 1491062SN/A .prereq(renameRenamedOperands); 1501062SN/A renameRenameLookups 1518240Snate@binkert.org .name(name() + ".RenameLookups") 1521062SN/A .desc("Number of register rename lookups that rename has made") 1531062SN/A .prereq(renameRenameLookups); 1541062SN/A renameCommittedMaps 1558240Snate@binkert.org .name(name() + ".CommittedMaps") 1561062SN/A .desc("Number of HB maps that are committed") 1571062SN/A .prereq(renameCommittedMaps); 1581062SN/A renameUndoneMaps 1598240Snate@binkert.org .name(name() + ".UndoneMaps") 1601062SN/A .desc("Number of HB maps that are undone due to squashing") 1611062SN/A .prereq(renameUndoneMaps); 1622301SN/A renamedSerializing 1638240Snate@binkert.org .name(name() + ".serializingInsts") 1642301SN/A .desc("count of serializing insts renamed") 1652301SN/A .flags(Stats::total) 1662301SN/A ; 1672301SN/A renamedTempSerializing 1688240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1692301SN/A .desc("count of temporary serializing insts renamed") 1702301SN/A .flags(Stats::total) 1712301SN/A ; 1722307SN/A renameSkidInsts 1738240Snate@binkert.org .name(name() + ".skidInsts") 1742307SN/A .desc("count of insts added to the skid buffer") 1752307SN/A .flags(Stats::total) 1762307SN/A ; 1777897Shestness@cs.utexas.edu intRenameLookups 1788240Snate@binkert.org .name(name() + ".int_rename_lookups") 1797897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1807897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1817897Shestness@cs.utexas.edu fpRenameLookups 1828240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1837897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1847897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1851062SN/A} 1861062SN/A 1871062SN/Atemplate <class Impl> 1881062SN/Avoid 1892292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1901060SN/A{ 1911060SN/A timeBuffer = tb_ptr; 1921060SN/A 1931060SN/A // Setup wire to read information from time buffer, from IEW stage. 1941060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1951060SN/A 1961060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1971060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1981060SN/A 1991060SN/A // Setup wire to write information to previous stages. 2001060SN/A toDecode = timeBuffer->getWire(0); 2011060SN/A} 2021060SN/A 2031061SN/Atemplate <class Impl> 2041060SN/Avoid 2052292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2061060SN/A{ 2071060SN/A renameQueue = rq_ptr; 2081060SN/A 2091060SN/A // Setup wire to write information to future stages. 2101060SN/A toIEW = renameQueue->getWire(0); 2111060SN/A} 2121060SN/A 2131061SN/Atemplate <class Impl> 2141060SN/Avoid 2152292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2161060SN/A{ 2171060SN/A decodeQueue = dq_ptr; 2181060SN/A 2191060SN/A // Setup wire to get information from decode. 2201060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2211060SN/A} 2221060SN/A 2231061SN/Atemplate <class Impl> 2241060SN/Avoid 2259427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2261060SN/A{ 2279444SAndreas.Sandberg@ARM.com resetStage(); 2289444SAndreas.Sandberg@ARM.com} 2299444SAndreas.Sandberg@ARM.com 2309444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2319444SAndreas.Sandberg@ARM.comvoid 2329444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2339444SAndreas.Sandberg@ARM.com{ 2349444SAndreas.Sandberg@ARM.com _status = Inactive; 2359444SAndreas.Sandberg@ARM.com 2369444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2379444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2389444SAndreas.Sandberg@ARM.com 2392329SN/A // Grab the number of free entries directly from the stages. 2406221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2419444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2429444SAndreas.Sandberg@ARM.com 2432292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 24410239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = iew_ptr->ldstQueue.numFreeLoadEntries(tid); 24510239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = iew_ptr->ldstQueue.numFreeStoreEntries(tid); 2462292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2472292SN/A emptyROB[tid] = true; 2489444SAndreas.Sandberg@ARM.com 2499444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2509444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2519444SAndreas.Sandberg@ARM.com 2529444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 25310239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] = 0; 25410239Sbinhpham@cs.rutgers.edu storesInProgress[tid] = 0; 2559444SAndreas.Sandberg@ARM.com 2569444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2572292SN/A } 2581060SN/A} 2591060SN/A 2602292SN/Atemplate<class Impl> 2612292SN/Avoid 2626221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2632292SN/A{ 2642292SN/A activeThreads = at_ptr; 2652292SN/A} 2662292SN/A 2672292SN/A 2681061SN/Atemplate <class Impl> 2691060SN/Avoid 2702292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2711060SN/A{ 2726221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2736221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2741060SN/A} 2751060SN/A 2761061SN/Atemplate <class Impl> 2771060SN/Avoid 2782292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2791060SN/A{ 2802292SN/A freeList = fl_ptr; 2812292SN/A} 2821060SN/A 2832292SN/Atemplate<class Impl> 2842292SN/Avoid 2852292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2862292SN/A{ 2872292SN/A scoreboard = _scoreboard; 2881060SN/A} 2891060SN/A 2901061SN/Atemplate <class Impl> 2912863Sktlim@umich.edubool 2929444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 2931060SN/A{ 2949444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2959444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 2969444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 2979444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 2989444SAndreas.Sandberg@ARM.com !insts[tid].empty()) 2999444SAndreas.Sandberg@ARM.com return false; 3009444SAndreas.Sandberg@ARM.com } 3012863Sktlim@umich.edu return true; 3022316SN/A} 3031060SN/A 3042316SN/Atemplate <class Impl> 3052316SN/Avoid 3062307SN/ADefaultRename<Impl>::takeOverFrom() 3071060SN/A{ 3089444SAndreas.Sandberg@ARM.com resetStage(); 3099444SAndreas.Sandberg@ARM.com} 3101060SN/A 3119444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3129444SAndreas.Sandberg@ARM.comvoid 3139444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3149444SAndreas.Sandberg@ARM.com{ 3156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3169444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3179444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3189444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3199444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3202307SN/A } 3212307SN/A} 3222307SN/A 3232307SN/Atemplate <class Impl> 3242307SN/Avoid 3256221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3261858SN/A{ 3272292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3281858SN/A 3292292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3302292SN/A // If it still needs to block, the blocking should happen the next 3312292SN/A // cycle and there should be space to hold everything due to the squash. 3322292SN/A if (renameStatus[tid] == Blocked || 3333788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3342292SN/A toDecode->renameUnblock[tid] = 1; 3352698Sktlim@umich.edu 3363788Sgblack@eecs.umich.edu resumeSerialize = false; 3372301SN/A serializeInst[tid] = NULL; 3383788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3393788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3403788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3413788Sgblack@eecs.umich.edu resumeSerialize = true; 3423788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3433788Sgblack@eecs.umich.edu } else { 3443788Sgblack@eecs.umich.edu resumeSerialize = false; 3453788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3463788Sgblack@eecs.umich.edu 3473788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3483788Sgblack@eecs.umich.edu } 3492292SN/A } 3502292SN/A 3512292SN/A // Set the status to Squashing. 3522292SN/A renameStatus[tid] = Squashing; 3532292SN/A 3542329SN/A // Squash any instructions from decode. 3552292SN/A for (int i=0; i<fromDecode->size; i++) { 3562935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3572935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3582731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3592292SN/A wroteToTimeBuffer = true; 3602292SN/A } 3612935Sksewell@umich.edu 3622292SN/A } 3632292SN/A 3642935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3654632Sgblack@eecs.umich.edu // insts in them. 3663093Sksewell@umich.edu insts[tid].clear(); 3672292SN/A 3682292SN/A // Clear the skid buffer in case it has any data in it. 3693093Sksewell@umich.edu skidBuffer[tid].clear(); 3704632Sgblack@eecs.umich.edu 3712935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3722292SN/A} 3732292SN/A 3742292SN/Atemplate <class Impl> 3752292SN/Avoid 3762292SN/ADefaultRename<Impl>::tick() 3772292SN/A{ 3782292SN/A wroteToTimeBuffer = false; 3792292SN/A 3802292SN/A blockThisCycle = false; 3812292SN/A 3822292SN/A bool status_change = false; 3832292SN/A 3842292SN/A toIEWIndex = 0; 3852292SN/A 3862292SN/A sortInsts(); 3872292SN/A 3886221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3896221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3902292SN/A 3912292SN/A // Check stall and squash signals. 3923867Sbinkertn@umich.edu while (threads != end) { 3936221Snate@binkert.org ThreadID tid = *threads++; 3942292SN/A 3952292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3962292SN/A 3972292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3982292SN/A 3992292SN/A rename(status_change, tid); 4002292SN/A } 4012292SN/A 4022292SN/A if (status_change) { 4032292SN/A updateStatus(); 4042292SN/A } 4052292SN/A 4062292SN/A if (wroteToTimeBuffer) { 4072292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4082292SN/A cpu->activityThisCycle(); 4092292SN/A } 4102292SN/A 4113867Sbinkertn@umich.edu threads = activeThreads->begin(); 4122292SN/A 4133867Sbinkertn@umich.edu while (threads != end) { 4146221Snate@binkert.org ThreadID tid = *threads++; 4152292SN/A 4162292SN/A // If we committed this cycle then doneSeqNum will be > 0 4172292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4182292SN/A !fromCommit->commitInfo[tid].squash && 4192292SN/A renameStatus[tid] != Squashing) { 4202292SN/A 4212292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4222292SN/A tid); 4232292SN/A } 4242292SN/A } 4252292SN/A 4262292SN/A // @todo: make into updateProgress function 4276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4282292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 42910239Sbinhpham@cs.rutgers.edu loadsInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToLQ; 43010239Sbinhpham@cs.rutgers.edu storesInProgress[tid] -= fromIEW->iewInfo[tid].dispatchedToSQ; 43110239Sbinhpham@cs.rutgers.edu assert(loadsInProgress[tid] >= 0); 43210239Sbinhpham@cs.rutgers.edu assert(storesInProgress[tid] >= 0); 4332292SN/A assert(instsInProgress[tid] >=0); 4342292SN/A } 4352292SN/A 4362292SN/A} 4372292SN/A 4382292SN/Atemplate<class Impl> 4392292SN/Avoid 4406221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4412292SN/A{ 4422292SN/A // If status is Running or idle, 4432292SN/A // call renameInsts() 4442292SN/A // If status is Unblocking, 4452292SN/A // buffer any instructions coming from decode 4462292SN/A // continue trying to empty skid buffer 4472292SN/A // check if stall conditions have passed 4482292SN/A 4492292SN/A if (renameStatus[tid] == Blocked) { 4502292SN/A ++renameBlockCycles; 4512292SN/A } else if (renameStatus[tid] == Squashing) { 4522292SN/A ++renameSquashCycles; 4532301SN/A } else if (renameStatus[tid] == SerializeStall) { 4542301SN/A ++renameSerializeStallCycles; 4553788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4563788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4573788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4583788Sgblack@eecs.umich.edu if (resumeSerialize) { 4593788Sgblack@eecs.umich.edu resumeSerialize = false; 4603788Sgblack@eecs.umich.edu block(tid); 4613788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4623788Sgblack@eecs.umich.edu } 4633798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4643798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4653798Sgblack@eecs.umich.edu block(tid); 4663798Sgblack@eecs.umich.edu resumeUnblocking = false; 4673798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4683798Sgblack@eecs.umich.edu } 4692292SN/A } 4702292SN/A 4712292SN/A if (renameStatus[tid] == Running || 4722292SN/A renameStatus[tid] == Idle) { 4732292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4742292SN/A "stage.\n", tid); 4752292SN/A 4762292SN/A renameInsts(tid); 4772292SN/A } else if (renameStatus[tid] == Unblocking) { 4782292SN/A renameInsts(tid); 4792292SN/A 4802292SN/A if (validInsts()) { 4812292SN/A // Add the current inputs to the skid buffer so they can be 4822292SN/A // reprocessed when this stage unblocks. 4832292SN/A skidInsert(tid); 4842292SN/A } 4852292SN/A 4862292SN/A // If we switched over to blocking, then there's a potential for 4872292SN/A // an overall status change. 4882292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4891858SN/A } 4901858SN/A} 4911858SN/A 4921858SN/Atemplate <class Impl> 4931858SN/Avoid 4946221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4951858SN/A{ 4962292SN/A // Instructions can be either in the skid buffer or the queue of 4972292SN/A // instructions coming from decode, depending on the status. 4982292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4992292SN/A skidBuffer[tid].size() : insts[tid].size(); 5001858SN/A 5012292SN/A // Check the decode queue to see if instructions are available. 5022292SN/A // If there are no available instructions to rename, then do nothing. 5032292SN/A if (insts_available == 0) { 5042292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 5052292SN/A tid); 5062292SN/A // Should I change status to idle? 5072292SN/A ++renameIdleCycles; 5082292SN/A return; 5092292SN/A } else if (renameStatus[tid] == Unblocking) { 5102292SN/A ++renameUnblockCycles; 5112292SN/A } else if (renameStatus[tid] == Running) { 5122292SN/A ++renameRunCycles; 5132292SN/A } 5141858SN/A 5152292SN/A DynInstPtr inst; 5162292SN/A 5172292SN/A // Will have to do a different calculation for the number of free 5182292SN/A // entries. 5192292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5202292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5212292SN/A int min_free_entries = free_rob_entries; 5222292SN/A 5232292SN/A FullSource source = ROB; 5242292SN/A 5252292SN/A if (free_iq_entries < min_free_entries) { 5262292SN/A min_free_entries = free_iq_entries; 5272292SN/A source = IQ; 5282292SN/A } 5292292SN/A 5302292SN/A // Check if there's any space left. 5312292SN/A if (min_free_entries <= 0) { 53210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/ " 5332292SN/A "entries.\n" 5342292SN/A "ROB has %i free entries.\n" 53510239Sbinhpham@cs.rutgers.edu "IQ has %i free entries.\n", 5362292SN/A tid, 5372292SN/A free_rob_entries, 53810239Sbinhpham@cs.rutgers.edu free_iq_entries); 5392292SN/A 5402292SN/A blockThisCycle = true; 5412292SN/A 5422292SN/A block(tid); 5432292SN/A 5442292SN/A incrFullStat(source); 5452292SN/A 5462292SN/A return; 5472292SN/A } else if (min_free_entries < insts_available) { 5482292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5492292SN/A "%i insts available, but only %i insts can be " 5502292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5512292SN/A tid, insts_available, min_free_entries); 5522292SN/A 5532292SN/A insts_available = min_free_entries; 5542292SN/A 5552292SN/A blockThisCycle = true; 5562292SN/A 5572292SN/A incrFullStat(source); 5582292SN/A } 5592292SN/A 5602292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5612292SN/A skidBuffer[tid] : insts[tid]; 5622292SN/A 5632292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5642292SN/A "send iew.\n", tid, insts_available); 5652292SN/A 5662292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5672292SN/A "dispatched to IQ last cycle.\n", 5682292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5692292SN/A 5702292SN/A // Handle serializing the next instruction if necessary. 5712292SN/A if (serializeOnNextInst[tid]) { 5722292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5732292SN/A // ROB already empty; no need to serialize. 5742292SN/A serializeOnNextInst[tid] = false; 5752292SN/A } else if (!insts_to_rename.empty()) { 5762292SN/A insts_to_rename.front()->setSerializeBefore(); 5772292SN/A } 5782292SN/A } 5792292SN/A 5802292SN/A int renamed_insts = 0; 5812292SN/A 5822292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5832292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5842292SN/A 5852292SN/A assert(!insts_to_rename.empty()); 5862292SN/A 5872292SN/A inst = insts_to_rename.front(); 5882292SN/A 58910239Sbinhpham@cs.rutgers.edu //For all kind of instructions, check ROB and IQ first 59010239Sbinhpham@cs.rutgers.edu //For load instruction, check LQ size and take into account the inflight loads 59110239Sbinhpham@cs.rutgers.edu //For store instruction, check SQ size and take into account the inflight stores 59210239Sbinhpham@cs.rutgers.edu 59310239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 59410933Snilay@cs.wisc.edu if (calcFreeLQEntries(tid) <= 0) { 59510933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free LQ\n"); 59610933Snilay@cs.wisc.edu source = LQ; 59710933Snilay@cs.wisc.edu incrFullStat(source); 59810933Snilay@cs.wisc.edu break; 59910933Snilay@cs.wisc.edu } 60010239Sbinhpham@cs.rutgers.edu } 60110239Sbinhpham@cs.rutgers.edu 60210239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 60310933Snilay@cs.wisc.edu if (calcFreeSQEntries(tid) <= 0) { 60410933Snilay@cs.wisc.edu DPRINTF(Rename, "[tid:%u]: Cannot rename due to no free SQ\n"); 60510933Snilay@cs.wisc.edu source = SQ; 60610933Snilay@cs.wisc.edu incrFullStat(source); 60710933Snilay@cs.wisc.edu break; 60810933Snilay@cs.wisc.edu } 60910239Sbinhpham@cs.rutgers.edu } 61010239Sbinhpham@cs.rutgers.edu 6112292SN/A insts_to_rename.pop_front(); 6122292SN/A 6132292SN/A if (renameStatus[tid] == Unblocking) { 6147720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 6157720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 6162292SN/A } 6172292SN/A 6182292SN/A if (inst->isSquashed()) { 6197720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 6207720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 6217720Sgblack@eecs.umich.edu inst->pcState()); 6222292SN/A 6232292SN/A ++renameSquashedInsts; 6242292SN/A 6252292SN/A // Decrement how many instructions are available. 6262292SN/A --insts_available; 6272292SN/A 6282292SN/A continue; 6292292SN/A } 6302292SN/A 6312292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6327720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6332292SN/A 6349531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6359531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 63610715SRekai.GonzalezAlberquilla@arm.com if (!renameMap[tid]->canRename(inst->numIntDestRegs(), 63710715SRekai.GonzalezAlberquilla@arm.com inst->numFPDestRegs(), 63810715SRekai.GonzalezAlberquilla@arm.com inst->numCCDestRegs())) { 6399531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6409531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6419531Sgeoffrey.blake@arm.com blockThisCycle = true; 6429531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6439531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6449531Sgeoffrey.blake@arm.com 6459531Sgeoffrey.blake@arm.com break; 6469531Sgeoffrey.blake@arm.com } 6479531Sgeoffrey.blake@arm.com 6482292SN/A // Handle serializeAfter/serializeBefore instructions. 6492292SN/A // serializeAfter marks the next instruction as serializeBefore. 6502292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6512292SN/A // is empty. 6522336SN/A 6532336SN/A // In this model, IPR accesses are serialize before 6542336SN/A // instructions, and store conditionals are serialize after 6552336SN/A // instructions. This is mainly due to lack of support for 6562336SN/A // out-of-order operations of either of those classes of 6572336SN/A // instructions. 6582336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6592336SN/A !inst->isSerializeHandled()) { 6602292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6612292SN/A 6622301SN/A if (!inst->isTempSerializeBefore()) { 6632301SN/A renamedSerializing++; 6642292SN/A inst->setSerializeHandled(); 6652301SN/A } else { 6662301SN/A renamedTempSerializing++; 6672301SN/A } 6682292SN/A 6692301SN/A // Change status over to SerializeStall so that other stages know 6702292SN/A // what this is blocked on. 6712301SN/A renameStatus[tid] = SerializeStall; 6722292SN/A 6732301SN/A serializeInst[tid] = inst; 6742292SN/A 6752292SN/A blockThisCycle = true; 6762292SN/A 6772292SN/A break; 6782336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6792336SN/A !inst->isSerializeHandled()) { 6802292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6812292SN/A 6822307SN/A renamedSerializing++; 6832307SN/A 6842292SN/A inst->setSerializeHandled(); 6852292SN/A 6862292SN/A serializeAfter(insts_to_rename, tid); 6872292SN/A } 6882292SN/A 6892292SN/A renameSrcRegs(inst, inst->threadNumber); 6902292SN/A 6912292SN/A renameDestRegs(inst, inst->threadNumber); 6922292SN/A 69310239Sbinhpham@cs.rutgers.edu if (inst->isLoad()) { 69410239Sbinhpham@cs.rutgers.edu loadsInProgress[tid]++; 69510239Sbinhpham@cs.rutgers.edu } 69610239Sbinhpham@cs.rutgers.edu if (inst->isStore()) { 69710239Sbinhpham@cs.rutgers.edu storesInProgress[tid]++; 69810239Sbinhpham@cs.rutgers.edu } 6992292SN/A ++renamed_insts; 7002292SN/A 7018471SGiacomo.Gabrielli@arm.com 7022292SN/A // Put instruction in rename queue. 7032292SN/A toIEW->insts[toIEWIndex] = inst; 7042292SN/A ++(toIEW->size); 7052292SN/A 7062292SN/A // Increment which instruction we're on. 7072292SN/A ++toIEWIndex; 7082292SN/A 7092292SN/A // Decrement how many instructions are available. 7102292SN/A --insts_available; 7112292SN/A } 7122292SN/A 7132292SN/A instsInProgress[tid] += renamed_insts; 7142307SN/A renameRenamedInsts += renamed_insts; 7152292SN/A 7162292SN/A // If we wrote to the time buffer, record this. 7172292SN/A if (toIEWIndex) { 7182292SN/A wroteToTimeBuffer = true; 7192292SN/A } 7202292SN/A 7212292SN/A // Check if there's any instructions left that haven't yet been renamed. 7222292SN/A // If so then block. 7232292SN/A if (insts_available) { 7242292SN/A blockThisCycle = true; 7252292SN/A } 7262292SN/A 7272292SN/A if (blockThisCycle) { 7282292SN/A block(tid); 7292292SN/A toDecode->renameUnblock[tid] = false; 7302292SN/A } 7312292SN/A} 7322292SN/A 7332292SN/Atemplate<class Impl> 7342292SN/Avoid 7356221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7362292SN/A{ 7372292SN/A DynInstPtr inst = NULL; 7382292SN/A 7392292SN/A while (!insts[tid].empty()) { 7402292SN/A inst = insts[tid].front(); 7412292SN/A 7422292SN/A insts[tid].pop_front(); 7432292SN/A 7442292SN/A assert(tid == inst->threadNumber); 7452292SN/A 7467720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7477720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7482292SN/A 7492307SN/A ++renameSkidInsts; 7502307SN/A 7512292SN/A skidBuffer[tid].push_back(inst); 7522292SN/A } 7532292SN/A 7542292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7553798Sgblack@eecs.umich.edu { 7563798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7573798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7583798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7593798Sgblack@eecs.umich.edu { 7603798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7617720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7623798Sgblack@eecs.umich.edu (*it)->seqNum); 7633798Sgblack@eecs.umich.edu } 7642292SN/A panic("Skidbuffer Exceeded Max Size"); 7653798Sgblack@eecs.umich.edu } 7662292SN/A} 7672292SN/A 7682292SN/Atemplate <class Impl> 7692292SN/Avoid 7702292SN/ADefaultRename<Impl>::sortInsts() 7712292SN/A{ 7722292SN/A int insts_from_decode = fromDecode->size; 7732292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7742292SN/A DynInstPtr inst = fromDecode->insts[i]; 7752292SN/A insts[inst->threadNumber].push_back(inst); 7769527SMatt.Horsnell@arm.com#if TRACING_ON 7779527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7789527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7799527SMatt.Horsnell@arm.com } 7809527SMatt.Horsnell@arm.com#endif 7812292SN/A } 7822292SN/A} 7832292SN/A 7842292SN/Atemplate<class Impl> 7852292SN/Abool 7862292SN/ADefaultRename<Impl>::skidsEmpty() 7872292SN/A{ 7886221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7896221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7902292SN/A 7913867Sbinkertn@umich.edu while (threads != end) { 7926221Snate@binkert.org ThreadID tid = *threads++; 7933867Sbinkertn@umich.edu 7943867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7952292SN/A return false; 7962292SN/A } 7972292SN/A 7982292SN/A return true; 7992292SN/A} 8002292SN/A 8012292SN/Atemplate<class Impl> 8022292SN/Avoid 8032292SN/ADefaultRename<Impl>::updateStatus() 8042292SN/A{ 8052292SN/A bool any_unblocking = false; 8062292SN/A 8076221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 8086221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 8092292SN/A 8103867Sbinkertn@umich.edu while (threads != end) { 8116221Snate@binkert.org ThreadID tid = *threads++; 8122292SN/A 8132292SN/A if (renameStatus[tid] == Unblocking) { 8142292SN/A any_unblocking = true; 8152292SN/A break; 8162292SN/A } 8172292SN/A } 8182292SN/A 8192292SN/A // Rename will have activity if it's unblocking. 8202292SN/A if (any_unblocking) { 8212292SN/A if (_status == Inactive) { 8222292SN/A _status = Active; 8232292SN/A 8242292SN/A DPRINTF(Activity, "Activating stage.\n"); 8252292SN/A 8262733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 8272292SN/A } 8282292SN/A } else { 8292292SN/A // If it's not unblocking, then rename will not have any internal 8302292SN/A // activity. Switch it to inactive. 8312292SN/A if (_status == Active) { 8322292SN/A _status = Inactive; 8332292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8342292SN/A 8352733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8362292SN/A } 8372292SN/A } 8382292SN/A} 8392292SN/A 8402292SN/Atemplate <class Impl> 8412292SN/Abool 8426221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8432292SN/A{ 8442292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8452292SN/A 8462292SN/A // Add the current inputs onto the skid buffer, so they can be 8472292SN/A // reprocessed when this stage unblocks. 8482292SN/A skidInsert(tid); 8492292SN/A 8502292SN/A // Only signal backwards to block if the previous stages do not think 8512292SN/A // rename is already blocked. 8522292SN/A if (renameStatus[tid] != Blocked) { 8533798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8543798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8553798Sgblack@eecs.umich.edu // stages to block. 8563798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8572292SN/A toDecode->renameBlock[tid] = true; 8582292SN/A toDecode->renameUnblock[tid] = false; 8592292SN/A wroteToTimeBuffer = true; 8602292SN/A } 8612292SN/A 8622329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8632329SN/A // it would not know to complete the serialize stall. 8642301SN/A if (renameStatus[tid] != SerializeStall) { 8652292SN/A // Set status to Blocked. 8662292SN/A renameStatus[tid] = Blocked; 8672292SN/A return true; 8682292SN/A } 8692292SN/A } 8702292SN/A 8712292SN/A return false; 8722292SN/A} 8732292SN/A 8742292SN/Atemplate <class Impl> 8752292SN/Abool 8766221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8772292SN/A{ 8782292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8792292SN/A 8802292SN/A // Rename is done unblocking if the skid buffer is empty. 8812301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8822292SN/A 8832292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8842292SN/A 8852292SN/A toDecode->renameUnblock[tid] = true; 8862292SN/A wroteToTimeBuffer = true; 8872292SN/A 8882292SN/A renameStatus[tid] = Running; 8892292SN/A return true; 8902292SN/A } 8912292SN/A 8922292SN/A return false; 8932292SN/A} 8942292SN/A 8952292SN/Atemplate <class Impl> 8962292SN/Avoid 8976221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8982292SN/A{ 8992980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9002980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 9012292SN/A 9021060SN/A // After a syscall squashes everything, the history buffer may be empty 9031060SN/A // but the ROB may still be squashing instructions. 9042292SN/A if (historyBuffer[tid].empty()) { 9051060SN/A return; 9061060SN/A } 9071060SN/A 9081060SN/A // Go through the most recent instructions, undoing the mappings 9091060SN/A // they did and freeing up the registers. 9102292SN/A while (!historyBuffer[tid].empty() && 9119919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 9122292SN/A assert(hb_it != historyBuffer[tid].end()); 9131062SN/A 9142292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 9159919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 9161060SN/A 9179919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 9189919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 9199919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 9209919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 9219919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 9229919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 9239919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9249919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 9259919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 9269919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 9271060SN/A 9289919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 9299919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 9309919Ssteve.reinhardt@amd.com } 9311062SN/A 9322292SN/A historyBuffer[tid].erase(hb_it++); 9331061SN/A 9341062SN/A ++renameUndoneMaps; 9351060SN/A } 9361060SN/A} 9371060SN/A 9381060SN/Atemplate<class Impl> 9391060SN/Avoid 9406221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9411060SN/A{ 9422292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9432292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9442292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9452292SN/A 9462980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9472980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9481060SN/A 9491061SN/A --hb_it; 9501060SN/A 9512292SN/A if (historyBuffer[tid].empty()) { 9522292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9532292SN/A return; 9542292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9552292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9562292SN/A "that a syscall happened recently.\n", tid); 9571060SN/A return; 9581060SN/A } 9591060SN/A 9602292SN/A // Commit all the renames up until (and including) the committed sequence 9612292SN/A // number. Some or even all of the committed instructions may not have 9622292SN/A // rename histories if they did not have destination registers that were 9632292SN/A // renamed. 9642292SN/A while (!historyBuffer[tid].empty() && 9652292SN/A hb_it != historyBuffer[tid].end() && 9669919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9671060SN/A 9682329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9692329SN/A "[sn:%lli].\n", 9709919Ssteve.reinhardt@amd.com tid, hb_it->prevPhysReg, hb_it->instSeqNum); 9711061SN/A 9729919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 9739919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 9749919Ssteve.reinhardt@amd.com // the old one. 9759919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9769919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 9779919Ssteve.reinhardt@amd.com } 9789919Ssteve.reinhardt@amd.com 9792292SN/A ++renameCommittedMaps; 9801061SN/A 9812292SN/A historyBuffer[tid].erase(hb_it--); 9821060SN/A } 9831060SN/A} 9841060SN/A 9851061SN/Atemplate <class Impl> 9861061SN/Ainline void 9876221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9881061SN/A{ 9899919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 9909919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 9911061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9921061SN/A 9931061SN/A // Get the architectual register numbers from the source and 9949919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 9952292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9961061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9979919Ssteve.reinhardt@amd.com RegIndex rel_src_reg; 9989919Ssteve.reinhardt@amd.com RegIndex flat_rel_src_reg; 9999919Ssteve.reinhardt@amd.com PhysRegIndex renamed_reg; 10009919Ssteve.reinhardt@amd.com 10019919Ssteve.reinhardt@amd.com switch (regIdxToClass(src_reg, &rel_src_reg)) { 10029913Ssteve.reinhardt@amd.com case IntRegClass: 10039919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 10049919Ssteve.reinhardt@amd.com renamed_reg = map->lookupInt(flat_rel_src_reg); 10059919Ssteve.reinhardt@amd.com intRenameLookups++; 10069913Ssteve.reinhardt@amd.com break; 10079913Ssteve.reinhardt@amd.com 10089913Ssteve.reinhardt@amd.com case FloatRegClass: 10099919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 10109919Ssteve.reinhardt@amd.com renamed_reg = map->lookupFloat(flat_rel_src_reg); 10119919Ssteve.reinhardt@amd.com fpRenameLookups++; 10129913Ssteve.reinhardt@amd.com break; 10139913Ssteve.reinhardt@amd.com 10149920Syasuko.eckert@amd.com case CCRegClass: 10159920Syasuko.eckert@amd.com flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 10169920Syasuko.eckert@amd.com renamed_reg = map->lookupCC(flat_rel_src_reg); 10179920Syasuko.eckert@amd.com break; 10189920Syasuko.eckert@amd.com 10199913Ssteve.reinhardt@amd.com case MiscRegClass: 10209919Ssteve.reinhardt@amd.com // misc regs don't get flattened 10219919Ssteve.reinhardt@amd.com flat_rel_src_reg = rel_src_reg; 10229919Ssteve.reinhardt@amd.com renamed_reg = map->lookupMisc(flat_rel_src_reg); 10239913Ssteve.reinhardt@amd.com break; 10249913Ssteve.reinhardt@amd.com 10259913Ssteve.reinhardt@amd.com default: 10267649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 10273773Sgblack@eecs.umich.edu } 10284352Sgblack@eecs.umich.edu 10299919Ssteve.reinhardt@amd.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 10309919Ssteve.reinhardt@amd.com "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 10319919Ssteve.reinhardt@amd.com (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 10321061SN/A 10331061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10341061SN/A 10352292SN/A // See if the register is ready or not. 10369919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 10377767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10387767Sgblack@eecs.umich.edu tid, renamed_reg); 10391061SN/A 10401061SN/A inst->markSrcRegReady(src_idx); 10414636Sgblack@eecs.umich.edu } else { 10427767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10437767Sgblack@eecs.umich.edu tid, renamed_reg); 10441061SN/A } 10451062SN/A 10461062SN/A ++renameRenameLookups; 10471061SN/A } 10481061SN/A} 10491061SN/A 10501061SN/Atemplate <class Impl> 10511061SN/Ainline void 10526221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10531061SN/A{ 10549919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10559919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10561061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10571061SN/A 10582292SN/A // Rename the destination registers. 10592292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10602292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10619919Ssteve.reinhardt@amd.com RegIndex rel_dest_reg; 10629919Ssteve.reinhardt@amd.com RegIndex flat_rel_dest_reg; 10639919Ssteve.reinhardt@amd.com RegIndex flat_uni_dest_reg; 10649919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10659919Ssteve.reinhardt@amd.com 10669919Ssteve.reinhardt@amd.com switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 10679913Ssteve.reinhardt@amd.com case IntRegClass: 10689919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 10699919Ssteve.reinhardt@amd.com rename_result = map->renameInt(flat_rel_dest_reg); 10709919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 10719913Ssteve.reinhardt@amd.com break; 10729913Ssteve.reinhardt@amd.com 10739913Ssteve.reinhardt@amd.com case FloatRegClass: 10749919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 10759919Ssteve.reinhardt@amd.com rename_result = map->renameFloat(flat_rel_dest_reg); 10769919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 10779913Ssteve.reinhardt@amd.com break; 10789913Ssteve.reinhardt@amd.com 10799920Syasuko.eckert@amd.com case CCRegClass: 10809920Syasuko.eckert@amd.com flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 10819920Syasuko.eckert@amd.com rename_result = map->renameCC(flat_rel_dest_reg); 10829920Syasuko.eckert@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 10839920Syasuko.eckert@amd.com break; 10849920Syasuko.eckert@amd.com 10859913Ssteve.reinhardt@amd.com case MiscRegClass: 10869919Ssteve.reinhardt@amd.com // misc regs don't get flattened 10879919Ssteve.reinhardt@amd.com flat_rel_dest_reg = rel_dest_reg; 10889919Ssteve.reinhardt@amd.com rename_result = map->renameMisc(flat_rel_dest_reg); 10899919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 10909913Ssteve.reinhardt@amd.com break; 10919913Ssteve.reinhardt@amd.com 10929913Ssteve.reinhardt@amd.com default: 10937649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10943773Sgblack@eecs.umich.edu } 10953773Sgblack@eecs.umich.edu 10969919Ssteve.reinhardt@amd.com inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 10971061SN/A 10989919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 10999916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 11001062SN/A 11012292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 11029919Ssteve.reinhardt@amd.com "reg %i.\n", tid, (int)flat_rel_dest_reg, 11032292SN/A (int)rename_result.first); 11041062SN/A 11052292SN/A // Record the rename information so that a history can be kept. 11069919Ssteve.reinhardt@amd.com RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 11072292SN/A rename_result.first, 11082292SN/A rename_result.second); 11091062SN/A 11102292SN/A historyBuffer[tid].push_front(hb_entry); 11111062SN/A 11122935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 11132935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 11142935Sksewell@umich.edu historyBuffer[tid].size(), 11152292SN/A (*historyBuffer[tid].begin()).instSeqNum); 11161062SN/A 11172292SN/A // Tell the instruction to rename the appropriate destination 11182292SN/A // register (dest_idx) to the new physical register 11192292SN/A // (rename_result.first), and record the previous physical 11202292SN/A // register that the same logical register was renamed to 11212292SN/A // (rename_result.second). 11222292SN/A inst->renameDestReg(dest_idx, 11232292SN/A rename_result.first, 11242292SN/A rename_result.second); 11251062SN/A 11262292SN/A ++renameRenamedOperands; 11271061SN/A } 11281061SN/A} 11291061SN/A 11301061SN/Atemplate <class Impl> 11311061SN/Ainline int 11326221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11331061SN/A{ 11342292SN/A int num_free = freeEntries[tid].robEntries - 11352292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11362292SN/A 11372292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11382292SN/A 11392292SN/A return num_free; 11401061SN/A} 11411061SN/A 11421061SN/Atemplate <class Impl> 11431061SN/Ainline int 11446221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11451061SN/A{ 11462292SN/A int num_free = freeEntries[tid].iqEntries - 11472292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11482292SN/A 11492292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11502292SN/A 11512292SN/A return num_free; 11522292SN/A} 11532292SN/A 11542292SN/Atemplate <class Impl> 11552292SN/Ainline int 115610239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeLQEntries(ThreadID tid) 11572292SN/A{ 115810239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].lqEntries - 115910239Sbinhpham@cs.rutgers.edu (loadsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLQ); 116010239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeLQEntries: free lqEntries: %d, loadsInProgress: %d, " 116110239Sbinhpham@cs.rutgers.edu "loads dispatchedToLQ: %d\n", freeEntries[tid].lqEntries, 116210239Sbinhpham@cs.rutgers.edu loadsInProgress[tid], fromIEW->iewInfo[tid].dispatchedToLQ); 116310239Sbinhpham@cs.rutgers.edu return num_free; 116410239Sbinhpham@cs.rutgers.edu} 11652292SN/A 116610239Sbinhpham@cs.rutgers.edutemplate <class Impl> 116710239Sbinhpham@cs.rutgers.eduinline int 116810239Sbinhpham@cs.rutgers.eduDefaultRename<Impl>::calcFreeSQEntries(ThreadID tid) 116910239Sbinhpham@cs.rutgers.edu{ 117010239Sbinhpham@cs.rutgers.edu int num_free = freeEntries[tid].sqEntries - 117110239Sbinhpham@cs.rutgers.edu (storesInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToSQ); 117210239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "calcFreeSQEntries: free sqEntries: %d, storesInProgress: %d, " 117310239Sbinhpham@cs.rutgers.edu "stores dispatchedToSQ: %d\n", freeEntries[tid].sqEntries, 117410239Sbinhpham@cs.rutgers.edu storesInProgress[tid], fromIEW->iewInfo[tid].dispatchedToSQ); 117510239Sbinhpham@cs.rutgers.edu return num_free; 11762292SN/A} 11772292SN/A 11782292SN/Atemplate <class Impl> 11792292SN/Aunsigned 11802292SN/ADefaultRename<Impl>::validInsts() 11812292SN/A{ 11822292SN/A unsigned inst_count = 0; 11832292SN/A 11842292SN/A for (int i=0; i<fromDecode->size; i++) { 11852731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11862292SN/A inst_count++; 11872292SN/A } 11882292SN/A 11892292SN/A return inst_count; 11902292SN/A} 11912292SN/A 11922292SN/Atemplate <class Impl> 11932292SN/Avoid 11946221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11952292SN/A{ 11962292SN/A if (fromIEW->iewBlock[tid]) { 11972292SN/A stalls[tid].iew = true; 11982292SN/A } 11992292SN/A 12002292SN/A if (fromIEW->iewUnblock[tid]) { 12012292SN/A assert(stalls[tid].iew); 12022292SN/A stalls[tid].iew = false; 12032292SN/A } 12042292SN/A} 12052292SN/A 12062292SN/Atemplate <class Impl> 12072292SN/Abool 12086221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 12092292SN/A{ 12102292SN/A bool ret_val = false; 12112292SN/A 12122292SN/A if (stalls[tid].iew) { 12132292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 12142292SN/A ret_val = true; 12152292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 12162292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 12172292SN/A ret_val = true; 12182292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 12192292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 12202292SN/A ret_val = true; 122110239Sbinhpham@cs.rutgers.edu } else if (calcFreeLQEntries(tid) <= 0 && calcFreeSQEntries(tid) <= 0) { 12222292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 12232292SN/A ret_val = true; 12242292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 12252292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 12262292SN/A ret_val = true; 12272301SN/A } else if (renameStatus[tid] == SerializeStall && 12282292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 12292301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 12302292SN/A "empty.\n", 12312292SN/A tid); 12322292SN/A ret_val = true; 12332292SN/A } 12342292SN/A 12352292SN/A return ret_val; 12362292SN/A} 12372292SN/A 12382292SN/Atemplate <class Impl> 12392292SN/Avoid 12406221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12412292SN/A{ 12428607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12438607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12442292SN/A 124510239Sbinhpham@cs.rutgers.edu if (fromIEW->iewInfo[tid].usedLSQ) { 124610239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries = fromIEW->iewInfo[tid].freeLQEntries; 124710239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries = fromIEW->iewInfo[tid].freeSQEntries; 124810239Sbinhpham@cs.rutgers.edu } 12492292SN/A 12502292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12512292SN/A freeEntries[tid].robEntries = 12522292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12532292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12542292SN/A } 12552292SN/A 125610239Sbinhpham@cs.rutgers.edu DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, " 125710239Sbinhpham@cs.rutgers.edu "Free LQ: %i, Free SQ: %i\n", 12582292SN/A tid, 12592292SN/A freeEntries[tid].iqEntries, 12602292SN/A freeEntries[tid].robEntries, 126110239Sbinhpham@cs.rutgers.edu freeEntries[tid].lqEntries, 126210239Sbinhpham@cs.rutgers.edu freeEntries[tid].sqEntries); 12632292SN/A 12642292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12652292SN/A tid, instsInProgress[tid]); 12662292SN/A} 12672292SN/A 12682292SN/Atemplate <class Impl> 12692292SN/Abool 12706221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12712292SN/A{ 12722292SN/A // Check if there's a squash signal, squash if there is 12732292SN/A // Check stall signals, block if necessary. 12742292SN/A // If status was blocked 12752292SN/A // check if stall conditions have passed 12762292SN/A // if so then go to unblocking 12772292SN/A // If status was Squashing 12782292SN/A // check if squashing is not high. Switch to running this cycle. 12792301SN/A // If status was serialize stall 12802292SN/A // check if ROB is empty and no insts are in flight to the ROB 12812292SN/A 12822292SN/A readFreeEntries(tid); 12832292SN/A readStallSignals(tid); 12842292SN/A 12852292SN/A if (fromCommit->commitInfo[tid].squash) { 12862292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12872292SN/A "commit.\n", tid); 12882292SN/A 12894632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12902292SN/A 12912292SN/A return true; 12922292SN/A } 12932292SN/A 12942292SN/A if (checkStall(tid)) { 12952292SN/A return block(tid); 12962292SN/A } 12972292SN/A 12982292SN/A if (renameStatus[tid] == Blocked) { 12992292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 13002292SN/A tid); 13012292SN/A 13022292SN/A renameStatus[tid] = Unblocking; 13032292SN/A 13042292SN/A unblock(tid); 13052292SN/A 13062292SN/A return true; 13072292SN/A } 13082292SN/A 13092292SN/A if (renameStatus[tid] == Squashing) { 13102292SN/A // Switch status to running if rename isn't being told to block or 13112292SN/A // squash this cycle. 13123798Sgblack@eecs.umich.edu if (resumeSerialize) { 13133798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 13143798Sgblack@eecs.umich.edu tid); 13152292SN/A 13163798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 13173798Sgblack@eecs.umich.edu return true; 13183798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 13193798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 13203798Sgblack@eecs.umich.edu tid); 13213798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 13223798Sgblack@eecs.umich.edu return true; 13233798Sgblack@eecs.umich.edu } else { 13243788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 13253788Sgblack@eecs.umich.edu tid); 13262292SN/A 13273788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13283788Sgblack@eecs.umich.edu return false; 13293788Sgblack@eecs.umich.edu } 13302292SN/A } 13312292SN/A 13322301SN/A if (renameStatus[tid] == SerializeStall) { 13332292SN/A // Stall ends once the ROB is free. 13342301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13352292SN/A "unblocking.\n", tid); 13362292SN/A 13372301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13382292SN/A 13392292SN/A renameStatus[tid] = Unblocking; 13402292SN/A 13412292SN/A unblock(tid); 13422292SN/A 13432292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13447720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13452292SN/A 13462292SN/A // Put instruction into queue here. 13472301SN/A serial_inst->clearSerializeBefore(); 13482292SN/A 13492292SN/A if (!skidBuffer[tid].empty()) { 13502301SN/A skidBuffer[tid].push_front(serial_inst); 13512292SN/A } else { 13522301SN/A insts[tid].push_front(serial_inst); 13532292SN/A } 13542292SN/A 13552292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13562703Sktlim@umich.edu " Adding to front of list.\n", tid); 13572292SN/A 13582301SN/A serializeInst[tid] = NULL; 13592292SN/A 13602292SN/A return true; 13612292SN/A } 13622292SN/A 13632292SN/A // If we've reached this point, we have not gotten any signals that 13642292SN/A // cause rename to change its status. Rename remains the same as before. 13652292SN/A return false; 13661061SN/A} 13671061SN/A 13681060SN/Atemplate<class Impl> 13691060SN/Avoid 13706221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13711060SN/A{ 13722292SN/A if (inst_list.empty()) { 13732292SN/A // Mark a bit to say that I must serialize on the next instruction. 13742292SN/A serializeOnNextInst[tid] = true; 13751060SN/A return; 13761060SN/A } 13771060SN/A 13782292SN/A // Set the next instruction as serializing. 13792292SN/A inst_list.front()->setSerializeBefore(); 13802292SN/A} 13812292SN/A 13822292SN/Atemplate <class Impl> 13832292SN/Ainline void 13842292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13852292SN/A{ 13862292SN/A switch (source) { 13872292SN/A case ROB: 13882292SN/A ++renameROBFullEvents; 13892292SN/A break; 13902292SN/A case IQ: 13912292SN/A ++renameIQFullEvents; 13922292SN/A break; 139310239Sbinhpham@cs.rutgers.edu case LQ: 139410239Sbinhpham@cs.rutgers.edu ++renameLQFullEvents; 139510239Sbinhpham@cs.rutgers.edu break; 139610239Sbinhpham@cs.rutgers.edu case SQ: 139710239Sbinhpham@cs.rutgers.edu ++renameSQFullEvents; 13982292SN/A break; 13992292SN/A default: 14002292SN/A panic("Rename full stall stat should be incremented for a reason!"); 14012292SN/A break; 14021060SN/A } 14032292SN/A} 14041060SN/A 14052292SN/Atemplate <class Impl> 14062292SN/Avoid 14072292SN/ADefaultRename<Impl>::dumpHistory() 14082292SN/A{ 14092980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 14101060SN/A 14116221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 14121060SN/A 14136221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 14141060SN/A 14156221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 14162292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 14172292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 14182292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 14191060SN/A 14202292SN/A buf_it++; 14211062SN/A } 14221060SN/A } 14231060SN/A} 14249944Smatt.horsnell@ARM.com 14259944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1426