rename_impl.hh revision 10172
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2012 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47854SAli.Saidi@ARM.com * All rights reserved. 57854SAli.Saidi@ARM.com * 67854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 77854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 87854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 97854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 107854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 117854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 127854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 137854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 147854SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422935Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_RENAME_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_RENAME_IMPL_HH__ 479944Smatt.horsnell@ARM.com 481060SN/A#include <list> 491060SN/A 503773Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 516329Sgblack@eecs.umich.edu#include "arch/registers.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 531717SN/A#include "cpu/o3/rename.hh" 549913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/Rename.hh" 579527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 585529Snate@binkert.org#include "params/DerivO3CPU.hh" 591060SN/A 606221Snate@binkert.orgusing namespace std; 616221Snate@binkert.org 621061SN/Atemplate <class Impl> 635529Snate@binkert.orgDefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params) 644329Sktlim@umich.edu : cpu(_cpu), 654329Sktlim@umich.edu iewToRenameDelay(params->iewToRenameDelay), 662292SN/A decodeToRenameDelay(params->decodeToRenameDelay), 672292SN/A commitToRenameDelay(params->commitToRenameDelay), 682292SN/A renameWidth(params->renameWidth), 692292SN/A commitWidth(params->commitWidth), 705529Snate@binkert.org numThreads(params->numThreads), 719920Syasuko.eckert@amd.com maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs 729920Syasuko.eckert@amd.com + params->numPhysCCRegs) 731060SN/A{ 7410172Sdam.sunwoo@arm.com if (renameWidth > Impl::MaxWidth) 7510172Sdam.sunwoo@arm.com fatal("renameWidth (%d) is larger than compiled limit (%d),\n" 7610172Sdam.sunwoo@arm.com "\tincrease MaxWidth in src/cpu/o3/impl.hh\n", 7710172Sdam.sunwoo@arm.com renameWidth, static_cast<int>(Impl::MaxWidth)); 7810172Sdam.sunwoo@arm.com 792292SN/A // @todo: Make into a parameter. 808907Slukefahr@umich.edu skidBufferMax = (2 * (decodeToRenameDelay * params->decodeWidth)) + renameWidth; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 842292SN/Astd::string 852292SN/ADefaultRename<Impl>::name() const 862292SN/A{ 872292SN/A return cpu->name() + ".rename"; 881060SN/A} 891060SN/A 901061SN/Atemplate <class Impl> 911060SN/Avoid 922292SN/ADefaultRename<Impl>::regStats() 931062SN/A{ 941062SN/A renameSquashCycles 958240Snate@binkert.org .name(name() + ".SquashCycles") 961062SN/A .desc("Number of cycles rename is squashing") 971062SN/A .prereq(renameSquashCycles); 981062SN/A renameIdleCycles 998240Snate@binkert.org .name(name() + ".IdleCycles") 1001062SN/A .desc("Number of cycles rename is idle") 1011062SN/A .prereq(renameIdleCycles); 1021062SN/A renameBlockCycles 1038240Snate@binkert.org .name(name() + ".BlockCycles") 1041062SN/A .desc("Number of cycles rename is blocking") 1051062SN/A .prereq(renameBlockCycles); 1062301SN/A renameSerializeStallCycles 1078240Snate@binkert.org .name(name() + ".serializeStallCycles") 1082301SN/A .desc("count of cycles rename stalled for serializing inst") 1092301SN/A .flags(Stats::total); 1102292SN/A renameRunCycles 1118240Snate@binkert.org .name(name() + ".RunCycles") 1122292SN/A .desc("Number of cycles rename is running") 1132292SN/A .prereq(renameIdleCycles); 1141062SN/A renameUnblockCycles 1158240Snate@binkert.org .name(name() + ".UnblockCycles") 1161062SN/A .desc("Number of cycles rename is unblocking") 1171062SN/A .prereq(renameUnblockCycles); 1181062SN/A renameRenamedInsts 1198240Snate@binkert.org .name(name() + ".RenamedInsts") 1201062SN/A .desc("Number of instructions processed by rename") 1211062SN/A .prereq(renameRenamedInsts); 1221062SN/A renameSquashedInsts 1238240Snate@binkert.org .name(name() + ".SquashedInsts") 1241062SN/A .desc("Number of squashed instructions processed by rename") 1251062SN/A .prereq(renameSquashedInsts); 1261062SN/A renameROBFullEvents 1278240Snate@binkert.org .name(name() + ".ROBFullEvents") 1282292SN/A .desc("Number of times rename has blocked due to ROB full") 1291062SN/A .prereq(renameROBFullEvents); 1301062SN/A renameIQFullEvents 1318240Snate@binkert.org .name(name() + ".IQFullEvents") 1322292SN/A .desc("Number of times rename has blocked due to IQ full") 1331062SN/A .prereq(renameIQFullEvents); 1342292SN/A renameLSQFullEvents 1358240Snate@binkert.org .name(name() + ".LSQFullEvents") 1362292SN/A .desc("Number of times rename has blocked due to LSQ full") 1372292SN/A .prereq(renameLSQFullEvents); 1381062SN/A renameFullRegistersEvents 1398240Snate@binkert.org .name(name() + ".FullRegisterEvents") 1401062SN/A .desc("Number of times there has been no free registers") 1411062SN/A .prereq(renameFullRegistersEvents); 1421062SN/A renameRenamedOperands 1438240Snate@binkert.org .name(name() + ".RenamedOperands") 1441062SN/A .desc("Number of destination operands rename has renamed") 1451062SN/A .prereq(renameRenamedOperands); 1461062SN/A renameRenameLookups 1478240Snate@binkert.org .name(name() + ".RenameLookups") 1481062SN/A .desc("Number of register rename lookups that rename has made") 1491062SN/A .prereq(renameRenameLookups); 1501062SN/A renameCommittedMaps 1518240Snate@binkert.org .name(name() + ".CommittedMaps") 1521062SN/A .desc("Number of HB maps that are committed") 1531062SN/A .prereq(renameCommittedMaps); 1541062SN/A renameUndoneMaps 1558240Snate@binkert.org .name(name() + ".UndoneMaps") 1561062SN/A .desc("Number of HB maps that are undone due to squashing") 1571062SN/A .prereq(renameUndoneMaps); 1582301SN/A renamedSerializing 1598240Snate@binkert.org .name(name() + ".serializingInsts") 1602301SN/A .desc("count of serializing insts renamed") 1612301SN/A .flags(Stats::total) 1622301SN/A ; 1632301SN/A renamedTempSerializing 1648240Snate@binkert.org .name(name() + ".tempSerializingInsts") 1652301SN/A .desc("count of temporary serializing insts renamed") 1662301SN/A .flags(Stats::total) 1672301SN/A ; 1682307SN/A renameSkidInsts 1698240Snate@binkert.org .name(name() + ".skidInsts") 1702307SN/A .desc("count of insts added to the skid buffer") 1712307SN/A .flags(Stats::total) 1722307SN/A ; 1737897Shestness@cs.utexas.edu intRenameLookups 1748240Snate@binkert.org .name(name() + ".int_rename_lookups") 1757897Shestness@cs.utexas.edu .desc("Number of integer rename lookups") 1767897Shestness@cs.utexas.edu .prereq(intRenameLookups); 1777897Shestness@cs.utexas.edu fpRenameLookups 1788240Snate@binkert.org .name(name() + ".fp_rename_lookups") 1797897Shestness@cs.utexas.edu .desc("Number of floating rename lookups") 1807897Shestness@cs.utexas.edu .prereq(fpRenameLookups); 1811062SN/A} 1821062SN/A 1831062SN/Atemplate <class Impl> 1841062SN/Avoid 1852292SN/ADefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1861060SN/A{ 1871060SN/A timeBuffer = tb_ptr; 1881060SN/A 1891060SN/A // Setup wire to read information from time buffer, from IEW stage. 1901060SN/A fromIEW = timeBuffer->getWire(-iewToRenameDelay); 1911060SN/A 1921060SN/A // Setup wire to read infromation from time buffer, from commit stage. 1931060SN/A fromCommit = timeBuffer->getWire(-commitToRenameDelay); 1941060SN/A 1951060SN/A // Setup wire to write information to previous stages. 1961060SN/A toDecode = timeBuffer->getWire(0); 1971060SN/A} 1981060SN/A 1991061SN/Atemplate <class Impl> 2001060SN/Avoid 2012292SN/ADefaultRename<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 2021060SN/A{ 2031060SN/A renameQueue = rq_ptr; 2041060SN/A 2051060SN/A // Setup wire to write information to future stages. 2061060SN/A toIEW = renameQueue->getWire(0); 2071060SN/A} 2081060SN/A 2091061SN/Atemplate <class Impl> 2101060SN/Avoid 2112292SN/ADefaultRename<Impl>::setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr) 2121060SN/A{ 2131060SN/A decodeQueue = dq_ptr; 2141060SN/A 2151060SN/A // Setup wire to get information from decode. 2161060SN/A fromDecode = decodeQueue->getWire(-decodeToRenameDelay); 2171060SN/A} 2181060SN/A 2191061SN/Atemplate <class Impl> 2201060SN/Avoid 2219427SAndreas.Sandberg@ARM.comDefaultRename<Impl>::startupStage() 2221060SN/A{ 2239444SAndreas.Sandberg@ARM.com resetStage(); 2249444SAndreas.Sandberg@ARM.com} 2259444SAndreas.Sandberg@ARM.com 2269444SAndreas.Sandberg@ARM.comtemplate <class Impl> 2279444SAndreas.Sandberg@ARM.comvoid 2289444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::resetStage() 2299444SAndreas.Sandberg@ARM.com{ 2309444SAndreas.Sandberg@ARM.com _status = Inactive; 2319444SAndreas.Sandberg@ARM.com 2329444SAndreas.Sandberg@ARM.com resumeSerialize = false; 2339444SAndreas.Sandberg@ARM.com resumeUnblocking = false; 2349444SAndreas.Sandberg@ARM.com 2352329SN/A // Grab the number of free entries directly from the stages. 2366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2379444SAndreas.Sandberg@ARM.com renameStatus[tid] = Idle; 2389444SAndreas.Sandberg@ARM.com 2392292SN/A freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid); 2402292SN/A freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid); 2412292SN/A freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid); 2422292SN/A emptyROB[tid] = true; 2439444SAndreas.Sandberg@ARM.com 2449444SAndreas.Sandberg@ARM.com stalls[tid].iew = false; 2459444SAndreas.Sandberg@ARM.com stalls[tid].commit = false; 2469444SAndreas.Sandberg@ARM.com serializeInst[tid] = NULL; 2479444SAndreas.Sandberg@ARM.com 2489444SAndreas.Sandberg@ARM.com instsInProgress[tid] = 0; 2499444SAndreas.Sandberg@ARM.com 2509444SAndreas.Sandberg@ARM.com serializeOnNextInst[tid] = false; 2512292SN/A } 2521060SN/A} 2531060SN/A 2542292SN/Atemplate<class Impl> 2552292SN/Avoid 2566221Snate@binkert.orgDefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 2572292SN/A{ 2582292SN/A activeThreads = at_ptr; 2592292SN/A} 2602292SN/A 2612292SN/A 2621061SN/Atemplate <class Impl> 2631060SN/Avoid 2642292SN/ADefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[]) 2651060SN/A{ 2666221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 2676221Snate@binkert.org renameMap[tid] = &rm_ptr[tid]; 2681060SN/A} 2691060SN/A 2701061SN/Atemplate <class Impl> 2711060SN/Avoid 2722292SN/ADefaultRename<Impl>::setFreeList(FreeList *fl_ptr) 2731060SN/A{ 2742292SN/A freeList = fl_ptr; 2752292SN/A} 2761060SN/A 2772292SN/Atemplate<class Impl> 2782292SN/Avoid 2792292SN/ADefaultRename<Impl>::setScoreboard(Scoreboard *_scoreboard) 2802292SN/A{ 2812292SN/A scoreboard = _scoreboard; 2821060SN/A} 2831060SN/A 2841061SN/Atemplate <class Impl> 2852863Sktlim@umich.edubool 2869444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::isDrained() const 2871060SN/A{ 2889444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 2899444SAndreas.Sandberg@ARM.com if (instsInProgress[tid] != 0 || 2909444SAndreas.Sandberg@ARM.com !historyBuffer[tid].empty() || 2919444SAndreas.Sandberg@ARM.com !skidBuffer[tid].empty() || 2929444SAndreas.Sandberg@ARM.com !insts[tid].empty()) 2939444SAndreas.Sandberg@ARM.com return false; 2949444SAndreas.Sandberg@ARM.com } 2952863Sktlim@umich.edu return true; 2962316SN/A} 2971060SN/A 2982316SN/Atemplate <class Impl> 2992316SN/Avoid 3002307SN/ADefaultRename<Impl>::takeOverFrom() 3011060SN/A{ 3029444SAndreas.Sandberg@ARM.com resetStage(); 3039444SAndreas.Sandberg@ARM.com} 3041060SN/A 3059444SAndreas.Sandberg@ARM.comtemplate <class Impl> 3069444SAndreas.Sandberg@ARM.comvoid 3079444SAndreas.Sandberg@ARM.comDefaultRename<Impl>::drainSanityCheck() const 3089444SAndreas.Sandberg@ARM.com{ 3096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3109444SAndreas.Sandberg@ARM.com assert(historyBuffer[tid].empty()); 3119444SAndreas.Sandberg@ARM.com assert(insts[tid].empty()); 3129444SAndreas.Sandberg@ARM.com assert(skidBuffer[tid].empty()); 3139444SAndreas.Sandberg@ARM.com assert(instsInProgress[tid] == 0); 3142307SN/A } 3152307SN/A} 3162307SN/A 3172307SN/Atemplate <class Impl> 3182307SN/Avoid 3196221Snate@binkert.orgDefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) 3201858SN/A{ 3212292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid); 3221858SN/A 3232292SN/A // Clear the stall signal if rename was blocked or unblocking before. 3242292SN/A // If it still needs to block, the blocking should happen the next 3252292SN/A // cycle and there should be space to hold everything due to the squash. 3262292SN/A if (renameStatus[tid] == Blocked || 3273788Sgblack@eecs.umich.edu renameStatus[tid] == Unblocking) { 3282292SN/A toDecode->renameUnblock[tid] = 1; 3292698Sktlim@umich.edu 3303788Sgblack@eecs.umich.edu resumeSerialize = false; 3312301SN/A serializeInst[tid] = NULL; 3323788Sgblack@eecs.umich.edu } else if (renameStatus[tid] == SerializeStall) { 3333788Sgblack@eecs.umich.edu if (serializeInst[tid]->seqNum <= squash_seq_num) { 3343788Sgblack@eecs.umich.edu DPRINTF(Rename, "Rename will resume serializing after squash\n"); 3353788Sgblack@eecs.umich.edu resumeSerialize = true; 3363788Sgblack@eecs.umich.edu assert(serializeInst[tid]); 3373788Sgblack@eecs.umich.edu } else { 3383788Sgblack@eecs.umich.edu resumeSerialize = false; 3393788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = 1; 3403788Sgblack@eecs.umich.edu 3413788Sgblack@eecs.umich.edu serializeInst[tid] = NULL; 3423788Sgblack@eecs.umich.edu } 3432292SN/A } 3442292SN/A 3452292SN/A // Set the status to Squashing. 3462292SN/A renameStatus[tid] = Squashing; 3472292SN/A 3482329SN/A // Squash any instructions from decode. 3492292SN/A for (int i=0; i<fromDecode->size; i++) { 3502935Sksewell@umich.edu if (fromDecode->insts[i]->threadNumber == tid && 3512935Sksewell@umich.edu fromDecode->insts[i]->seqNum > squash_seq_num) { 3522731Sktlim@umich.edu fromDecode->insts[i]->setSquashed(); 3532292SN/A wroteToTimeBuffer = true; 3542292SN/A } 3552935Sksewell@umich.edu 3562292SN/A } 3572292SN/A 3582935Sksewell@umich.edu // Clear the instruction list and skid buffer in case they have any 3594632Sgblack@eecs.umich.edu // insts in them. 3603093Sksewell@umich.edu insts[tid].clear(); 3612292SN/A 3622292SN/A // Clear the skid buffer in case it has any data in it. 3633093Sksewell@umich.edu skidBuffer[tid].clear(); 3644632Sgblack@eecs.umich.edu 3652935Sksewell@umich.edu doSquash(squash_seq_num, tid); 3662292SN/A} 3672292SN/A 3682292SN/Atemplate <class Impl> 3692292SN/Avoid 3702292SN/ADefaultRename<Impl>::tick() 3712292SN/A{ 3722292SN/A wroteToTimeBuffer = false; 3732292SN/A 3742292SN/A blockThisCycle = false; 3752292SN/A 3762292SN/A bool status_change = false; 3772292SN/A 3782292SN/A toIEWIndex = 0; 3792292SN/A 3802292SN/A sortInsts(); 3812292SN/A 3826221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 3836221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 3842292SN/A 3852292SN/A // Check stall and squash signals. 3863867Sbinkertn@umich.edu while (threads != end) { 3876221Snate@binkert.org ThreadID tid = *threads++; 3882292SN/A 3892292SN/A DPRINTF(Rename, "Processing [tid:%i]\n", tid); 3902292SN/A 3912292SN/A status_change = checkSignalsAndUpdate(tid) || status_change; 3922292SN/A 3932292SN/A rename(status_change, tid); 3942292SN/A } 3952292SN/A 3962292SN/A if (status_change) { 3972292SN/A updateStatus(); 3982292SN/A } 3992292SN/A 4002292SN/A if (wroteToTimeBuffer) { 4012292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 4022292SN/A cpu->activityThisCycle(); 4032292SN/A } 4042292SN/A 4053867Sbinkertn@umich.edu threads = activeThreads->begin(); 4062292SN/A 4073867Sbinkertn@umich.edu while (threads != end) { 4086221Snate@binkert.org ThreadID tid = *threads++; 4092292SN/A 4102292SN/A // If we committed this cycle then doneSeqNum will be > 0 4112292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 4122292SN/A !fromCommit->commitInfo[tid].squash && 4132292SN/A renameStatus[tid] != Squashing) { 4142292SN/A 4152292SN/A removeFromHistory(fromCommit->commitInfo[tid].doneSeqNum, 4162292SN/A tid); 4172292SN/A } 4182292SN/A } 4192292SN/A 4202292SN/A // @todo: make into updateProgress function 4216221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4222292SN/A instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched; 4232292SN/A 4242292SN/A assert(instsInProgress[tid] >=0); 4252292SN/A } 4262292SN/A 4272292SN/A} 4282292SN/A 4292292SN/Atemplate<class Impl> 4302292SN/Avoid 4316221Snate@binkert.orgDefaultRename<Impl>::rename(bool &status_change, ThreadID tid) 4322292SN/A{ 4332292SN/A // If status is Running or idle, 4342292SN/A // call renameInsts() 4352292SN/A // If status is Unblocking, 4362292SN/A // buffer any instructions coming from decode 4372292SN/A // continue trying to empty skid buffer 4382292SN/A // check if stall conditions have passed 4392292SN/A 4402292SN/A if (renameStatus[tid] == Blocked) { 4412292SN/A ++renameBlockCycles; 4422292SN/A } else if (renameStatus[tid] == Squashing) { 4432292SN/A ++renameSquashCycles; 4442301SN/A } else if (renameStatus[tid] == SerializeStall) { 4452301SN/A ++renameSerializeStallCycles; 4463788Sgblack@eecs.umich.edu // If we are currently in SerializeStall and resumeSerialize 4473788Sgblack@eecs.umich.edu // was set, then that means that we are resuming serializing 4483788Sgblack@eecs.umich.edu // this cycle. Tell the previous stages to block. 4493788Sgblack@eecs.umich.edu if (resumeSerialize) { 4503788Sgblack@eecs.umich.edu resumeSerialize = false; 4513788Sgblack@eecs.umich.edu block(tid); 4523788Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4533788Sgblack@eecs.umich.edu } 4543798Sgblack@eecs.umich.edu } else if (renameStatus[tid] == Unblocking) { 4553798Sgblack@eecs.umich.edu if (resumeUnblocking) { 4563798Sgblack@eecs.umich.edu block(tid); 4573798Sgblack@eecs.umich.edu resumeUnblocking = false; 4583798Sgblack@eecs.umich.edu toDecode->renameUnblock[tid] = false; 4593798Sgblack@eecs.umich.edu } 4602292SN/A } 4612292SN/A 4622292SN/A if (renameStatus[tid] == Running || 4632292SN/A renameStatus[tid] == Idle) { 4642292SN/A DPRINTF(Rename, "[tid:%u]: Not blocked, so attempting to run " 4652292SN/A "stage.\n", tid); 4662292SN/A 4672292SN/A renameInsts(tid); 4682292SN/A } else if (renameStatus[tid] == Unblocking) { 4692292SN/A renameInsts(tid); 4702292SN/A 4712292SN/A if (validInsts()) { 4722292SN/A // Add the current inputs to the skid buffer so they can be 4732292SN/A // reprocessed when this stage unblocks. 4742292SN/A skidInsert(tid); 4752292SN/A } 4762292SN/A 4772292SN/A // If we switched over to blocking, then there's a potential for 4782292SN/A // an overall status change. 4792292SN/A status_change = unblock(tid) || status_change || blockThisCycle; 4801858SN/A } 4811858SN/A} 4821858SN/A 4831858SN/Atemplate <class Impl> 4841858SN/Avoid 4856221Snate@binkert.orgDefaultRename<Impl>::renameInsts(ThreadID tid) 4861858SN/A{ 4872292SN/A // Instructions can be either in the skid buffer or the queue of 4882292SN/A // instructions coming from decode, depending on the status. 4892292SN/A int insts_available = renameStatus[tid] == Unblocking ? 4902292SN/A skidBuffer[tid].size() : insts[tid].size(); 4911858SN/A 4922292SN/A // Check the decode queue to see if instructions are available. 4932292SN/A // If there are no available instructions to rename, then do nothing. 4942292SN/A if (insts_available == 0) { 4952292SN/A DPRINTF(Rename, "[tid:%u]: Nothing to do, breaking out early.\n", 4962292SN/A tid); 4972292SN/A // Should I change status to idle? 4982292SN/A ++renameIdleCycles; 4992292SN/A return; 5002292SN/A } else if (renameStatus[tid] == Unblocking) { 5012292SN/A ++renameUnblockCycles; 5022292SN/A } else if (renameStatus[tid] == Running) { 5032292SN/A ++renameRunCycles; 5042292SN/A } 5051858SN/A 5062292SN/A DynInstPtr inst; 5072292SN/A 5082292SN/A // Will have to do a different calculation for the number of free 5092292SN/A // entries. 5102292SN/A int free_rob_entries = calcFreeROBEntries(tid); 5112292SN/A int free_iq_entries = calcFreeIQEntries(tid); 5122292SN/A int free_lsq_entries = calcFreeLSQEntries(tid); 5132292SN/A int min_free_entries = free_rob_entries; 5142292SN/A 5152292SN/A FullSource source = ROB; 5162292SN/A 5172292SN/A if (free_iq_entries < min_free_entries) { 5182292SN/A min_free_entries = free_iq_entries; 5192292SN/A source = IQ; 5202292SN/A } 5212292SN/A 5222292SN/A if (free_lsq_entries < min_free_entries) { 5232292SN/A min_free_entries = free_lsq_entries; 5242292SN/A source = LSQ; 5252292SN/A } 5262292SN/A 5272292SN/A // Check if there's any space left. 5282292SN/A if (min_free_entries <= 0) { 5292292SN/A DPRINTF(Rename, "[tid:%u]: Blocking due to no free ROB/IQ/LSQ " 5302292SN/A "entries.\n" 5312292SN/A "ROB has %i free entries.\n" 5322292SN/A "IQ has %i free entries.\n" 5332292SN/A "LSQ has %i free entries.\n", 5342292SN/A tid, 5352292SN/A free_rob_entries, 5362292SN/A free_iq_entries, 5372292SN/A free_lsq_entries); 5382292SN/A 5392292SN/A blockThisCycle = true; 5402292SN/A 5412292SN/A block(tid); 5422292SN/A 5432292SN/A incrFullStat(source); 5442292SN/A 5452292SN/A return; 5462292SN/A } else if (min_free_entries < insts_available) { 5472292SN/A DPRINTF(Rename, "[tid:%u]: Will have to block this cycle." 5482292SN/A "%i insts available, but only %i insts can be " 5492292SN/A "renamed due to ROB/IQ/LSQ limits.\n", 5502292SN/A tid, insts_available, min_free_entries); 5512292SN/A 5522292SN/A insts_available = min_free_entries; 5532292SN/A 5542292SN/A blockThisCycle = true; 5552292SN/A 5562292SN/A incrFullStat(source); 5572292SN/A } 5582292SN/A 5592292SN/A InstQueue &insts_to_rename = renameStatus[tid] == Unblocking ? 5602292SN/A skidBuffer[tid] : insts[tid]; 5612292SN/A 5622292SN/A DPRINTF(Rename, "[tid:%u]: %i available instructions to " 5632292SN/A "send iew.\n", tid, insts_available); 5642292SN/A 5652292SN/A DPRINTF(Rename, "[tid:%u]: %i insts pipelining from Rename | %i insts " 5662292SN/A "dispatched to IQ last cycle.\n", 5672292SN/A tid, instsInProgress[tid], fromIEW->iewInfo[tid].dispatched); 5682292SN/A 5692292SN/A // Handle serializing the next instruction if necessary. 5702292SN/A if (serializeOnNextInst[tid]) { 5712292SN/A if (emptyROB[tid] && instsInProgress[tid] == 0) { 5722292SN/A // ROB already empty; no need to serialize. 5732292SN/A serializeOnNextInst[tid] = false; 5742292SN/A } else if (!insts_to_rename.empty()) { 5752292SN/A insts_to_rename.front()->setSerializeBefore(); 5762292SN/A } 5772292SN/A } 5782292SN/A 5792292SN/A int renamed_insts = 0; 5802292SN/A 5812292SN/A while (insts_available > 0 && toIEWIndex < renameWidth) { 5822292SN/A DPRINTF(Rename, "[tid:%u]: Sending instructions to IEW.\n", tid); 5832292SN/A 5842292SN/A assert(!insts_to_rename.empty()); 5852292SN/A 5862292SN/A inst = insts_to_rename.front(); 5872292SN/A 5882292SN/A insts_to_rename.pop_front(); 5892292SN/A 5902292SN/A if (renameStatus[tid] == Unblocking) { 5917720Sgblack@eecs.umich.edu DPRINTF(Rename,"[tid:%u]: Removing [sn:%lli] PC:%s from rename " 5927720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 5932292SN/A } 5942292SN/A 5952292SN/A if (inst->isSquashed()) { 5967720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: instruction %i with PC %s is " 5977720Sgblack@eecs.umich.edu "squashed, skipping.\n", tid, inst->seqNum, 5987720Sgblack@eecs.umich.edu inst->pcState()); 5992292SN/A 6002292SN/A ++renameSquashedInsts; 6012292SN/A 6022292SN/A // Decrement how many instructions are available. 6032292SN/A --insts_available; 6042292SN/A 6052292SN/A continue; 6062292SN/A } 6072292SN/A 6082292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [sn:%lli] with " 6097720Sgblack@eecs.umich.edu "PC %s.\n", tid, inst->seqNum, inst->pcState()); 6102292SN/A 6119531Sgeoffrey.blake@arm.com // Check here to make sure there are enough destination registers 6129531Sgeoffrey.blake@arm.com // to rename to. Otherwise block. 6139531Sgeoffrey.blake@arm.com if (renameMap[tid]->numFreeEntries() < inst->numDestRegs()) { 6149531Sgeoffrey.blake@arm.com DPRINTF(Rename, "Blocking due to lack of free " 6159531Sgeoffrey.blake@arm.com "physical registers to rename to.\n"); 6169531Sgeoffrey.blake@arm.com blockThisCycle = true; 6179531Sgeoffrey.blake@arm.com insts_to_rename.push_front(inst); 6189531Sgeoffrey.blake@arm.com ++renameFullRegistersEvents; 6199531Sgeoffrey.blake@arm.com 6209531Sgeoffrey.blake@arm.com break; 6219531Sgeoffrey.blake@arm.com } 6229531Sgeoffrey.blake@arm.com 6232292SN/A // Handle serializeAfter/serializeBefore instructions. 6242292SN/A // serializeAfter marks the next instruction as serializeBefore. 6252292SN/A // serializeBefore makes the instruction wait in rename until the ROB 6262292SN/A // is empty. 6272336SN/A 6282336SN/A // In this model, IPR accesses are serialize before 6292336SN/A // instructions, and store conditionals are serialize after 6302336SN/A // instructions. This is mainly due to lack of support for 6312336SN/A // out-of-order operations of either of those classes of 6322336SN/A // instructions. 6332336SN/A if ((inst->isIprAccess() || inst->isSerializeBefore()) && 6342336SN/A !inst->isSerializeHandled()) { 6352292SN/A DPRINTF(Rename, "Serialize before instruction encountered.\n"); 6362292SN/A 6372301SN/A if (!inst->isTempSerializeBefore()) { 6382301SN/A renamedSerializing++; 6392292SN/A inst->setSerializeHandled(); 6402301SN/A } else { 6412301SN/A renamedTempSerializing++; 6422301SN/A } 6432292SN/A 6442301SN/A // Change status over to SerializeStall so that other stages know 6452292SN/A // what this is blocked on. 6462301SN/A renameStatus[tid] = SerializeStall; 6472292SN/A 6482301SN/A serializeInst[tid] = inst; 6492292SN/A 6502292SN/A blockThisCycle = true; 6512292SN/A 6522292SN/A break; 6532336SN/A } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && 6542336SN/A !inst->isSerializeHandled()) { 6552292SN/A DPRINTF(Rename, "Serialize after instruction encountered.\n"); 6562292SN/A 6572307SN/A renamedSerializing++; 6582307SN/A 6592292SN/A inst->setSerializeHandled(); 6602292SN/A 6612292SN/A serializeAfter(insts_to_rename, tid); 6622292SN/A } 6632292SN/A 6642292SN/A renameSrcRegs(inst, inst->threadNumber); 6652292SN/A 6662292SN/A renameDestRegs(inst, inst->threadNumber); 6672292SN/A 6682292SN/A ++renamed_insts; 6692292SN/A 6708471SGiacomo.Gabrielli@arm.com 6712292SN/A // Put instruction in rename queue. 6722292SN/A toIEW->insts[toIEWIndex] = inst; 6732292SN/A ++(toIEW->size); 6742292SN/A 6752292SN/A // Increment which instruction we're on. 6762292SN/A ++toIEWIndex; 6772292SN/A 6782292SN/A // Decrement how many instructions are available. 6792292SN/A --insts_available; 6802292SN/A } 6812292SN/A 6822292SN/A instsInProgress[tid] += renamed_insts; 6832307SN/A renameRenamedInsts += renamed_insts; 6842292SN/A 6852292SN/A // If we wrote to the time buffer, record this. 6862292SN/A if (toIEWIndex) { 6872292SN/A wroteToTimeBuffer = true; 6882292SN/A } 6892292SN/A 6902292SN/A // Check if there's any instructions left that haven't yet been renamed. 6912292SN/A // If so then block. 6922292SN/A if (insts_available) { 6932292SN/A blockThisCycle = true; 6942292SN/A } 6952292SN/A 6962292SN/A if (blockThisCycle) { 6972292SN/A block(tid); 6982292SN/A toDecode->renameUnblock[tid] = false; 6992292SN/A } 7002292SN/A} 7012292SN/A 7022292SN/Atemplate<class Impl> 7032292SN/Avoid 7046221Snate@binkert.orgDefaultRename<Impl>::skidInsert(ThreadID tid) 7052292SN/A{ 7062292SN/A DynInstPtr inst = NULL; 7072292SN/A 7082292SN/A while (!insts[tid].empty()) { 7092292SN/A inst = insts[tid].front(); 7102292SN/A 7112292SN/A insts[tid].pop_front(); 7122292SN/A 7132292SN/A assert(tid == inst->threadNumber); 7142292SN/A 7157720Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Inserting [sn:%lli] PC: %s into Rename " 7167720Sgblack@eecs.umich.edu "skidBuffer\n", tid, inst->seqNum, inst->pcState()); 7172292SN/A 7182307SN/A ++renameSkidInsts; 7192307SN/A 7202292SN/A skidBuffer[tid].push_back(inst); 7212292SN/A } 7222292SN/A 7232292SN/A if (skidBuffer[tid].size() > skidBufferMax) 7243798Sgblack@eecs.umich.edu { 7253798Sgblack@eecs.umich.edu typename InstQueue::iterator it; 7263798Sgblack@eecs.umich.edu warn("Skidbuffer contents:\n"); 7273798Sgblack@eecs.umich.edu for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) 7283798Sgblack@eecs.umich.edu { 7293798Sgblack@eecs.umich.edu warn("[tid:%u]: %s [sn:%i].\n", tid, 7307720Sgblack@eecs.umich.edu (*it)->staticInst->disassemble(inst->instAddr()), 7313798Sgblack@eecs.umich.edu (*it)->seqNum); 7323798Sgblack@eecs.umich.edu } 7332292SN/A panic("Skidbuffer Exceeded Max Size"); 7343798Sgblack@eecs.umich.edu } 7352292SN/A} 7362292SN/A 7372292SN/Atemplate <class Impl> 7382292SN/Avoid 7392292SN/ADefaultRename<Impl>::sortInsts() 7402292SN/A{ 7412292SN/A int insts_from_decode = fromDecode->size; 7422292SN/A for (int i = 0; i < insts_from_decode; ++i) { 7432292SN/A DynInstPtr inst = fromDecode->insts[i]; 7442292SN/A insts[inst->threadNumber].push_back(inst); 7459527SMatt.Horsnell@arm.com#if TRACING_ON 7469527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 7479527SMatt.Horsnell@arm.com inst->renameTick = curTick() - inst->fetchTick; 7489527SMatt.Horsnell@arm.com } 7499527SMatt.Horsnell@arm.com#endif 7502292SN/A } 7512292SN/A} 7522292SN/A 7532292SN/Atemplate<class Impl> 7542292SN/Abool 7552292SN/ADefaultRename<Impl>::skidsEmpty() 7562292SN/A{ 7576221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7586221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7592292SN/A 7603867Sbinkertn@umich.edu while (threads != end) { 7616221Snate@binkert.org ThreadID tid = *threads++; 7623867Sbinkertn@umich.edu 7633867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 7642292SN/A return false; 7652292SN/A } 7662292SN/A 7672292SN/A return true; 7682292SN/A} 7692292SN/A 7702292SN/Atemplate<class Impl> 7712292SN/Avoid 7722292SN/ADefaultRename<Impl>::updateStatus() 7732292SN/A{ 7742292SN/A bool any_unblocking = false; 7752292SN/A 7766221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7776221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7782292SN/A 7793867Sbinkertn@umich.edu while (threads != end) { 7806221Snate@binkert.org ThreadID tid = *threads++; 7812292SN/A 7822292SN/A if (renameStatus[tid] == Unblocking) { 7832292SN/A any_unblocking = true; 7842292SN/A break; 7852292SN/A } 7862292SN/A } 7872292SN/A 7882292SN/A // Rename will have activity if it's unblocking. 7892292SN/A if (any_unblocking) { 7902292SN/A if (_status == Inactive) { 7912292SN/A _status = Active; 7922292SN/A 7932292SN/A DPRINTF(Activity, "Activating stage.\n"); 7942292SN/A 7952733Sktlim@umich.edu cpu->activateStage(O3CPU::RenameIdx); 7962292SN/A } 7972292SN/A } else { 7982292SN/A // If it's not unblocking, then rename will not have any internal 7992292SN/A // activity. Switch it to inactive. 8002292SN/A if (_status == Active) { 8012292SN/A _status = Inactive; 8022292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8032292SN/A 8042733Sktlim@umich.edu cpu->deactivateStage(O3CPU::RenameIdx); 8052292SN/A } 8062292SN/A } 8072292SN/A} 8082292SN/A 8092292SN/Atemplate <class Impl> 8102292SN/Abool 8116221Snate@binkert.orgDefaultRename<Impl>::block(ThreadID tid) 8122292SN/A{ 8132292SN/A DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid); 8142292SN/A 8152292SN/A // Add the current inputs onto the skid buffer, so they can be 8162292SN/A // reprocessed when this stage unblocks. 8172292SN/A skidInsert(tid); 8182292SN/A 8192292SN/A // Only signal backwards to block if the previous stages do not think 8202292SN/A // rename is already blocked. 8212292SN/A if (renameStatus[tid] != Blocked) { 8223798Sgblack@eecs.umich.edu // If resumeUnblocking is set, we unblocked during the squash, 8233798Sgblack@eecs.umich.edu // but now we're have unblocking status. We need to tell earlier 8243798Sgblack@eecs.umich.edu // stages to block. 8253798Sgblack@eecs.umich.edu if (resumeUnblocking || renameStatus[tid] != Unblocking) { 8262292SN/A toDecode->renameBlock[tid] = true; 8272292SN/A toDecode->renameUnblock[tid] = false; 8282292SN/A wroteToTimeBuffer = true; 8292292SN/A } 8302292SN/A 8312329SN/A // Rename can not go from SerializeStall to Blocked, otherwise 8322329SN/A // it would not know to complete the serialize stall. 8332301SN/A if (renameStatus[tid] != SerializeStall) { 8342292SN/A // Set status to Blocked. 8352292SN/A renameStatus[tid] = Blocked; 8362292SN/A return true; 8372292SN/A } 8382292SN/A } 8392292SN/A 8402292SN/A return false; 8412292SN/A} 8422292SN/A 8432292SN/Atemplate <class Impl> 8442292SN/Abool 8456221Snate@binkert.orgDefaultRename<Impl>::unblock(ThreadID tid) 8462292SN/A{ 8472292SN/A DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid); 8482292SN/A 8492292SN/A // Rename is done unblocking if the skid buffer is empty. 8502301SN/A if (skidBuffer[tid].empty() && renameStatus[tid] != SerializeStall) { 8512292SN/A 8522292SN/A DPRINTF(Rename, "[tid:%u]: Done unblocking.\n", tid); 8532292SN/A 8542292SN/A toDecode->renameUnblock[tid] = true; 8552292SN/A wroteToTimeBuffer = true; 8562292SN/A 8572292SN/A renameStatus[tid] = Running; 8582292SN/A return true; 8592292SN/A } 8602292SN/A 8612292SN/A return false; 8622292SN/A} 8632292SN/A 8642292SN/Atemplate <class Impl> 8652292SN/Avoid 8666221Snate@binkert.orgDefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) 8672292SN/A{ 8682980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 8692980Sgblack@eecs.umich.edu historyBuffer[tid].begin(); 8702292SN/A 8711060SN/A // After a syscall squashes everything, the history buffer may be empty 8721060SN/A // but the ROB may still be squashing instructions. 8732292SN/A if (historyBuffer[tid].empty()) { 8741060SN/A return; 8751060SN/A } 8761060SN/A 8771060SN/A // Go through the most recent instructions, undoing the mappings 8781060SN/A // they did and freeing up the registers. 8792292SN/A while (!historyBuffer[tid].empty() && 8809919Ssteve.reinhardt@amd.com hb_it->instSeqNum > squashed_seq_num) { 8812292SN/A assert(hb_it != historyBuffer[tid].end()); 8821062SN/A 8832292SN/A DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence " 8849919Ssteve.reinhardt@amd.com "number %i.\n", tid, hb_it->instSeqNum); 8851060SN/A 8869919Ssteve.reinhardt@amd.com // Undo the rename mapping only if it was really a change. 8879919Ssteve.reinhardt@amd.com // Special regs that are not really renamed (like misc regs 8889919Ssteve.reinhardt@amd.com // and the zero reg) can be recognized because the new mapping 8899919Ssteve.reinhardt@amd.com // is the same as the old one. While it would be merely a 8909919Ssteve.reinhardt@amd.com // waste of time to update the rename table, we definitely 8919919Ssteve.reinhardt@amd.com // don't want to put these on the free list. 8929919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 8939919Ssteve.reinhardt@amd.com // Tell the rename map to set the architected register to the 8949919Ssteve.reinhardt@amd.com // previous physical register that it was renamed to. 8959919Ssteve.reinhardt@amd.com renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg); 8961060SN/A 8979919Ssteve.reinhardt@amd.com // Put the renamed physical register back on the free list. 8989919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->newPhysReg); 8999919Ssteve.reinhardt@amd.com } 9001062SN/A 9012292SN/A historyBuffer[tid].erase(hb_it++); 9021061SN/A 9031062SN/A ++renameUndoneMaps; 9041060SN/A } 9051060SN/A} 9061060SN/A 9071060SN/Atemplate<class Impl> 9081060SN/Avoid 9096221Snate@binkert.orgDefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) 9101060SN/A{ 9112292SN/A DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the " 9122292SN/A "history buffer %u (size=%i), until [sn:%lli].\n", 9132292SN/A tid, tid, historyBuffer[tid].size(), inst_seq_num); 9142292SN/A 9152980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator hb_it = 9162980Sgblack@eecs.umich.edu historyBuffer[tid].end(); 9171060SN/A 9181061SN/A --hb_it; 9191060SN/A 9202292SN/A if (historyBuffer[tid].empty()) { 9212292SN/A DPRINTF(Rename, "[tid:%u]: History buffer is empty.\n", tid); 9222292SN/A return; 9232292SN/A } else if (hb_it->instSeqNum > inst_seq_num) { 9242292SN/A DPRINTF(Rename, "[tid:%u]: Old sequence number encountered. Ensure " 9252292SN/A "that a syscall happened recently.\n", tid); 9261060SN/A return; 9271060SN/A } 9281060SN/A 9292292SN/A // Commit all the renames up until (and including) the committed sequence 9302292SN/A // number. Some or even all of the committed instructions may not have 9312292SN/A // rename histories if they did not have destination registers that were 9322292SN/A // renamed. 9332292SN/A while (!historyBuffer[tid].empty() && 9342292SN/A hb_it != historyBuffer[tid].end() && 9359919Ssteve.reinhardt@amd.com hb_it->instSeqNum <= inst_seq_num) { 9361060SN/A 9372329SN/A DPRINTF(Rename, "[tid:%u]: Freeing up older rename of reg %i, " 9382329SN/A "[sn:%lli].\n", 9399919Ssteve.reinhardt@amd.com tid, hb_it->prevPhysReg, hb_it->instSeqNum); 9401061SN/A 9419919Ssteve.reinhardt@amd.com // Don't free special phys regs like misc and zero regs, which 9429919Ssteve.reinhardt@amd.com // can be recognized because the new mapping is the same as 9439919Ssteve.reinhardt@amd.com // the old one. 9449919Ssteve.reinhardt@amd.com if (hb_it->newPhysReg != hb_it->prevPhysReg) { 9459919Ssteve.reinhardt@amd.com freeList->addReg(hb_it->prevPhysReg); 9469919Ssteve.reinhardt@amd.com } 9479919Ssteve.reinhardt@amd.com 9482292SN/A ++renameCommittedMaps; 9491061SN/A 9502292SN/A historyBuffer[tid].erase(hb_it--); 9511060SN/A } 9521060SN/A} 9531060SN/A 9541061SN/Atemplate <class Impl> 9551061SN/Ainline void 9566221Snate@binkert.orgDefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid) 9571061SN/A{ 9589919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 9599919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 9601061SN/A unsigned num_src_regs = inst->numSrcRegs(); 9611061SN/A 9621061SN/A // Get the architectual register numbers from the source and 9639919Ssteve.reinhardt@amd.com // operands, and redirect them to the right physical register. 9642292SN/A for (int src_idx = 0; src_idx < num_src_regs; src_idx++) { 9651061SN/A RegIndex src_reg = inst->srcRegIdx(src_idx); 9669919Ssteve.reinhardt@amd.com RegIndex rel_src_reg; 9679919Ssteve.reinhardt@amd.com RegIndex flat_rel_src_reg; 9689919Ssteve.reinhardt@amd.com PhysRegIndex renamed_reg; 9699919Ssteve.reinhardt@amd.com 9709919Ssteve.reinhardt@amd.com switch (regIdxToClass(src_reg, &rel_src_reg)) { 9719913Ssteve.reinhardt@amd.com case IntRegClass: 9729919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenIntIndex(rel_src_reg); 9739919Ssteve.reinhardt@amd.com renamed_reg = map->lookupInt(flat_rel_src_reg); 9749919Ssteve.reinhardt@amd.com intRenameLookups++; 9759913Ssteve.reinhardt@amd.com break; 9769913Ssteve.reinhardt@amd.com 9779913Ssteve.reinhardt@amd.com case FloatRegClass: 9789919Ssteve.reinhardt@amd.com flat_rel_src_reg = tc->flattenFloatIndex(rel_src_reg); 9799919Ssteve.reinhardt@amd.com renamed_reg = map->lookupFloat(flat_rel_src_reg); 9809919Ssteve.reinhardt@amd.com fpRenameLookups++; 9819913Ssteve.reinhardt@amd.com break; 9829913Ssteve.reinhardt@amd.com 9839920Syasuko.eckert@amd.com case CCRegClass: 9849920Syasuko.eckert@amd.com flat_rel_src_reg = tc->flattenCCIndex(rel_src_reg); 9859920Syasuko.eckert@amd.com renamed_reg = map->lookupCC(flat_rel_src_reg); 9869920Syasuko.eckert@amd.com break; 9879920Syasuko.eckert@amd.com 9889913Ssteve.reinhardt@amd.com case MiscRegClass: 9899919Ssteve.reinhardt@amd.com // misc regs don't get flattened 9909919Ssteve.reinhardt@amd.com flat_rel_src_reg = rel_src_reg; 9919919Ssteve.reinhardt@amd.com renamed_reg = map->lookupMisc(flat_rel_src_reg); 9929913Ssteve.reinhardt@amd.com break; 9939913Ssteve.reinhardt@amd.com 9949913Ssteve.reinhardt@amd.com default: 9957649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", src_reg); 9963773Sgblack@eecs.umich.edu } 9974352Sgblack@eecs.umich.edu 9989919Ssteve.reinhardt@amd.com DPRINTF(Rename, "[tid:%u]: Looking up %s arch reg %i (flattened %i), " 9999919Ssteve.reinhardt@amd.com "got phys reg %i\n", tid, RegClassStrings[regIdxToClass(src_reg)], 10009919Ssteve.reinhardt@amd.com (int)src_reg, (int)flat_rel_src_reg, (int)renamed_reg); 10011061SN/A 10021061SN/A inst->renameSrcReg(src_idx, renamed_reg); 10031061SN/A 10042292SN/A // See if the register is ready or not. 10059919Ssteve.reinhardt@amd.com if (scoreboard->getReg(renamed_reg)) { 10067767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is ready.\n", 10077767Sgblack@eecs.umich.edu tid, renamed_reg); 10081061SN/A 10091061SN/A inst->markSrcRegReady(src_idx); 10104636Sgblack@eecs.umich.edu } else { 10117767Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Register %d is not ready.\n", 10127767Sgblack@eecs.umich.edu tid, renamed_reg); 10131061SN/A } 10141062SN/A 10151062SN/A ++renameRenameLookups; 10161061SN/A } 10171061SN/A} 10181061SN/A 10191061SN/Atemplate <class Impl> 10201061SN/Ainline void 10216221Snate@binkert.orgDefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid) 10221061SN/A{ 10239919Ssteve.reinhardt@amd.com ThreadContext *tc = inst->tcBase(); 10249919Ssteve.reinhardt@amd.com RenameMap *map = renameMap[tid]; 10251061SN/A unsigned num_dest_regs = inst->numDestRegs(); 10261061SN/A 10272292SN/A // Rename the destination registers. 10282292SN/A for (int dest_idx = 0; dest_idx < num_dest_regs; dest_idx++) { 10292292SN/A RegIndex dest_reg = inst->destRegIdx(dest_idx); 10309919Ssteve.reinhardt@amd.com RegIndex rel_dest_reg; 10319919Ssteve.reinhardt@amd.com RegIndex flat_rel_dest_reg; 10329919Ssteve.reinhardt@amd.com RegIndex flat_uni_dest_reg; 10339919Ssteve.reinhardt@amd.com typename RenameMap::RenameInfo rename_result; 10349919Ssteve.reinhardt@amd.com 10359919Ssteve.reinhardt@amd.com switch (regIdxToClass(dest_reg, &rel_dest_reg)) { 10369913Ssteve.reinhardt@amd.com case IntRegClass: 10379919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenIntIndex(rel_dest_reg); 10389919Ssteve.reinhardt@amd.com rename_result = map->renameInt(flat_rel_dest_reg); 10399919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg; // 1:1 mapping 10409913Ssteve.reinhardt@amd.com break; 10419913Ssteve.reinhardt@amd.com 10429913Ssteve.reinhardt@amd.com case FloatRegClass: 10439919Ssteve.reinhardt@amd.com flat_rel_dest_reg = tc->flattenFloatIndex(rel_dest_reg); 10449919Ssteve.reinhardt@amd.com rename_result = map->renameFloat(flat_rel_dest_reg); 10459919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::FP_Reg_Base; 10469913Ssteve.reinhardt@amd.com break; 10479913Ssteve.reinhardt@amd.com 10489920Syasuko.eckert@amd.com case CCRegClass: 10499920Syasuko.eckert@amd.com flat_rel_dest_reg = tc->flattenCCIndex(rel_dest_reg); 10509920Syasuko.eckert@amd.com rename_result = map->renameCC(flat_rel_dest_reg); 10519920Syasuko.eckert@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::CC_Reg_Base; 10529920Syasuko.eckert@amd.com break; 10539920Syasuko.eckert@amd.com 10549913Ssteve.reinhardt@amd.com case MiscRegClass: 10559919Ssteve.reinhardt@amd.com // misc regs don't get flattened 10569919Ssteve.reinhardt@amd.com flat_rel_dest_reg = rel_dest_reg; 10579919Ssteve.reinhardt@amd.com rename_result = map->renameMisc(flat_rel_dest_reg); 10589919Ssteve.reinhardt@amd.com flat_uni_dest_reg = flat_rel_dest_reg + TheISA::Misc_Reg_Base; 10599913Ssteve.reinhardt@amd.com break; 10609913Ssteve.reinhardt@amd.com 10619913Ssteve.reinhardt@amd.com default: 10627649Sminkyu.jeong@arm.com panic("Reg index is out of bound: %d.", dest_reg); 10633773Sgblack@eecs.umich.edu } 10643773Sgblack@eecs.umich.edu 10659919Ssteve.reinhardt@amd.com inst->flattenDestReg(dest_idx, flat_uni_dest_reg); 10661061SN/A 10679919Ssteve.reinhardt@amd.com // Mark Scoreboard entry as not ready 10689916Ssteve.reinhardt@amd.com scoreboard->unsetReg(rename_result.first); 10691062SN/A 10702292SN/A DPRINTF(Rename, "[tid:%u]: Renaming arch reg %i to physical " 10719919Ssteve.reinhardt@amd.com "reg %i.\n", tid, (int)flat_rel_dest_reg, 10722292SN/A (int)rename_result.first); 10731062SN/A 10742292SN/A // Record the rename information so that a history can be kept. 10759919Ssteve.reinhardt@amd.com RenameHistory hb_entry(inst->seqNum, flat_uni_dest_reg, 10762292SN/A rename_result.first, 10772292SN/A rename_result.second); 10781062SN/A 10792292SN/A historyBuffer[tid].push_front(hb_entry); 10801062SN/A 10812935Sksewell@umich.edu DPRINTF(Rename, "[tid:%u]: Adding instruction to history buffer " 10822935Sksewell@umich.edu "(size=%i), [sn:%lli].\n",tid, 10832935Sksewell@umich.edu historyBuffer[tid].size(), 10842292SN/A (*historyBuffer[tid].begin()).instSeqNum); 10851062SN/A 10862292SN/A // Tell the instruction to rename the appropriate destination 10872292SN/A // register (dest_idx) to the new physical register 10882292SN/A // (rename_result.first), and record the previous physical 10892292SN/A // register that the same logical register was renamed to 10902292SN/A // (rename_result.second). 10912292SN/A inst->renameDestReg(dest_idx, 10922292SN/A rename_result.first, 10932292SN/A rename_result.second); 10941062SN/A 10952292SN/A ++renameRenamedOperands; 10961061SN/A } 10971061SN/A} 10981061SN/A 10991061SN/Atemplate <class Impl> 11001061SN/Ainline int 11016221Snate@binkert.orgDefaultRename<Impl>::calcFreeROBEntries(ThreadID tid) 11021061SN/A{ 11032292SN/A int num_free = freeEntries[tid].robEntries - 11042292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11052292SN/A 11062292SN/A //DPRINTF(Rename,"[tid:%i]: %i rob free\n",tid,num_free); 11072292SN/A 11082292SN/A return num_free; 11091061SN/A} 11101061SN/A 11111061SN/Atemplate <class Impl> 11121061SN/Ainline int 11136221Snate@binkert.orgDefaultRename<Impl>::calcFreeIQEntries(ThreadID tid) 11141061SN/A{ 11152292SN/A int num_free = freeEntries[tid].iqEntries - 11162292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched); 11172292SN/A 11182292SN/A //DPRINTF(Rename,"[tid:%i]: %i iq free\n",tid,num_free); 11192292SN/A 11202292SN/A return num_free; 11212292SN/A} 11222292SN/A 11232292SN/Atemplate <class Impl> 11242292SN/Ainline int 11256221Snate@binkert.orgDefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid) 11262292SN/A{ 11272292SN/A int num_free = freeEntries[tid].lsqEntries - 11282292SN/A (instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ); 11292292SN/A 11302292SN/A //DPRINTF(Rename,"[tid:%i]: %i lsq free\n",tid,num_free); 11312292SN/A 11322292SN/A return num_free; 11332292SN/A} 11342292SN/A 11352292SN/Atemplate <class Impl> 11362292SN/Aunsigned 11372292SN/ADefaultRename<Impl>::validInsts() 11382292SN/A{ 11392292SN/A unsigned inst_count = 0; 11402292SN/A 11412292SN/A for (int i=0; i<fromDecode->size; i++) { 11422731Sktlim@umich.edu if (!fromDecode->insts[i]->isSquashed()) 11432292SN/A inst_count++; 11442292SN/A } 11452292SN/A 11462292SN/A return inst_count; 11472292SN/A} 11482292SN/A 11492292SN/Atemplate <class Impl> 11502292SN/Avoid 11516221Snate@binkert.orgDefaultRename<Impl>::readStallSignals(ThreadID tid) 11522292SN/A{ 11532292SN/A if (fromIEW->iewBlock[tid]) { 11542292SN/A stalls[tid].iew = true; 11552292SN/A } 11562292SN/A 11572292SN/A if (fromIEW->iewUnblock[tid]) { 11582292SN/A assert(stalls[tid].iew); 11592292SN/A stalls[tid].iew = false; 11602292SN/A } 11612292SN/A 11622292SN/A if (fromCommit->commitBlock[tid]) { 11632292SN/A stalls[tid].commit = true; 11642292SN/A } 11652292SN/A 11662292SN/A if (fromCommit->commitUnblock[tid]) { 11672292SN/A assert(stalls[tid].commit); 11682292SN/A stalls[tid].commit = false; 11692292SN/A } 11702292SN/A} 11712292SN/A 11722292SN/Atemplate <class Impl> 11732292SN/Abool 11746221Snate@binkert.orgDefaultRename<Impl>::checkStall(ThreadID tid) 11752292SN/A{ 11762292SN/A bool ret_val = false; 11772292SN/A 11782292SN/A if (stalls[tid].iew) { 11792292SN/A DPRINTF(Rename,"[tid:%i]: Stall from IEW stage detected.\n", tid); 11802292SN/A ret_val = true; 11812292SN/A } else if (stalls[tid].commit) { 11822292SN/A DPRINTF(Rename,"[tid:%i]: Stall from Commit stage detected.\n", tid); 11832292SN/A ret_val = true; 11842292SN/A } else if (calcFreeROBEntries(tid) <= 0) { 11852292SN/A DPRINTF(Rename,"[tid:%i]: Stall: ROB has 0 free entries.\n", tid); 11862292SN/A ret_val = true; 11872292SN/A } else if (calcFreeIQEntries(tid) <= 0) { 11882292SN/A DPRINTF(Rename,"[tid:%i]: Stall: IQ has 0 free entries.\n", tid); 11892292SN/A ret_val = true; 11902292SN/A } else if (calcFreeLSQEntries(tid) <= 0) { 11912292SN/A DPRINTF(Rename,"[tid:%i]: Stall: LSQ has 0 free entries.\n", tid); 11922292SN/A ret_val = true; 11932292SN/A } else if (renameMap[tid]->numFreeEntries() <= 0) { 11942292SN/A DPRINTF(Rename,"[tid:%i]: Stall: RenameMap has 0 free entries.\n", tid); 11952292SN/A ret_val = true; 11962301SN/A } else if (renameStatus[tid] == SerializeStall && 11972292SN/A (!emptyROB[tid] || instsInProgress[tid])) { 11982301SN/A DPRINTF(Rename,"[tid:%i]: Stall: Serialize stall and ROB is not " 11992292SN/A "empty.\n", 12002292SN/A tid); 12012292SN/A ret_val = true; 12022292SN/A } 12032292SN/A 12042292SN/A return ret_val; 12052292SN/A} 12062292SN/A 12072292SN/Atemplate <class Impl> 12082292SN/Avoid 12096221Snate@binkert.orgDefaultRename<Impl>::readFreeEntries(ThreadID tid) 12102292SN/A{ 12118607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedIQ) 12128607Sgblack@eecs.umich.edu freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries; 12132292SN/A 12148607Sgblack@eecs.umich.edu if (fromIEW->iewInfo[tid].usedLSQ) 12158607Sgblack@eecs.umich.edu freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries; 12162292SN/A 12172292SN/A if (fromCommit->commitInfo[tid].usedROB) { 12182292SN/A freeEntries[tid].robEntries = 12192292SN/A fromCommit->commitInfo[tid].freeROBEntries; 12202292SN/A emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB; 12212292SN/A } 12222292SN/A 12232292SN/A DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n", 12242292SN/A tid, 12252292SN/A freeEntries[tid].iqEntries, 12262292SN/A freeEntries[tid].robEntries, 12272292SN/A freeEntries[tid].lsqEntries); 12282292SN/A 12292292SN/A DPRINTF(Rename, "[tid:%i]: %i instructions not yet in ROB\n", 12302292SN/A tid, instsInProgress[tid]); 12312292SN/A} 12322292SN/A 12332292SN/Atemplate <class Impl> 12342292SN/Abool 12356221Snate@binkert.orgDefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid) 12362292SN/A{ 12372292SN/A // Check if there's a squash signal, squash if there is 12382292SN/A // Check stall signals, block if necessary. 12392292SN/A // If status was blocked 12402292SN/A // check if stall conditions have passed 12412292SN/A // if so then go to unblocking 12422292SN/A // If status was Squashing 12432292SN/A // check if squashing is not high. Switch to running this cycle. 12442301SN/A // If status was serialize stall 12452292SN/A // check if ROB is empty and no insts are in flight to the ROB 12462292SN/A 12472292SN/A readFreeEntries(tid); 12482292SN/A readStallSignals(tid); 12492292SN/A 12502292SN/A if (fromCommit->commitInfo[tid].squash) { 12512292SN/A DPRINTF(Rename, "[tid:%u]: Squashing instructions due to squash from " 12522292SN/A "commit.\n", tid); 12532292SN/A 12544632Sgblack@eecs.umich.edu squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 12552292SN/A 12562292SN/A return true; 12572292SN/A } 12582292SN/A 12592292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 12602292SN/A DPRINTF(Rename, "[tid:%u]: ROB is still squashing.\n", tid); 12612292SN/A 12622292SN/A renameStatus[tid] = Squashing; 12632292SN/A 12642292SN/A return true; 12652292SN/A } 12662292SN/A 12672292SN/A if (checkStall(tid)) { 12682292SN/A return block(tid); 12692292SN/A } 12702292SN/A 12712292SN/A if (renameStatus[tid] == Blocked) { 12722292SN/A DPRINTF(Rename, "[tid:%u]: Done blocking, switching to unblocking.\n", 12732292SN/A tid); 12742292SN/A 12752292SN/A renameStatus[tid] = Unblocking; 12762292SN/A 12772292SN/A unblock(tid); 12782292SN/A 12792292SN/A return true; 12802292SN/A } 12812292SN/A 12822292SN/A if (renameStatus[tid] == Squashing) { 12832292SN/A // Switch status to running if rename isn't being told to block or 12842292SN/A // squash this cycle. 12853798Sgblack@eecs.umich.edu if (resumeSerialize) { 12863798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to serialize.\n", 12873798Sgblack@eecs.umich.edu tid); 12882292SN/A 12893798Sgblack@eecs.umich.edu renameStatus[tid] = SerializeStall; 12903798Sgblack@eecs.umich.edu return true; 12913798Sgblack@eecs.umich.edu } else if (resumeUnblocking) { 12923798Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to unblocking.\n", 12933798Sgblack@eecs.umich.edu tid); 12943798Sgblack@eecs.umich.edu renameStatus[tid] = Unblocking; 12953798Sgblack@eecs.umich.edu return true; 12963798Sgblack@eecs.umich.edu } else { 12973788Sgblack@eecs.umich.edu DPRINTF(Rename, "[tid:%u]: Done squashing, switching to running.\n", 12983788Sgblack@eecs.umich.edu tid); 12992292SN/A 13003788Sgblack@eecs.umich.edu renameStatus[tid] = Running; 13013788Sgblack@eecs.umich.edu return false; 13023788Sgblack@eecs.umich.edu } 13032292SN/A } 13042292SN/A 13052301SN/A if (renameStatus[tid] == SerializeStall) { 13062292SN/A // Stall ends once the ROB is free. 13072301SN/A DPRINTF(Rename, "[tid:%u]: Done with serialize stall, switching to " 13082292SN/A "unblocking.\n", tid); 13092292SN/A 13102301SN/A DynInstPtr serial_inst = serializeInst[tid]; 13112292SN/A 13122292SN/A renameStatus[tid] = Unblocking; 13132292SN/A 13142292SN/A unblock(tid); 13152292SN/A 13162292SN/A DPRINTF(Rename, "[tid:%u]: Processing instruction [%lli] with " 13177720Sgblack@eecs.umich.edu "PC %s.\n", tid, serial_inst->seqNum, serial_inst->pcState()); 13182292SN/A 13192292SN/A // Put instruction into queue here. 13202301SN/A serial_inst->clearSerializeBefore(); 13212292SN/A 13222292SN/A if (!skidBuffer[tid].empty()) { 13232301SN/A skidBuffer[tid].push_front(serial_inst); 13242292SN/A } else { 13252301SN/A insts[tid].push_front(serial_inst); 13262292SN/A } 13272292SN/A 13282292SN/A DPRINTF(Rename, "[tid:%u]: Instruction must be processed by rename." 13292703Sktlim@umich.edu " Adding to front of list.\n", tid); 13302292SN/A 13312301SN/A serializeInst[tid] = NULL; 13322292SN/A 13332292SN/A return true; 13342292SN/A } 13352292SN/A 13362292SN/A // If we've reached this point, we have not gotten any signals that 13372292SN/A // cause rename to change its status. Rename remains the same as before. 13382292SN/A return false; 13391061SN/A} 13401061SN/A 13411060SN/Atemplate<class Impl> 13421060SN/Avoid 13436221Snate@binkert.orgDefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid) 13441060SN/A{ 13452292SN/A if (inst_list.empty()) { 13462292SN/A // Mark a bit to say that I must serialize on the next instruction. 13472292SN/A serializeOnNextInst[tid] = true; 13481060SN/A return; 13491060SN/A } 13501060SN/A 13512292SN/A // Set the next instruction as serializing. 13522292SN/A inst_list.front()->setSerializeBefore(); 13532292SN/A} 13542292SN/A 13552292SN/Atemplate <class Impl> 13562292SN/Ainline void 13572292SN/ADefaultRename<Impl>::incrFullStat(const FullSource &source) 13582292SN/A{ 13592292SN/A switch (source) { 13602292SN/A case ROB: 13612292SN/A ++renameROBFullEvents; 13622292SN/A break; 13632292SN/A case IQ: 13642292SN/A ++renameIQFullEvents; 13652292SN/A break; 13662292SN/A case LSQ: 13672292SN/A ++renameLSQFullEvents; 13682292SN/A break; 13692292SN/A default: 13702292SN/A panic("Rename full stall stat should be incremented for a reason!"); 13712292SN/A break; 13721060SN/A } 13732292SN/A} 13741060SN/A 13752292SN/Atemplate <class Impl> 13762292SN/Avoid 13772292SN/ADefaultRename<Impl>::dumpHistory() 13782292SN/A{ 13792980Sgblack@eecs.umich.edu typename std::list<RenameHistory>::iterator buf_it; 13801060SN/A 13816221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 13821060SN/A 13836221Snate@binkert.org buf_it = historyBuffer[tid].begin(); 13841060SN/A 13856221Snate@binkert.org while (buf_it != historyBuffer[tid].end()) { 13862292SN/A cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys " 13872292SN/A "reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg, 13882292SN/A (int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg); 13891060SN/A 13902292SN/A buf_it++; 13911062SN/A } 13921060SN/A } 13931060SN/A} 13949944Smatt.horsnell@ARM.com 13959944Smatt.horsnell@ARM.com#endif//__CPU_O3_RENAME_IMPL_HH__ 1396