rename.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo:
30// Fix up trap and barrier handling.
31// May want to have different statuses to differentiate the different stall
32// conditions.
33
34#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
35#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
36
37#include <list>
38
39#include "base/statistics.hh"
40#include "base/timebuf.hh"
41
42// Will need rename maps for both the int reg file and fp reg file.
43// Or change rename map class to handle both. (RegFile handles both.)
44template<class Impl>
45class SimpleRename
46{
47  public:
48    // Typedefs from the Impl.
49    typedef typename Impl::CPUPol CPUPol;
50    typedef typename Impl::DynInstPtr DynInstPtr;
51    typedef typename Impl::FullCPU FullCPU;
52    typedef typename Impl::Params Params;
53
54    typedef typename CPUPol::FetchStruct FetchStruct;
55    typedef typename CPUPol::DecodeStruct DecodeStruct;
56    typedef typename CPUPol::RenameStruct RenameStruct;
57    typedef typename CPUPol::TimeStruct TimeStruct;
58
59    // Typedefs from the CPUPol
60    typedef typename CPUPol::FreeList FreeList;
61    typedef typename CPUPol::RenameMap RenameMap;
62
63    // Typedefs from the ISA.
64    typedef TheISA::RegIndex RegIndex;
65
66  public:
67    // Rename will block if ROB becomes full or issue queue becomes full,
68    // or there are no free registers to rename to.
69    // Only case where rename squashes is if IEW squashes.
70    enum Status {
71        Running,
72        Idle,
73        Squashing,
74        Blocked,
75        Unblocking,
76        BarrierStall
77    };
78
79  private:
80    Status _status;
81
82  public:
83    SimpleRename(Params &params);
84
85    void regStats();
86
87    void setCPU(FullCPU *cpu_ptr);
88
89    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
90
91    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
92
93    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
94
95    void setRenameMap(RenameMap *rm_ptr);
96
97    void setFreeList(FreeList *fl_ptr);
98
99    void dumpHistory();
100
101    void tick();
102
103    void rename();
104
105    void squash();
106
107  private:
108    void block();
109
110    inline void unblock();
111
112    void doSquash();
113
114    void removeFromHistory(InstSeqNum inst_seq_num);
115
116    inline void renameSrcRegs(DynInstPtr &inst);
117
118    inline void renameDestRegs(DynInstPtr &inst);
119
120    inline int calcFreeROBEntries();
121
122    inline int calcFreeIQEntries();
123
124    /** Holds the previous information for each rename.
125     *  Note that often times the inst may have been deleted, so only access
126     *  the pointer for the address and do not dereference it.
127     */
128    struct RenameHistory {
129        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
130                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
131            : instSeqNum(_instSeqNum), archReg(_archReg),
132              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
133              placeHolder(false)
134        {
135        }
136
137        /** Constructor used specifically for cases where a place holder
138         *  rename history entry is being made.
139         */
140        RenameHistory(InstSeqNum _instSeqNum)
141            : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
142              prevPhysReg(0), placeHolder(true)
143        {
144        }
145
146        InstSeqNum instSeqNum;
147        RegIndex archReg;
148        PhysRegIndex newPhysReg;
149        PhysRegIndex prevPhysReg;
150        bool placeHolder;
151    };
152
153    std::list<RenameHistory> historyBuffer;
154
155    /** CPU interface. */
156    FullCPU *cpu;
157
158    // Interfaces to objects outside of rename.
159    /** Time buffer interface. */
160    TimeBuffer<TimeStruct> *timeBuffer;
161
162    /** Wire to get IEW's output from backwards time buffer. */
163    typename TimeBuffer<TimeStruct>::wire fromIEW;
164
165    /** Wire to get commit's output from backwards time buffer. */
166    typename TimeBuffer<TimeStruct>::wire fromCommit;
167
168    /** Wire to write infromation heading to previous stages. */
169    // Might not be the best name as not only decode will read it.
170    typename TimeBuffer<TimeStruct>::wire toDecode;
171
172    /** Rename instruction queue. */
173    TimeBuffer<RenameStruct> *renameQueue;
174
175    /** Wire to write any information heading to IEW. */
176    typename TimeBuffer<RenameStruct>::wire toIEW;
177
178    /** Decode instruction queue interface. */
179    TimeBuffer<DecodeStruct> *decodeQueue;
180
181    /** Wire to get decode's output from decode queue. */
182    typename TimeBuffer<DecodeStruct>::wire fromDecode;
183
184    /** Skid buffer between rename and decode. */
185    std::queue<DecodeStruct> skidBuffer;
186
187    /** Rename map interface. */
188    SimpleRenameMap *renameMap;
189
190    /** Free list interface. */
191    FreeList *freeList;
192
193    /** Delay between iew and rename, in ticks. */
194    int iewToRenameDelay;
195
196    /** Delay between decode and rename, in ticks. */
197    int decodeToRenameDelay;
198
199    /** Delay between commit and rename, in ticks. */
200    unsigned commitToRenameDelay;
201
202    /** Rename width, in instructions. */
203    unsigned renameWidth;
204
205    /** Commit width, in instructions.  Used so rename knows how many
206     *  instructions might have freed registers in the previous cycle.
207     */
208    unsigned commitWidth;
209
210    /** The instruction that rename is currently on.  It needs to have
211     *  persistent state so that when a stall occurs in the middle of a
212     *  group of instructions, it can restart at the proper instruction.
213     */
214    unsigned numInst;
215
216    Stats::Scalar<> renameSquashCycles;
217    Stats::Scalar<> renameIdleCycles;
218    Stats::Scalar<> renameBlockCycles;
219    Stats::Scalar<> renameUnblockCycles;
220    Stats::Scalar<> renameRenamedInsts;
221    Stats::Scalar<> renameSquashedInsts;
222    Stats::Scalar<> renameROBFullEvents;
223    Stats::Scalar<> renameIQFullEvents;
224    Stats::Scalar<> renameFullRegistersEvents;
225    Stats::Scalar<> renameRenamedOperands;
226    Stats::Scalar<> renameRenameLookups;
227    Stats::Scalar<> renameHBPlaceHolders;
228    Stats::Scalar<> renameCommittedMaps;
229    Stats::Scalar<> renameUndoneMaps;
230    Stats::Scalar<> renameValidUndoneMaps;
231};
232
233#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
234