rename.hh revision 1689 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29// Todo:
30// Fix up trap and barrier handling.
31// May want to have different statuses to differentiate the different stall
32// conditions.
33
34#ifndef __CPU_BETA_CPU_SIMPLE_RENAME_HH__
35#define __CPU_BETA_CPU_SIMPLE_RENAME_HH__
36
37#include <list>
38
39#include "base/statistics.hh"
40#include "base/timebuf.hh"
41
42// Will need rename maps for both the int reg file and fp reg file.
43// Or change rename map class to handle both. (RegFile handles both.)
44template<class Impl>
45class SimpleRename
46{
47  public:
48    // Typedefs from the Impl.
49    typedef typename Impl::ISA ISA;
50    typedef typename Impl::CPUPol CPUPol;
51    typedef typename Impl::DynInstPtr DynInstPtr;
52    typedef typename Impl::FullCPU FullCPU;
53    typedef typename Impl::Params Params;
54
55    typedef typename CPUPol::FetchStruct FetchStruct;
56    typedef typename CPUPol::DecodeStruct DecodeStruct;
57    typedef typename CPUPol::RenameStruct RenameStruct;
58    typedef typename CPUPol::TimeStruct TimeStruct;
59
60    // Typedefs from the CPUPol
61    typedef typename CPUPol::FreeList FreeList;
62    typedef typename CPUPol::RenameMap RenameMap;
63
64    // Typedefs from the ISA.
65    typedef typename ISA::Addr Addr;
66
67  public:
68    // Rename will block if ROB becomes full or issue queue becomes full,
69    // or there are no free registers to rename to.
70    // Only case where rename squashes is if IEW squashes.
71    enum Status {
72        Running,
73        Idle,
74        Squashing,
75        Blocked,
76        Unblocking,
77        BarrierStall
78    };
79
80  private:
81    Status _status;
82
83  public:
84    SimpleRename(Params &params);
85
86    void regStats();
87
88    void setCPU(FullCPU *cpu_ptr);
89
90    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
91
92    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
93
94    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
95
96    void setRenameMap(RenameMap *rm_ptr);
97
98    void setFreeList(FreeList *fl_ptr);
99
100    void dumpHistory();
101
102    void tick();
103
104    void rename();
105
106    void squash();
107
108  private:
109    void block();
110
111    inline void unblock();
112
113    void doSquash();
114
115    void removeFromHistory(InstSeqNum inst_seq_num);
116
117    inline void renameSrcRegs(DynInstPtr &inst);
118
119    inline void renameDestRegs(DynInstPtr &inst);
120
121    inline int calcFreeROBEntries();
122
123    inline int calcFreeIQEntries();
124
125    /** Holds the previous information for each rename.
126     *  Note that often times the inst may have been deleted, so only access
127     *  the pointer for the address and do not dereference it.
128     */
129    struct RenameHistory {
130        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
131                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
132            : instSeqNum(_instSeqNum), archReg(_archReg),
133              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
134              placeHolder(false)
135        {
136        }
137
138        /** Constructor used specifically for cases where a place holder
139         *  rename history entry is being made.
140         */
141        RenameHistory(InstSeqNum _instSeqNum)
142            : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
143              prevPhysReg(0), placeHolder(true)
144        {
145        }
146
147        InstSeqNum instSeqNum;
148        RegIndex archReg;
149        PhysRegIndex newPhysReg;
150        PhysRegIndex prevPhysReg;
151        bool placeHolder;
152    };
153
154    std::list<RenameHistory> historyBuffer;
155
156    /** CPU interface. */
157    FullCPU *cpu;
158
159    // Interfaces to objects outside of rename.
160    /** Time buffer interface. */
161    TimeBuffer<TimeStruct> *timeBuffer;
162
163    /** Wire to get IEW's output from backwards time buffer. */
164    typename TimeBuffer<TimeStruct>::wire fromIEW;
165
166    /** Wire to get commit's output from backwards time buffer. */
167    typename TimeBuffer<TimeStruct>::wire fromCommit;
168
169    /** Wire to write infromation heading to previous stages. */
170    // Might not be the best name as not only decode will read it.
171    typename TimeBuffer<TimeStruct>::wire toDecode;
172
173    /** Rename instruction queue. */
174    TimeBuffer<RenameStruct> *renameQueue;
175
176    /** Wire to write any information heading to IEW. */
177    typename TimeBuffer<RenameStruct>::wire toIEW;
178
179    /** Decode instruction queue interface. */
180    TimeBuffer<DecodeStruct> *decodeQueue;
181
182    /** Wire to get decode's output from decode queue. */
183    typename TimeBuffer<DecodeStruct>::wire fromDecode;
184
185    /** Skid buffer between rename and decode. */
186    std::queue<DecodeStruct> skidBuffer;
187
188    /** Rename map interface. */
189    SimpleRenameMap *renameMap;
190
191    /** Free list interface. */
192    FreeList *freeList;
193
194    /** Delay between iew and rename, in ticks. */
195    int iewToRenameDelay;
196
197    /** Delay between decode and rename, in ticks. */
198    int decodeToRenameDelay;
199
200    /** Delay between commit and rename, in ticks. */
201    unsigned commitToRenameDelay;
202
203    /** Rename width, in instructions. */
204    unsigned renameWidth;
205
206    /** Commit width, in instructions.  Used so rename knows how many
207     *  instructions might have freed registers in the previous cycle.
208     */
209    unsigned commitWidth;
210
211    /** The instruction that rename is currently on.  It needs to have
212     *  persistent state so that when a stall occurs in the middle of a
213     *  group of instructions, it can restart at the proper instruction.
214     */
215    unsigned numInst;
216
217    Stats::Scalar<> renameSquashCycles;
218    Stats::Scalar<> renameIdleCycles;
219    Stats::Scalar<> renameBlockCycles;
220    Stats::Scalar<> renameUnblockCycles;
221    Stats::Scalar<> renameRenamedInsts;
222    Stats::Scalar<> renameSquashedInsts;
223    Stats::Scalar<> renameROBFullEvents;
224    Stats::Scalar<> renameIQFullEvents;
225    Stats::Scalar<> renameFullRegistersEvents;
226    Stats::Scalar<> renameRenamedOperands;
227    Stats::Scalar<> renameRenameLookups;
228    Stats::Scalar<> renameHBPlaceHolders;
229    Stats::Scalar<> renameCommittedMaps;
230    Stats::Scalar<> renameUndoneMaps;
231    Stats::Scalar<> renameValidUndoneMaps;
232};
233
234#endif // __CPU_BETA_CPU_SIMPLE_RENAME_HH__
235