rename.hh revision 5999
11689SN/A/*
22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
312292SN/A#ifndef __CPU_O3_RENAME_HH__
322292SN/A#define __CPU_O3_RENAME_HH__
331060SN/A
341060SN/A#include <list>
351060SN/A
361461SN/A#include "base/statistics.hh"
371060SN/A#include "base/timebuf.hh"
381060SN/A
395529Snate@binkert.orgclass DerivO3CPUParams;
405529Snate@binkert.org
412292SN/A/**
422329SN/A * DefaultRename handles both single threaded and SMT rename. Its
432329SN/A * width is specified by the parameters; each cycle it tries to rename
442329SN/A * that many instructions. It holds onto the rename history of all
452329SN/A * instructions with destination registers, storing the
462329SN/A * arch. register, the new physical register, and the old physical
472329SN/A * register, to allow for undoing of mappings if squashing happens, or
482329SN/A * freeing up registers upon commit. Rename handles blocking if the
492329SN/A * ROB, IQ, or LSQ is going to be full. Rename also handles barriers,
502329SN/A * and does so by stalling on the instruction until the ROB is empty
512329SN/A * and there are no instructions in flight to the ROB.
522292SN/A */
531060SN/Atemplate<class Impl>
542292SN/Aclass DefaultRename
551060SN/A{
561060SN/A  public:
571060SN/A    // Typedefs from the Impl.
581060SN/A    typedef typename Impl::CPUPol CPUPol;
591061SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
602733Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
611060SN/A
622292SN/A    // Typedefs from the CPUPol
631061SN/A    typedef typename CPUPol::DecodeStruct DecodeStruct;
641061SN/A    typedef typename CPUPol::RenameStruct RenameStruct;
651061SN/A    typedef typename CPUPol::TimeStruct TimeStruct;
661060SN/A    typedef typename CPUPol::FreeList FreeList;
671060SN/A    typedef typename CPUPol::RenameMap RenameMap;
682292SN/A    // These are used only for initialization.
692292SN/A    typedef typename CPUPol::IEW IEW;
702292SN/A    typedef typename CPUPol::Commit Commit;
711060SN/A
721060SN/A    // Typedefs from the ISA.
732107SN/A    typedef TheISA::RegIndex RegIndex;
741060SN/A
752329SN/A    // A list is used to queue the instructions.  Barrier insts must
762329SN/A    // be added to the front of the list, which is the only reason for
772329SN/A    // using a list instead of a queue. (Most other stages use a
782329SN/A    // queue)
792292SN/A    typedef std::list<DynInstPtr> InstQueue;
802935Sksewell@umich.edu    typedef typename std::list<DynInstPtr>::iterator ListIt;
812292SN/A
821060SN/A  public:
832329SN/A    /** Overall rename status. Used to determine if the CPU can
842329SN/A     * deschedule itself due to a lack of activity.
852292SN/A     */
862292SN/A    enum RenameStatus {
872292SN/A        Active,
882292SN/A        Inactive
892292SN/A    };
902292SN/A
912292SN/A    /** Individual thread status. */
922292SN/A    enum ThreadStatus {
931060SN/A        Running,
941060SN/A        Idle,
952292SN/A        StartSquash,
961060SN/A        Squashing,
971060SN/A        Blocked,
981060SN/A        Unblocking,
992301SN/A        SerializeStall
1001060SN/A    };
1011060SN/A
1021060SN/A  private:
1032292SN/A    /** Rename status. */
1042292SN/A    RenameStatus _status;
1052292SN/A
1062292SN/A    /** Per-thread status. */
1072292SN/A    ThreadStatus renameStatus[Impl::MaxThreads];
1081060SN/A
1091060SN/A  public:
1102292SN/A    /** DefaultRename constructor. */
1115529Snate@binkert.org    DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
1121060SN/A
1132292SN/A    /** Returns the name of rename. */
1142292SN/A    std::string name() const;
1152292SN/A
1162292SN/A    /** Registers statistics. */
1171062SN/A    void regStats();
1181062SN/A
1192292SN/A    /** Sets the main backwards communication time buffer pointer. */
1201060SN/A    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
1211060SN/A
1222292SN/A    /** Sets pointer to time buffer used to communicate to the next stage. */
1231060SN/A    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
1241060SN/A
1252292SN/A    /** Sets pointer to time buffer coming from decode. */
1261060SN/A    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
1271060SN/A
1282292SN/A    /** Sets pointer to IEW stage. Used only for initialization. */
1292292SN/A    void setIEWStage(IEW *iew_stage)
1302292SN/A    { iew_ptr = iew_stage; }
1311060SN/A
1322292SN/A    /** Sets pointer to commit stage. Used only for initialization. */
1332292SN/A    void setCommitStage(Commit *commit_stage)
1342292SN/A    { commit_ptr = commit_stage; }
1352292SN/A
1362292SN/A  private:
1372292SN/A    /** Pointer to IEW stage. Used only for initialization. */
1382292SN/A    IEW *iew_ptr;
1392292SN/A
1402292SN/A    /** Pointer to commit stage. Used only for initialization. */
1412292SN/A    Commit *commit_ptr;
1422292SN/A
1432292SN/A  public:
1442292SN/A    /** Initializes variables for the stage. */
1452292SN/A    void initStage();
1462292SN/A
1472292SN/A    /** Sets pointer to list of active threads. */
1482292SN/A    void setActiveThreads(std::list<unsigned> *at_ptr);
1492292SN/A
1502292SN/A    /** Sets pointer to rename maps (per-thread structures). */
1512292SN/A    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
1522292SN/A
1532292SN/A    /** Sets pointer to the free list. */
1541060SN/A    void setFreeList(FreeList *fl_ptr);
1551060SN/A
1562292SN/A    /** Sets pointer to the scoreboard. */
1572292SN/A    void setScoreboard(Scoreboard *_scoreboard);
1582292SN/A
1592843Sktlim@umich.edu    /** Drains the rename stage. */
1602863Sktlim@umich.edu    bool drain();
1612843Sktlim@umich.edu
1622843Sktlim@umich.edu    /** Resumes execution after a drain. */
1632843Sktlim@umich.edu    void resume() { }
1642843Sktlim@umich.edu
1652348SN/A    /** Switches out the rename stage. */
1662307SN/A    void switchOut();
1672307SN/A
1682348SN/A    /** Takes over from another CPU's thread. */
1692307SN/A    void takeOverFrom();
1702307SN/A
1712292SN/A    /** Squashes all instructions in a thread. */
1722935Sksewell@umich.edu    void squash(const InstSeqNum &squash_seq_num, unsigned tid);
1732292SN/A
1742292SN/A    /** Ticks rename, which processes all input signals and attempts to rename
1752292SN/A     * as many instructions as possible.
1762292SN/A     */
1772292SN/A    void tick();
1782292SN/A
1792292SN/A    /** Debugging function used to dump history buffer of renamings. */
1801060SN/A    void dumpHistory();
1811060SN/A
1822292SN/A  private:
1832292SN/A    /** Determines what to do based on rename's current status.
1842292SN/A     * @param status_change rename() sets this variable if there was a status
1852292SN/A     * change (ie switching from blocking to unblocking).
1862292SN/A     * @param tid Thread id to rename instructions from.
1872292SN/A     */
1882292SN/A    void rename(bool &status_change, unsigned tid);
1891060SN/A
1902292SN/A    /** Renames instructions for the given thread. Also handles serializing
1912292SN/A     * instructions.
1922292SN/A     */
1932292SN/A    void renameInsts(unsigned tid);
1941060SN/A
1952292SN/A    /** Inserts unused instructions from a given thread into the skid buffer,
1962292SN/A     * to be renamed once rename unblocks.
1972292SN/A     */
1982292SN/A    void skidInsert(unsigned tid);
1991060SN/A
2002292SN/A    /** Separates instructions from decode into individual lists of instructions
2012292SN/A     * sorted by thread.
2022292SN/A     */
2032292SN/A    void sortInsts();
2041060SN/A
2052292SN/A    /** Returns if all of the skid buffers are empty. */
2062292SN/A    bool skidsEmpty();
2071060SN/A
2082292SN/A    /** Updates overall rename status based on all of the threads' statuses. */
2092292SN/A    void updateStatus();
2101060SN/A
2112292SN/A    /** Switches rename to blocking, and signals back that rename has become
2122292SN/A     * blocked.
2132292SN/A     * @return Returns true if there is a status change.
2142292SN/A     */
2152292SN/A    bool block(unsigned tid);
2161060SN/A
2172292SN/A    /** Switches rename to unblocking if the skid buffer is empty, and signals
2182292SN/A     * back that rename has unblocked.
2192292SN/A     * @return Returns true if there is a status change.
2202292SN/A     */
2212292SN/A    bool unblock(unsigned tid);
2221061SN/A
2232292SN/A    /** Executes actual squash, removing squashed instructions. */
2242935Sksewell@umich.edu    void doSquash(const InstSeqNum &squash_seq_num, unsigned tid);
2251061SN/A
2262292SN/A    /** Removes a committed instruction's rename history. */
2272292SN/A    void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
2281061SN/A
2292292SN/A    /** Renames the source registers of an instruction. */
2302292SN/A    inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
2311061SN/A
2322292SN/A    /** Renames the destination registers of an instruction. */
2332292SN/A    inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
2342292SN/A
2352292SN/A    /** Calculates the number of free ROB entries for a specific thread. */
2362292SN/A    inline int calcFreeROBEntries(unsigned tid);
2372292SN/A
2382292SN/A    /** Calculates the number of free IQ entries for a specific thread. */
2392292SN/A    inline int calcFreeIQEntries(unsigned tid);
2402292SN/A
2412292SN/A    /** Calculates the number of free LSQ entries for a specific thread. */
2422292SN/A    inline int calcFreeLSQEntries(unsigned tid);
2432292SN/A
2442292SN/A    /** Returns the number of valid instructions coming from decode. */
2452292SN/A    unsigned validInsts();
2462292SN/A
2472292SN/A    /** Reads signals telling rename to block/unblock. */
2482292SN/A    void readStallSignals(unsigned tid);
2492292SN/A
2502292SN/A    /** Checks if any stages are telling rename to block. */
2512292SN/A    bool checkStall(unsigned tid);
2522292SN/A
2532348SN/A    /** Gets the number of free entries for a specific thread. */
2542292SN/A    void readFreeEntries(unsigned tid);
2552292SN/A
2562348SN/A    /** Checks the signals and updates the status. */
2572292SN/A    bool checkSignalsAndUpdate(unsigned tid);
2582292SN/A
2592292SN/A    /** Either serializes on the next instruction available in the InstQueue,
2602292SN/A     * or records that it must serialize on the next instruction to enter
2612292SN/A     * rename.
2622292SN/A     * @param inst_list The list of younger, unprocessed instructions for the
2632292SN/A     * thread that has the serializeAfter instruction.
2642292SN/A     * @param tid The thread id.
2652292SN/A     */
2662292SN/A    void serializeAfter(InstQueue &inst_list, unsigned tid);
2672292SN/A
2682292SN/A    /** Holds the information for each destination register rename. It holds
2692292SN/A     * the instruction's sequence number, the arch register, the old physical
2702292SN/A     * register for that arch. register, and the new physical register.
2711060SN/A     */
2721060SN/A    struct RenameHistory {
2731060SN/A        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
2741060SN/A                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
2751060SN/A            : instSeqNum(_instSeqNum), archReg(_archReg),
2762292SN/A              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
2771060SN/A        {
2781060SN/A        }
2791060SN/A
2802292SN/A        /** The sequence number of the instruction that renamed. */
2811060SN/A        InstSeqNum instSeqNum;
2822292SN/A        /** The architectural register index that was renamed. */
2831060SN/A        RegIndex archReg;
2842292SN/A        /** The new physical register that the arch. register is renamed to. */
2851060SN/A        PhysRegIndex newPhysReg;
2862292SN/A        /** The old physical register that the arch. register was renamed to. */
2871060SN/A        PhysRegIndex prevPhysReg;
2881060SN/A    };
2891060SN/A
2902292SN/A    /** A per-thread list of all destination register renames, used to either
2912292SN/A     * undo rename mappings or free old physical registers.
2922292SN/A     */
2932292SN/A    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
2941060SN/A
2952292SN/A    /** Pointer to CPU. */
2962733Sktlim@umich.edu    O3CPU *cpu;
2971060SN/A
2982292SN/A    /** Pointer to main time buffer used for backwards communication. */
2991060SN/A    TimeBuffer<TimeStruct> *timeBuffer;
3001060SN/A
3011060SN/A    /** Wire to get IEW's output from backwards time buffer. */
3021060SN/A    typename TimeBuffer<TimeStruct>::wire fromIEW;
3031060SN/A
3041060SN/A    /** Wire to get commit's output from backwards time buffer. */
3051060SN/A    typename TimeBuffer<TimeStruct>::wire fromCommit;
3061060SN/A
3071060SN/A    /** Wire to write infromation heading to previous stages. */
3081060SN/A    typename TimeBuffer<TimeStruct>::wire toDecode;
3091060SN/A
3101060SN/A    /** Rename instruction queue. */
3111060SN/A    TimeBuffer<RenameStruct> *renameQueue;
3121060SN/A
3131060SN/A    /** Wire to write any information heading to IEW. */
3141060SN/A    typename TimeBuffer<RenameStruct>::wire toIEW;
3151060SN/A
3161060SN/A    /** Decode instruction queue interface. */
3171060SN/A    TimeBuffer<DecodeStruct> *decodeQueue;
3181060SN/A
3191060SN/A    /** Wire to get decode's output from decode queue. */
3201060SN/A    typename TimeBuffer<DecodeStruct>::wire fromDecode;
3211060SN/A
3222292SN/A    /** Queue of all instructions coming from decode this cycle. */
3232292SN/A    InstQueue insts[Impl::MaxThreads];
3242292SN/A
3251060SN/A    /** Skid buffer between rename and decode. */
3262292SN/A    InstQueue skidBuffer[Impl::MaxThreads];
3271060SN/A
3281060SN/A    /** Rename map interface. */
3292292SN/A    RenameMap *renameMap[Impl::MaxThreads];
3301060SN/A
3311060SN/A    /** Free list interface. */
3321060SN/A    FreeList *freeList;
3331060SN/A
3342292SN/A    /** Pointer to the list of active threads. */
3352292SN/A    std::list<unsigned> *activeThreads;
3362292SN/A
3372292SN/A    /** Pointer to the scoreboard. */
3382292SN/A    Scoreboard *scoreboard;
3392292SN/A
3402292SN/A    /** Count of instructions in progress that have been sent off to the IQ
3412292SN/A     * and ROB, but are not yet included in their occupancy counts.
3422292SN/A     */
3432292SN/A    int instsInProgress[Impl::MaxThreads];
3442292SN/A
3452292SN/A    /** Variable that tracks if decode has written to the time buffer this
3462292SN/A     * cycle. Used to tell CPU if there is activity this cycle.
3472292SN/A     */
3482292SN/A    bool wroteToTimeBuffer;
3492292SN/A
3502292SN/A    /** Structures whose free entries impact the amount of instructions that
3512292SN/A     * can be renamed.
3522292SN/A     */
3532292SN/A    struct FreeEntries {
3542292SN/A        unsigned iqEntries;
3552292SN/A        unsigned lsqEntries;
3562292SN/A        unsigned robEntries;
3572292SN/A    };
3582292SN/A
3592292SN/A    /** Per-thread tracking of the number of free entries of back-end
3602292SN/A     * structures.
3612292SN/A     */
3622292SN/A    FreeEntries freeEntries[Impl::MaxThreads];
3632292SN/A
3642292SN/A    /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
3652292SN/A     * partitioned between threads, so the ROB must tell rename when it is
3662292SN/A     * empty.
3672292SN/A     */
3682292SN/A    bool emptyROB[Impl::MaxThreads];
3692292SN/A
3702292SN/A    /** Source of possible stalls. */
3712292SN/A    struct Stalls {
3722292SN/A        bool iew;
3732292SN/A        bool commit;
3742292SN/A    };
3752292SN/A
3762292SN/A    /** Tracks which stages are telling decode to stall. */
3772292SN/A    Stalls stalls[Impl::MaxThreads];
3782292SN/A
3792301SN/A    /** The serialize instruction that rename has stalled on. */
3802301SN/A    DynInstPtr serializeInst[Impl::MaxThreads];
3812292SN/A
3822292SN/A    /** Records if rename needs to serialize on the next instruction for any
3832292SN/A     * thread.
3842292SN/A     */
3852292SN/A    bool serializeOnNextInst[Impl::MaxThreads];
3862292SN/A
3871060SN/A    /** Delay between iew and rename, in ticks. */
3881060SN/A    int iewToRenameDelay;
3891060SN/A
3901060SN/A    /** Delay between decode and rename, in ticks. */
3911060SN/A    int decodeToRenameDelay;
3921060SN/A
3931060SN/A    /** Delay between commit and rename, in ticks. */
3941060SN/A    unsigned commitToRenameDelay;
3951060SN/A
3961060SN/A    /** Rename width, in instructions. */
3971060SN/A    unsigned renameWidth;
3981060SN/A
3991060SN/A    /** Commit width, in instructions.  Used so rename knows how many
4001060SN/A     *  instructions might have freed registers in the previous cycle.
4011060SN/A     */
4021060SN/A    unsigned commitWidth;
4031061SN/A
4042292SN/A    /** The index of the instruction in the time buffer to IEW that rename is
4052292SN/A     * currently using.
4061061SN/A     */
4072292SN/A    unsigned toIEWIndex;
4081062SN/A
4092292SN/A    /** Whether or not rename needs to block this cycle. */
4102292SN/A    bool blockThisCycle;
4112292SN/A
4123788Sgblack@eecs.umich.edu    /** Whether or not rename needs to resume a serialize instruction
4133788Sgblack@eecs.umich.edu     * after squashing. */
4143788Sgblack@eecs.umich.edu    bool resumeSerialize;
4153788Sgblack@eecs.umich.edu
4163798Sgblack@eecs.umich.edu    /** Whether or not rename needs to resume clearing out the skidbuffer
4173798Sgblack@eecs.umich.edu     * after squashing. */
4183798Sgblack@eecs.umich.edu    bool resumeUnblocking;
4193798Sgblack@eecs.umich.edu
4202292SN/A    /** The number of threads active in rename. */
4212292SN/A    unsigned numThreads;
4222292SN/A
4232292SN/A    /** The maximum skid buffer size. */
4242292SN/A    unsigned skidBufferMax;
4252292SN/A
4262361SN/A    PhysRegIndex maxPhysicalRegs;
4272361SN/A
4282292SN/A    /** Enum to record the source of a structure full stall.  Can come from
4292292SN/A     * either ROB, IQ, LSQ, and it is priortized in that order.
4302292SN/A     */
4312292SN/A    enum FullSource {
4322292SN/A        ROB,
4332292SN/A        IQ,
4342292SN/A        LSQ,
4352292SN/A        NONE
4362292SN/A    };
4372292SN/A
4382292SN/A    /** Function used to increment the stat that corresponds to the source of
4392292SN/A     * the stall.
4402292SN/A     */
4412292SN/A    inline void incrFullStat(const FullSource &source);
4422292SN/A
4432292SN/A    /** Stat for total number of cycles spent squashing. */
4445999Snate@binkert.org    Stats::Scalar renameSquashCycles;
4452292SN/A    /** Stat for total number of cycles spent idle. */
4465999Snate@binkert.org    Stats::Scalar renameIdleCycles;
4472292SN/A    /** Stat for total number of cycles spent blocking. */
4485999Snate@binkert.org    Stats::Scalar renameBlockCycles;
4492301SN/A    /** Stat for total number of cycles spent stalling for a serializing inst. */
4505999Snate@binkert.org    Stats::Scalar renameSerializeStallCycles;
4512292SN/A    /** Stat for total number of cycles spent running normally. */
4525999Snate@binkert.org    Stats::Scalar renameRunCycles;
4532292SN/A    /** Stat for total number of cycles spent unblocking. */
4545999Snate@binkert.org    Stats::Scalar renameUnblockCycles;
4552292SN/A    /** Stat for total number of renamed instructions. */
4565999Snate@binkert.org    Stats::Scalar renameRenamedInsts;
4572292SN/A    /** Stat for total number of squashed instructions that rename discards. */
4585999Snate@binkert.org    Stats::Scalar renameSquashedInsts;
4592292SN/A    /** Stat for total number of times that the ROB starts a stall in rename. */
4605999Snate@binkert.org    Stats::Scalar renameROBFullEvents;
4612292SN/A    /** Stat for total number of times that the IQ starts a stall in rename. */
4625999Snate@binkert.org    Stats::Scalar renameIQFullEvents;
4632292SN/A    /** Stat for total number of times that the LSQ starts a stall in rename. */
4645999Snate@binkert.org    Stats::Scalar renameLSQFullEvents;
4652292SN/A    /** Stat for total number of times that rename runs out of free registers
4662292SN/A     * to use to rename. */
4675999Snate@binkert.org    Stats::Scalar renameFullRegistersEvents;
4682292SN/A    /** Stat for total number of renamed destination registers. */
4695999Snate@binkert.org    Stats::Scalar renameRenamedOperands;
4702292SN/A    /** Stat for total number of source register rename lookups. */
4715999Snate@binkert.org    Stats::Scalar renameRenameLookups;
4722292SN/A    /** Stat for total number of committed renaming mappings. */
4735999Snate@binkert.org    Stats::Scalar renameCommittedMaps;
4742292SN/A    /** Stat for total number of mappings that were undone due to a squash. */
4755999Snate@binkert.org    Stats::Scalar renameUndoneMaps;
4762348SN/A    /** Number of serialize instructions handled. */
4775999Snate@binkert.org    Stats::Scalar renamedSerializing;
4782348SN/A    /** Number of instructions marked as temporarily serializing. */
4795999Snate@binkert.org    Stats::Scalar renamedTempSerializing;
4802348SN/A    /** Number of instructions inserted into skid buffers. */
4815999Snate@binkert.org    Stats::Scalar renameSkidInsts;
4821060SN/A};
4831060SN/A
4842292SN/A#endif // __CPU_O3_RENAME_HH__
485