rename.hh revision 2665
11689SN/A/* 21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// Todo: 321061SN/A// Fix up trap and barrier handling. 331061SN/A// May want to have different statuses to differentiate the different stall 341061SN/A// conditions. 351060SN/A 361755SN/A#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__ 371755SN/A#define __CPU_O3_CPU_SIMPLE_RENAME_HH__ 381060SN/A 391060SN/A#include <list> 401060SN/A 411461SN/A#include "base/statistics.hh" 421060SN/A#include "base/timebuf.hh" 431060SN/A 441060SN/A// Will need rename maps for both the int reg file and fp reg file. 451060SN/A// Or change rename map class to handle both. (RegFile handles both.) 461060SN/Atemplate<class Impl> 471060SN/Aclass SimpleRename 481060SN/A{ 491060SN/A public: 501060SN/A // Typedefs from the Impl. 511060SN/A typedef typename Impl::CPUPol CPUPol; 521061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 531060SN/A typedef typename Impl::FullCPU FullCPU; 541060SN/A typedef typename Impl::Params Params; 551060SN/A 561061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 571061SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 581061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 591061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 601060SN/A 611060SN/A // Typedefs from the CPUPol 621060SN/A typedef typename CPUPol::FreeList FreeList; 631060SN/A typedef typename CPUPol::RenameMap RenameMap; 641060SN/A 651060SN/A // Typedefs from the ISA. 662107SN/A typedef TheISA::RegIndex RegIndex; 671060SN/A 681060SN/A public: 691060SN/A // Rename will block if ROB becomes full or issue queue becomes full, 701060SN/A // or there are no free registers to rename to. 711060SN/A // Only case where rename squashes is if IEW squashes. 721060SN/A enum Status { 731060SN/A Running, 741060SN/A Idle, 751060SN/A Squashing, 761060SN/A Blocked, 771060SN/A Unblocking, 781060SN/A BarrierStall 791060SN/A }; 801060SN/A 811060SN/A private: 821060SN/A Status _status; 831060SN/A 841060SN/A public: 851060SN/A SimpleRename(Params ¶ms); 861060SN/A 871062SN/A void regStats(); 881062SN/A 891060SN/A void setCPU(FullCPU *cpu_ptr); 901060SN/A 911060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 921060SN/A 931060SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 941060SN/A 951060SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 961060SN/A 971060SN/A void setRenameMap(RenameMap *rm_ptr); 981060SN/A 991060SN/A void setFreeList(FreeList *fl_ptr); 1001060SN/A 1011060SN/A void dumpHistory(); 1021060SN/A 1031060SN/A void tick(); 1041060SN/A 1051060SN/A void rename(); 1061060SN/A 1071060SN/A void squash(); 1081060SN/A 1091060SN/A private: 1101060SN/A void block(); 1111060SN/A 1121060SN/A inline void unblock(); 1131060SN/A 1141060SN/A void doSquash(); 1151060SN/A 1161060SN/A void removeFromHistory(InstSeqNum inst_seq_num); 1171060SN/A 1181061SN/A inline void renameSrcRegs(DynInstPtr &inst); 1191061SN/A 1201061SN/A inline void renameDestRegs(DynInstPtr &inst); 1211061SN/A 1221061SN/A inline int calcFreeROBEntries(); 1231061SN/A 1241061SN/A inline int calcFreeIQEntries(); 1251061SN/A 1261060SN/A /** Holds the previous information for each rename. 1271060SN/A * Note that often times the inst may have been deleted, so only access 1281060SN/A * the pointer for the address and do not dereference it. 1291060SN/A */ 1301060SN/A struct RenameHistory { 1311060SN/A RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1321060SN/A PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1331060SN/A : instSeqNum(_instSeqNum), archReg(_archReg), 1341060SN/A newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1351060SN/A placeHolder(false) 1361060SN/A { 1371060SN/A } 1381060SN/A 1391060SN/A /** Constructor used specifically for cases where a place holder 1401060SN/A * rename history entry is being made. 1411060SN/A */ 1421060SN/A RenameHistory(InstSeqNum _instSeqNum) 1431060SN/A : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1441060SN/A prevPhysReg(0), placeHolder(true) 1451060SN/A { 1461060SN/A } 1471060SN/A 1481060SN/A InstSeqNum instSeqNum; 1491060SN/A RegIndex archReg; 1501060SN/A PhysRegIndex newPhysReg; 1511060SN/A PhysRegIndex prevPhysReg; 1521060SN/A bool placeHolder; 1531060SN/A }; 1541060SN/A 1551061SN/A std::list<RenameHistory> historyBuffer; 1561060SN/A 1571060SN/A /** CPU interface. */ 1581060SN/A FullCPU *cpu; 1591060SN/A 1601060SN/A // Interfaces to objects outside of rename. 1611060SN/A /** Time buffer interface. */ 1621060SN/A TimeBuffer<TimeStruct> *timeBuffer; 1631060SN/A 1641060SN/A /** Wire to get IEW's output from backwards time buffer. */ 1651060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 1661060SN/A 1671060SN/A /** Wire to get commit's output from backwards time buffer. */ 1681060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1691060SN/A 1701060SN/A /** Wire to write infromation heading to previous stages. */ 1711060SN/A // Might not be the best name as not only decode will read it. 1721060SN/A typename TimeBuffer<TimeStruct>::wire toDecode; 1731060SN/A 1741060SN/A /** Rename instruction queue. */ 1751060SN/A TimeBuffer<RenameStruct> *renameQueue; 1761060SN/A 1771060SN/A /** Wire to write any information heading to IEW. */ 1781060SN/A typename TimeBuffer<RenameStruct>::wire toIEW; 1791060SN/A 1801060SN/A /** Decode instruction queue interface. */ 1811060SN/A TimeBuffer<DecodeStruct> *decodeQueue; 1821060SN/A 1831060SN/A /** Wire to get decode's output from decode queue. */ 1841060SN/A typename TimeBuffer<DecodeStruct>::wire fromDecode; 1851060SN/A 1861060SN/A /** Skid buffer between rename and decode. */ 1871061SN/A std::queue<DecodeStruct> skidBuffer; 1881060SN/A 1891060SN/A /** Rename map interface. */ 1901060SN/A SimpleRenameMap *renameMap; 1911060SN/A 1921060SN/A /** Free list interface. */ 1931060SN/A FreeList *freeList; 1941060SN/A 1951060SN/A /** Delay between iew and rename, in ticks. */ 1961060SN/A int iewToRenameDelay; 1971060SN/A 1981060SN/A /** Delay between decode and rename, in ticks. */ 1991060SN/A int decodeToRenameDelay; 2001060SN/A 2011060SN/A /** Delay between commit and rename, in ticks. */ 2021060SN/A unsigned commitToRenameDelay; 2031060SN/A 2041060SN/A /** Rename width, in instructions. */ 2051060SN/A unsigned renameWidth; 2061060SN/A 2071060SN/A /** Commit width, in instructions. Used so rename knows how many 2081060SN/A * instructions might have freed registers in the previous cycle. 2091060SN/A */ 2101060SN/A unsigned commitWidth; 2111061SN/A 2121061SN/A /** The instruction that rename is currently on. It needs to have 2131061SN/A * persistent state so that when a stall occurs in the middle of a 2141061SN/A * group of instructions, it can restart at the proper instruction. 2151061SN/A */ 2161061SN/A unsigned numInst; 2171062SN/A 2181062SN/A Stats::Scalar<> renameSquashCycles; 2191062SN/A Stats::Scalar<> renameIdleCycles; 2201062SN/A Stats::Scalar<> renameBlockCycles; 2211062SN/A Stats::Scalar<> renameUnblockCycles; 2221062SN/A Stats::Scalar<> renameRenamedInsts; 2231062SN/A Stats::Scalar<> renameSquashedInsts; 2241062SN/A Stats::Scalar<> renameROBFullEvents; 2251062SN/A Stats::Scalar<> renameIQFullEvents; 2261062SN/A Stats::Scalar<> renameFullRegistersEvents; 2271062SN/A Stats::Scalar<> renameRenamedOperands; 2281062SN/A Stats::Scalar<> renameRenameLookups; 2291062SN/A Stats::Scalar<> renameHBPlaceHolders; 2301062SN/A Stats::Scalar<> renameCommittedMaps; 2311062SN/A Stats::Scalar<> renameUndoneMaps; 2321062SN/A Stats::Scalar<> renameValidUndoneMaps; 2331060SN/A}; 2341060SN/A 2351755SN/A#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__ 236