rename.hh revision 2316 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_O3_RENAME_HH__
30#define __CPU_O3_RENAME_HH__
31
32#include <list>
33
34#include "base/statistics.hh"
35#include "base/timebuf.hh"
36
37/**
38 * DefaultRename handles both single threaded and SMT rename. Its width is
39 * specified by the parameters; each cycle it tries to rename that many
40 * instructions. It holds onto the rename history of all instructions with
41 * destination registers, storing the arch. register, the new physical
42 * register, and the old physical register, to allow for undoing of mappings
43 * if squashing happens, or freeing up registers upon commit. Rename handles
44 * blocking if the ROB, IQ, or LSQ is going to be full. Rename also handles
45 * barriers, and does so by stalling on the instruction until the ROB is
46 * empty and there are no instructions in flight to the ROB.
47 */
48template<class Impl>
49class DefaultRename
50{
51  public:
52    // Typedefs from the Impl.
53    typedef typename Impl::CPUPol CPUPol;
54    typedef typename Impl::DynInstPtr DynInstPtr;
55    typedef typename Impl::FullCPU FullCPU;
56    typedef typename Impl::Params Params;
57
58    // Typedefs from the CPUPol
59    typedef typename CPUPol::DecodeStruct DecodeStruct;
60    typedef typename CPUPol::RenameStruct RenameStruct;
61    typedef typename CPUPol::TimeStruct TimeStruct;
62    typedef typename CPUPol::FreeList FreeList;
63    typedef typename CPUPol::RenameMap RenameMap;
64    // These are used only for initialization.
65    typedef typename CPUPol::IEW IEW;
66    typedef typename CPUPol::Commit Commit;
67
68    // Typedefs from the ISA.
69    typedef TheISA::RegIndex RegIndex;
70
71    // A deque is used to queue the instructions.  Barrier insts must be
72    // added to the front of the deque, which is the only reason for using
73    // a deque instead of a queue. (Most other stages use a queue)
74    typedef std::list<DynInstPtr> InstQueue;
75
76  public:
77    /** Overall rename status. Used to determine if the CPU can deschedule
78     * itself due to a lack of activity.
79     */
80    enum RenameStatus {
81        Active,
82        Inactive
83    };
84
85    /** Individual thread status. */
86    enum ThreadStatus {
87        Running,
88        Idle,
89        StartSquash,
90        Squashing,
91        Blocked,
92        Unblocking,
93        SerializeStall
94    };
95
96  private:
97    /** Rename status. */
98    RenameStatus _status;
99
100    /** Per-thread status. */
101    ThreadStatus renameStatus[Impl::MaxThreads];
102
103  public:
104    /** DefaultRename constructor. */
105    DefaultRename(Params *params);
106
107    /** Returns the name of rename. */
108    std::string name() const;
109
110    /** Registers statistics. */
111    void regStats();
112
113    /** Sets CPU pointer. */
114    void setCPU(FullCPU *cpu_ptr);
115
116    /** Sets the main backwards communication time buffer pointer. */
117    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
118
119    /** Sets pointer to time buffer used to communicate to the next stage. */
120    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
121
122    /** Sets pointer to time buffer coming from decode. */
123    void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
124
125    /** Sets pointer to IEW stage. Used only for initialization. */
126    void setIEWStage(IEW *iew_stage)
127    { iew_ptr = iew_stage; }
128
129    /** Sets pointer to commit stage. Used only for initialization. */
130    void setCommitStage(Commit *commit_stage)
131    { commit_ptr = commit_stage; }
132
133  private:
134    /** Pointer to IEW stage. Used only for initialization. */
135    IEW *iew_ptr;
136
137    /** Pointer to commit stage. Used only for initialization. */
138    Commit *commit_ptr;
139
140  public:
141    /** Initializes variables for the stage. */
142    void initStage();
143
144    /** Sets pointer to list of active threads. */
145    void setActiveThreads(std::list<unsigned> *at_ptr);
146
147    /** Sets pointer to rename maps (per-thread structures). */
148    void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
149
150    /** Sets pointer to the free list. */
151    void setFreeList(FreeList *fl_ptr);
152
153    /** Sets pointer to the scoreboard. */
154    void setScoreboard(Scoreboard *_scoreboard);
155
156    void switchOut();
157
158    void doSwitchOut();
159
160    void takeOverFrom();
161
162    /** Squashes all instructions in a thread. */
163    void squash(unsigned tid);
164
165    /** Ticks rename, which processes all input signals and attempts to rename
166     * as many instructions as possible.
167     */
168    void tick();
169
170    /** Debugging function used to dump history buffer of renamings. */
171    void dumpHistory();
172
173  private:
174    /** Determines what to do based on rename's current status.
175     * @param status_change rename() sets this variable if there was a status
176     * change (ie switching from blocking to unblocking).
177     * @param tid Thread id to rename instructions from.
178     */
179    void rename(bool &status_change, unsigned tid);
180
181    /** Renames instructions for the given thread. Also handles serializing
182     * instructions.
183     */
184    void renameInsts(unsigned tid);
185
186    /** Inserts unused instructions from a given thread into the skid buffer,
187     * to be renamed once rename unblocks.
188     */
189    void skidInsert(unsigned tid);
190
191    /** Separates instructions from decode into individual lists of instructions
192     * sorted by thread.
193     */
194    void sortInsts();
195
196    /** Returns if all of the skid buffers are empty. */
197    bool skidsEmpty();
198
199    /** Updates overall rename status based on all of the threads' statuses. */
200    void updateStatus();
201
202    /** Switches rename to blocking, and signals back that rename has become
203     * blocked.
204     * @return Returns true if there is a status change.
205     */
206    bool block(unsigned tid);
207
208    /** Switches rename to unblocking if the skid buffer is empty, and signals
209     * back that rename has unblocked.
210     * @return Returns true if there is a status change.
211     */
212    bool unblock(unsigned tid);
213
214    /** Executes actual squash, removing squashed instructions. */
215    void doSquash(unsigned tid);
216
217    /** Removes a committed instruction's rename history. */
218    void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
219
220    /** Renames the source registers of an instruction. */
221    inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
222
223    /** Renames the destination registers of an instruction. */
224    inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
225
226    /** Calculates the number of free ROB entries for a specific thread. */
227    inline int calcFreeROBEntries(unsigned tid);
228
229    /** Calculates the number of free IQ entries for a specific thread. */
230    inline int calcFreeIQEntries(unsigned tid);
231
232    /** Calculates the number of free LSQ entries for a specific thread. */
233    inline int calcFreeLSQEntries(unsigned tid);
234
235    /** Returns the number of valid instructions coming from decode. */
236    unsigned validInsts();
237
238    /** Reads signals telling rename to block/unblock. */
239    void readStallSignals(unsigned tid);
240
241    /** Checks if any stages are telling rename to block. */
242    bool checkStall(unsigned tid);
243
244    void readFreeEntries(unsigned tid);
245
246    bool checkSignalsAndUpdate(unsigned tid);
247
248    /** Either serializes on the next instruction available in the InstQueue,
249     * or records that it must serialize on the next instruction to enter
250     * rename.
251     * @param inst_list The list of younger, unprocessed instructions for the
252     * thread that has the serializeAfter instruction.
253     * @param tid The thread id.
254     */
255    void serializeAfter(InstQueue &inst_list, unsigned tid);
256
257    /** Holds the information for each destination register rename. It holds
258     * the instruction's sequence number, the arch register, the old physical
259     * register for that arch. register, and the new physical register.
260     */
261    struct RenameHistory {
262        RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
263                      PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
264            : instSeqNum(_instSeqNum), archReg(_archReg),
265              newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg)
266        {
267        }
268
269        /** The sequence number of the instruction that renamed. */
270        InstSeqNum instSeqNum;
271        /** The architectural register index that was renamed. */
272        RegIndex archReg;
273        /** The new physical register that the arch. register is renamed to. */
274        PhysRegIndex newPhysReg;
275        /** The old physical register that the arch. register was renamed to. */
276        PhysRegIndex prevPhysReg;
277    };
278
279    /** A per-thread list of all destination register renames, used to either
280     * undo rename mappings or free old physical registers.
281     */
282    std::list<RenameHistory> historyBuffer[Impl::MaxThreads];
283
284    /** Pointer to CPU. */
285    FullCPU *cpu;
286
287    /** Pointer to main time buffer used for backwards communication. */
288    TimeBuffer<TimeStruct> *timeBuffer;
289
290    /** Wire to get IEW's output from backwards time buffer. */
291    typename TimeBuffer<TimeStruct>::wire fromIEW;
292
293    /** Wire to get commit's output from backwards time buffer. */
294    typename TimeBuffer<TimeStruct>::wire fromCommit;
295
296    /** Wire to write infromation heading to previous stages. */
297    typename TimeBuffer<TimeStruct>::wire toDecode;
298
299    /** Rename instruction queue. */
300    TimeBuffer<RenameStruct> *renameQueue;
301
302    /** Wire to write any information heading to IEW. */
303    typename TimeBuffer<RenameStruct>::wire toIEW;
304
305    /** Decode instruction queue interface. */
306    TimeBuffer<DecodeStruct> *decodeQueue;
307
308    /** Wire to get decode's output from decode queue. */
309    typename TimeBuffer<DecodeStruct>::wire fromDecode;
310
311    /** Queue of all instructions coming from decode this cycle. */
312    InstQueue insts[Impl::MaxThreads];
313
314    /** Skid buffer between rename and decode. */
315    InstQueue skidBuffer[Impl::MaxThreads];
316
317    /** Rename map interface. */
318    RenameMap *renameMap[Impl::MaxThreads];
319
320    /** Free list interface. */
321    FreeList *freeList;
322
323    /** Pointer to the list of active threads. */
324    std::list<unsigned> *activeThreads;
325
326    /** Pointer to the scoreboard. */
327    Scoreboard *scoreboard;
328
329    /** Count of instructions in progress that have been sent off to the IQ
330     * and ROB, but are not yet included in their occupancy counts.
331     */
332    int instsInProgress[Impl::MaxThreads];
333
334    /** Variable that tracks if decode has written to the time buffer this
335     * cycle. Used to tell CPU if there is activity this cycle.
336     */
337    bool wroteToTimeBuffer;
338
339    /** Structures whose free entries impact the amount of instructions that
340     * can be renamed.
341     */
342    struct FreeEntries {
343        unsigned iqEntries;
344        unsigned lsqEntries;
345        unsigned robEntries;
346    };
347
348    /** Per-thread tracking of the number of free entries of back-end
349     * structures.
350     */
351    FreeEntries freeEntries[Impl::MaxThreads];
352
353    /** Records if the ROB is empty. In SMT mode the ROB may be dynamically
354     * partitioned between threads, so the ROB must tell rename when it is
355     * empty.
356     */
357    bool emptyROB[Impl::MaxThreads];
358
359    /** Source of possible stalls. */
360    struct Stalls {
361        bool iew;
362        bool commit;
363    };
364
365    /** Tracks which stages are telling decode to stall. */
366    Stalls stalls[Impl::MaxThreads];
367
368    /** The serialize instruction that rename has stalled on. */
369    DynInstPtr serializeInst[Impl::MaxThreads];
370
371    /** Records if rename needs to serialize on the next instruction for any
372     * thread.
373     */
374    bool serializeOnNextInst[Impl::MaxThreads];
375
376    /** Delay between iew and rename, in ticks. */
377    int iewToRenameDelay;
378
379    /** Delay between decode and rename, in ticks. */
380    int decodeToRenameDelay;
381
382    /** Delay between commit and rename, in ticks. */
383    unsigned commitToRenameDelay;
384
385    /** Rename width, in instructions. */
386    unsigned renameWidth;
387
388    /** Commit width, in instructions.  Used so rename knows how many
389     *  instructions might have freed registers in the previous cycle.
390     */
391    unsigned commitWidth;
392
393    /** The index of the instruction in the time buffer to IEW that rename is
394     * currently using.
395     */
396    unsigned toIEWIndex;
397
398    /** Whether or not rename needs to block this cycle. */
399    bool blockThisCycle;
400
401    /** The number of threads active in rename. */
402    unsigned numThreads;
403
404    /** The maximum skid buffer size. */
405    unsigned skidBufferMax;
406
407    /** Enum to record the source of a structure full stall.  Can come from
408     * either ROB, IQ, LSQ, and it is priortized in that order.
409     */
410    enum FullSource {
411        ROB,
412        IQ,
413        LSQ,
414        NONE
415    };
416
417    /** Function used to increment the stat that corresponds to the source of
418     * the stall.
419     */
420    inline void incrFullStat(const FullSource &source);
421
422    /** Stat for total number of cycles spent squashing. */
423    Stats::Scalar<> renameSquashCycles;
424    /** Stat for total number of cycles spent idle. */
425    Stats::Scalar<> renameIdleCycles;
426    /** Stat for total number of cycles spent blocking. */
427    Stats::Scalar<> renameBlockCycles;
428    /** Stat for total number of cycles spent stalling for a serializing inst. */
429    Stats::Scalar<> renameSerializeStallCycles;
430    /** Stat for total number of cycles spent running normally. */
431    Stats::Scalar<> renameRunCycles;
432    /** Stat for total number of cycles spent unblocking. */
433    Stats::Scalar<> renameUnblockCycles;
434    /** Stat for total number of renamed instructions. */
435    Stats::Scalar<> renameRenamedInsts;
436    /** Stat for total number of squashed instructions that rename discards. */
437    Stats::Scalar<> renameSquashedInsts;
438    /** Stat for total number of times that the ROB starts a stall in rename. */
439    Stats::Scalar<> renameROBFullEvents;
440    /** Stat for total number of times that the IQ starts a stall in rename. */
441    Stats::Scalar<> renameIQFullEvents;
442    /** Stat for total number of times that the LSQ starts a stall in rename. */
443    Stats::Scalar<> renameLSQFullEvents;
444    /** Stat for total number of times that rename runs out of free registers
445     * to use to rename. */
446    Stats::Scalar<> renameFullRegistersEvents;
447    /** Stat for total number of renamed destination registers. */
448    Stats::Scalar<> renameRenamedOperands;
449    /** Stat for total number of source register rename lookups. */
450    Stats::Scalar<> renameRenameLookups;
451    /** Stat for total number of committed renaming mappings. */
452    Stats::Scalar<> renameCommittedMaps;
453    /** Stat for total number of mappings that were undone due to a squash. */
454    Stats::Scalar<> renameUndoneMaps;
455    Stats::Scalar<> renamedSerializing;
456    Stats::Scalar<> renamedTempSerializing;
457    Stats::Scalar<> renameSkidInsts;
458};
459
460#endif // __CPU_O3_RENAME_HH__
461