rename.hh revision 2307
12914Ssaidi@eecs.umich.edu/* 28856Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152914Ssaidi@eecs.umich.edu * 162914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914Ssaidi@eecs.umich.edu */ 282914Ssaidi@eecs.umich.edu 292914Ssaidi@eecs.umich.edu#ifndef __CPU_O3_RENAME_HH__ 302914Ssaidi@eecs.umich.edu#define __CPU_O3_RENAME_HH__ 312914Ssaidi@eecs.umich.edu 322914Ssaidi@eecs.umich.edu#include <list> 332914Ssaidi@eecs.umich.edu 342914Ssaidi@eecs.umich.edu#include "base/statistics.hh" 352914Ssaidi@eecs.umich.edu#include "base/timebuf.hh" 362914Ssaidi@eecs.umich.edu 372914Ssaidi@eecs.umich.edu/** 382914Ssaidi@eecs.umich.edu * DefaultRename handles both single threaded and SMT rename. Its width is 392914Ssaidi@eecs.umich.edu * specified by the parameters; each cycle it tries to rename that many 402914Ssaidi@eecs.umich.edu * instructions. It holds onto the rename history of all instructions with 418856Sandreas.hansson@arm.com * destination registers, storing the arch. register, the new physical 422914Ssaidi@eecs.umich.edu * register, and the old physical register, to allow for undoing of mappings 432914Ssaidi@eecs.umich.edu * if squashing happens, or freeing up registers upon commit. Rename handles 443091Sstever@eecs.umich.edu * blocking if the ROB, IQ, or LSQ is going to be full. Rename also handles 453091Sstever@eecs.umich.edu * barriers, and does so by stalling on the instruction until the ROB is 463091Sstever@eecs.umich.edu * empty and there are no instructions in flight to the ROB. 472914Ssaidi@eecs.umich.edu */ 482914Ssaidi@eecs.umich.edutemplate<class Impl> 493091Sstever@eecs.umich.educlass DefaultRename 503091Sstever@eecs.umich.edu{ 512914Ssaidi@eecs.umich.edu public: 522914Ssaidi@eecs.umich.edu // Typedefs from the Impl. 538914Sandreas.hansson@arm.com typedef typename Impl::CPUPol CPUPol; 542914Ssaidi@eecs.umich.edu typedef typename Impl::DynInstPtr DynInstPtr; 5513892Sgabeblack@google.com typedef typename Impl::FullCPU FullCPU; 5613892Sgabeblack@google.com typedef typename Impl::Params Params; 573091Sstever@eecs.umich.edu 588914Sandreas.hansson@arm.com // Typedefs from the CPUPol 598975Sandreas.hansson@arm.com typedef typename CPUPol::DecodeStruct DecodeStruct; 608914Sandreas.hansson@arm.com typedef typename CPUPol::RenameStruct RenameStruct; 613091Sstever@eecs.umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 628922Swilliam.wang@arm.com typedef typename CPUPol::FreeList FreeList; 632914Ssaidi@eecs.umich.edu typedef typename CPUPol::RenameMap RenameMap; 648914Sandreas.hansson@arm.com // These are used only for initialization. 659097Sandreas.hansson@arm.com typedef typename CPUPol::IEW IEW; 669097Sandreas.hansson@arm.com typedef typename CPUPol::Commit Commit; 679097Sandreas.hansson@arm.com 689097Sandreas.hansson@arm.com // Typedefs from the ISA. 699097Sandreas.hansson@arm.com typedef TheISA::RegIndex RegIndex; 709097Sandreas.hansson@arm.com 719097Sandreas.hansson@arm.com // A deque is used to queue the instructions. Barrier insts must be 729097Sandreas.hansson@arm.com // added to the front of the deque, which is the only reason for using 7310713Sandreas.hansson@arm.com // a deque instead of a queue. (Most other stages use a queue) 749097Sandreas.hansson@arm.com typedef std::list<DynInstPtr> InstQueue; 752914Ssaidi@eecs.umich.edu 764490Sstever@eecs.umich.edu public: 773091Sstever@eecs.umich.edu /** Overall rename status. Used to determine if the CPU can deschedule 783349Sbinkertn@umich.edu * itself due to a lack of activity. 793091Sstever@eecs.umich.edu */ 803091Sstever@eecs.umich.edu enum RenameStatus { 818975Sandreas.hansson@arm.com Active, 823091Sstever@eecs.umich.edu Inactive 838914Sandreas.hansson@arm.com }; 843091Sstever@eecs.umich.edu 859063SAli.Saidi@ARM.com /** Individual thread status. */ 8611190Sandreas.hansson@arm.com enum ThreadStatus { 8711190Sandreas.hansson@arm.com Running, 889063SAli.Saidi@ARM.com Idle, 8911190Sandreas.hansson@arm.com StartSquash, 909063SAli.Saidi@ARM.com Squashing, 912914Ssaidi@eecs.umich.edu Blocked, 924490Sstever@eecs.umich.edu Unblocking, 938914Sandreas.hansson@arm.com SerializeStall 948914Sandreas.hansson@arm.com }; 958975Sandreas.hansson@arm.com 968914Sandreas.hansson@arm.com private: 978914Sandreas.hansson@arm.com /** Rename status. */ 988914Sandreas.hansson@arm.com RenameStatus _status; 998914Sandreas.hansson@arm.com 1008914Sandreas.hansson@arm.com /** Per-thread status. */ 1018914Sandreas.hansson@arm.com ThreadStatus renameStatus[Impl::MaxThreads]; 1028914Sandreas.hansson@arm.com 1038914Sandreas.hansson@arm.com public: 10413892Sgabeblack@google.com /** DefaultRename constructor. */ 1058856Sandreas.hansson@arm.com DefaultRename(Params *params); 1068914Sandreas.hansson@arm.com 1078914Sandreas.hansson@arm.com /** Returns the name of rename. */ 1082914Ssaidi@eecs.umich.edu std::string name() const; 1092914Ssaidi@eecs.umich.edu 1102914Ssaidi@eecs.umich.edu /** Registers statistics. */ 111 void regStats(); 112 113 /** Sets CPU pointer. */ 114 void setCPU(FullCPU *cpu_ptr); 115 116 /** Sets the main backwards communication time buffer pointer. */ 117 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 118 119 /** Sets pointer to time buffer used to communicate to the next stage. */ 120 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 121 122 /** Sets pointer to time buffer coming from decode. */ 123 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 124 125 /** Sets pointer to IEW stage. Used only for initialization. */ 126 void setIEWStage(IEW *iew_stage) 127 { iew_ptr = iew_stage; } 128 129 /** Sets pointer to commit stage. Used only for initialization. */ 130 void setCommitStage(Commit *commit_stage) 131 { commit_ptr = commit_stage; } 132 133 private: 134 /** Pointer to IEW stage. Used only for initialization. */ 135 IEW *iew_ptr; 136 137 /** Pointer to commit stage. Used only for initialization. */ 138 Commit *commit_ptr; 139 140 public: 141 /** Initializes variables for the stage. */ 142 void initStage(); 143 144 /** Sets pointer to list of active threads. */ 145 void setActiveThreads(std::list<unsigned> *at_ptr); 146 147 /** Sets pointer to rename maps (per-thread structures). */ 148 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 149 150 /** Sets pointer to the free list. */ 151 void setFreeList(FreeList *fl_ptr); 152 153 /** Sets pointer to the scoreboard. */ 154 void setScoreboard(Scoreboard *_scoreboard); 155 156 void switchOut(); 157 158 void takeOverFrom(); 159 160 /** Squashes all instructions in a thread. */ 161 void squash(unsigned tid); 162 163 /** Ticks rename, which processes all input signals and attempts to rename 164 * as many instructions as possible. 165 */ 166 void tick(); 167 168 /** Debugging function used to dump history buffer of renamings. */ 169 void dumpHistory(); 170 171 private: 172 /** Determines what to do based on rename's current status. 173 * @param status_change rename() sets this variable if there was a status 174 * change (ie switching from blocking to unblocking). 175 * @param tid Thread id to rename instructions from. 176 */ 177 void rename(bool &status_change, unsigned tid); 178 179 /** Renames instructions for the given thread. Also handles serializing 180 * instructions. 181 */ 182 void renameInsts(unsigned tid); 183 184 /** Inserts unused instructions from a given thread into the skid buffer, 185 * to be renamed once rename unblocks. 186 */ 187 void skidInsert(unsigned tid); 188 189 /** Separates instructions from decode into individual lists of instructions 190 * sorted by thread. 191 */ 192 void sortInsts(); 193 194 /** Returns if all of the skid buffers are empty. */ 195 bool skidsEmpty(); 196 197 /** Updates overall rename status based on all of the threads' statuses. */ 198 void updateStatus(); 199 200 /** Switches rename to blocking, and signals back that rename has become 201 * blocked. 202 * @return Returns true if there is a status change. 203 */ 204 bool block(unsigned tid); 205 206 /** Switches rename to unblocking if the skid buffer is empty, and signals 207 * back that rename has unblocked. 208 * @return Returns true if there is a status change. 209 */ 210 bool unblock(unsigned tid); 211 212 /** Executes actual squash, removing squashed instructions. */ 213 void doSquash(unsigned tid); 214 215 /** Removes a committed instruction's rename history. */ 216 void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid); 217 218 /** Renames the source registers of an instruction. */ 219 inline void renameSrcRegs(DynInstPtr &inst, unsigned tid); 220 221 /** Renames the destination registers of an instruction. */ 222 inline void renameDestRegs(DynInstPtr &inst, unsigned tid); 223 224 /** Calculates the number of free ROB entries for a specific thread. */ 225 inline int calcFreeROBEntries(unsigned tid); 226 227 /** Calculates the number of free IQ entries for a specific thread. */ 228 inline int calcFreeIQEntries(unsigned tid); 229 230 /** Calculates the number of free LSQ entries for a specific thread. */ 231 inline int calcFreeLSQEntries(unsigned tid); 232 233 /** Returns the number of valid instructions coming from decode. */ 234 unsigned validInsts(); 235 236 /** Reads signals telling rename to block/unblock. */ 237 void readStallSignals(unsigned tid); 238 239 /** Checks if any stages are telling rename to block. */ 240 bool checkStall(unsigned tid); 241 242 void readFreeEntries(unsigned tid); 243 244 bool checkSignalsAndUpdate(unsigned tid); 245 246 /** Either serializes on the next instruction available in the InstQueue, 247 * or records that it must serialize on the next instruction to enter 248 * rename. 249 * @param inst_list The list of younger, unprocessed instructions for the 250 * thread that has the serializeAfter instruction. 251 * @param tid The thread id. 252 */ 253 void serializeAfter(InstQueue &inst_list, unsigned tid); 254 255 /** Holds the information for each destination register rename. It holds 256 * the instruction's sequence number, the arch register, the old physical 257 * register for that arch. register, and the new physical register. 258 */ 259 struct RenameHistory { 260 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 261 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 262 : instSeqNum(_instSeqNum), archReg(_archReg), 263 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 264 { 265 } 266 267 /** The sequence number of the instruction that renamed. */ 268 InstSeqNum instSeqNum; 269 /** The architectural register index that was renamed. */ 270 RegIndex archReg; 271 /** The new physical register that the arch. register is renamed to. */ 272 PhysRegIndex newPhysReg; 273 /** The old physical register that the arch. register was renamed to. */ 274 PhysRegIndex prevPhysReg; 275 }; 276 277 /** A per-thread list of all destination register renames, used to either 278 * undo rename mappings or free old physical registers. 279 */ 280 std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 281 282 /** Pointer to CPU. */ 283 FullCPU *cpu; 284 285 /** Pointer to main time buffer used for backwards communication. */ 286 TimeBuffer<TimeStruct> *timeBuffer; 287 288 /** Wire to get IEW's output from backwards time buffer. */ 289 typename TimeBuffer<TimeStruct>::wire fromIEW; 290 291 /** Wire to get commit's output from backwards time buffer. */ 292 typename TimeBuffer<TimeStruct>::wire fromCommit; 293 294 /** Wire to write infromation heading to previous stages. */ 295 typename TimeBuffer<TimeStruct>::wire toDecode; 296 297 /** Rename instruction queue. */ 298 TimeBuffer<RenameStruct> *renameQueue; 299 300 /** Wire to write any information heading to IEW. */ 301 typename TimeBuffer<RenameStruct>::wire toIEW; 302 303 /** Decode instruction queue interface. */ 304 TimeBuffer<DecodeStruct> *decodeQueue; 305 306 /** Wire to get decode's output from decode queue. */ 307 typename TimeBuffer<DecodeStruct>::wire fromDecode; 308 309 /** Queue of all instructions coming from decode this cycle. */ 310 InstQueue insts[Impl::MaxThreads]; 311 312 /** Skid buffer between rename and decode. */ 313 InstQueue skidBuffer[Impl::MaxThreads]; 314 315 /** Rename map interface. */ 316 RenameMap *renameMap[Impl::MaxThreads]; 317 318 /** Free list interface. */ 319 FreeList *freeList; 320 321 /** Pointer to the list of active threads. */ 322 std::list<unsigned> *activeThreads; 323 324 /** Pointer to the scoreboard. */ 325 Scoreboard *scoreboard; 326 327 /** Count of instructions in progress that have been sent off to the IQ 328 * and ROB, but are not yet included in their occupancy counts. 329 */ 330 int instsInProgress[Impl::MaxThreads]; 331 332 /** Variable that tracks if decode has written to the time buffer this 333 * cycle. Used to tell CPU if there is activity this cycle. 334 */ 335 bool wroteToTimeBuffer; 336 337 /** Structures whose free entries impact the amount of instructions that 338 * can be renamed. 339 */ 340 struct FreeEntries { 341 unsigned iqEntries; 342 unsigned lsqEntries; 343 unsigned robEntries; 344 }; 345 346 /** Per-thread tracking of the number of free entries of back-end 347 * structures. 348 */ 349 FreeEntries freeEntries[Impl::MaxThreads]; 350 351 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 352 * partitioned between threads, so the ROB must tell rename when it is 353 * empty. 354 */ 355 bool emptyROB[Impl::MaxThreads]; 356 357 /** Source of possible stalls. */ 358 struct Stalls { 359 bool iew; 360 bool commit; 361 }; 362 363 /** Tracks which stages are telling decode to stall. */ 364 Stalls stalls[Impl::MaxThreads]; 365 366 /** The serialize instruction that rename has stalled on. */ 367 DynInstPtr serializeInst[Impl::MaxThreads]; 368 369 /** Records if rename needs to serialize on the next instruction for any 370 * thread. 371 */ 372 bool serializeOnNextInst[Impl::MaxThreads]; 373 374 /** Delay between iew and rename, in ticks. */ 375 int iewToRenameDelay; 376 377 /** Delay between decode and rename, in ticks. */ 378 int decodeToRenameDelay; 379 380 /** Delay between commit and rename, in ticks. */ 381 unsigned commitToRenameDelay; 382 383 /** Rename width, in instructions. */ 384 unsigned renameWidth; 385 386 /** Commit width, in instructions. Used so rename knows how many 387 * instructions might have freed registers in the previous cycle. 388 */ 389 unsigned commitWidth; 390 391 /** The index of the instruction in the time buffer to IEW that rename is 392 * currently using. 393 */ 394 unsigned toIEWIndex; 395 396 /** Whether or not rename needs to block this cycle. */ 397 bool blockThisCycle; 398 399 /** The number of threads active in rename. */ 400 unsigned numThreads; 401 402 /** The maximum skid buffer size. */ 403 unsigned skidBufferMax; 404 405 /** Enum to record the source of a structure full stall. Can come from 406 * either ROB, IQ, LSQ, and it is priortized in that order. 407 */ 408 enum FullSource { 409 ROB, 410 IQ, 411 LSQ, 412 NONE 413 }; 414 415 /** Function used to increment the stat that corresponds to the source of 416 * the stall. 417 */ 418 inline void incrFullStat(const FullSource &source); 419 420 /** Stat for total number of cycles spent squashing. */ 421 Stats::Scalar<> renameSquashCycles; 422 /** Stat for total number of cycles spent idle. */ 423 Stats::Scalar<> renameIdleCycles; 424 /** Stat for total number of cycles spent blocking. */ 425 Stats::Scalar<> renameBlockCycles; 426 /** Stat for total number of cycles spent stalling for a serializing inst. */ 427 Stats::Scalar<> renameSerializeStallCycles; 428 /** Stat for total number of cycles spent running normally. */ 429 Stats::Scalar<> renameRunCycles; 430 /** Stat for total number of cycles spent unblocking. */ 431 Stats::Scalar<> renameUnblockCycles; 432 /** Stat for total number of renamed instructions. */ 433 Stats::Scalar<> renameRenamedInsts; 434 /** Stat for total number of squashed instructions that rename discards. */ 435 Stats::Scalar<> renameSquashedInsts; 436 /** Stat for total number of times that the ROB starts a stall in rename. */ 437 Stats::Scalar<> renameROBFullEvents; 438 /** Stat for total number of times that the IQ starts a stall in rename. */ 439 Stats::Scalar<> renameIQFullEvents; 440 /** Stat for total number of times that the LSQ starts a stall in rename. */ 441 Stats::Scalar<> renameLSQFullEvents; 442 /** Stat for total number of times that rename runs out of free registers 443 * to use to rename. */ 444 Stats::Scalar<> renameFullRegistersEvents; 445 /** Stat for total number of renamed destination registers. */ 446 Stats::Scalar<> renameRenamedOperands; 447 /** Stat for total number of source register rename lookups. */ 448 Stats::Scalar<> renameRenameLookups; 449 /** Stat for total number of committed renaming mappings. */ 450 Stats::Scalar<> renameCommittedMaps; 451 /** Stat for total number of mappings that were undone due to a squash. */ 452 Stats::Scalar<> renameUndoneMaps; 453 Stats::Scalar<> renamedSerializing; 454 Stats::Scalar<> renamedTempSerializing; 455 Stats::Scalar<> renameSkidInsts; 456}; 457 458#endif // __CPU_O3_RENAME_HH__ 459