rename.hh revision 2292
19155SN/A/* 29155SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 39155SN/A * All rights reserved. 49155SN/A * 59155SN/A * Redistribution and use in source and binary forms, with or without 69155SN/A * modification, are permitted provided that the following conditions are 79155SN/A * met: redistributions of source code must retain the above copyright 89155SN/A * notice, this list of conditions and the following disclaimer; 99155SN/A * redistributions in binary form must reproduce the above copyright 109155SN/A * notice, this list of conditions and the following disclaimer in the 119155SN/A * documentation and/or other materials provided with the distribution; 129155SN/A * neither the name of the copyright holders nor the names of its 139155SN/A * contributors may be used to endorse or promote products derived from 149155SN/A * this software without specific prior written permission. 159155SN/A * 169155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279155SN/A */ 289155SN/A 299155SN/A#ifndef __CPU_O3_RENAME_HH__ 309155SN/A#define __CPU_O3_RENAME_HH__ 319105SN/A 3210441Snilay@cs.wisc.edu#include <list> 3310441Snilay@cs.wisc.edu 349105SN/A#include "base/statistics.hh" 359105SN/A#include "base/timebuf.hh" 369105SN/A 379105SN/A/** 3810919Sbrandon.potter@amd.com * DefaultRename handles both single threaded and SMT rename. Its width is 399297SN/A * specified by the parameters; each cycle it tries to rename that many 409105SN/A * instructions. It holds onto the rename history of all instructions with 419297SN/A * destination registers, storing the arch. register, the new physical 429105SN/A * register, and the old physical register, to allow for undoing of mappings 439297SN/A * if squashing happens, or freeing up registers upon commit. Rename handles 449105SN/A * blocking if the ROB, IQ, or LSQ is going to be full. Rename also handles 459184SN/A * barriers, and does so by stalling on the instruction until the ROB is 469105SN/A * empty and there are no instructions in flight to the ROB. 479105SN/A */ 4810919Sbrandon.potter@amd.comtemplate<class Impl> 499105SN/Aclass DefaultRename 509297SN/A{ 519105SN/A public: 529297SN/A // Typedefs from the Impl. 539297SN/A typedef typename Impl::CPUPol CPUPol; 5410314Snilay@cs.wisc.edu typedef typename Impl::DynInstPtr DynInstPtr; 559105SN/A typedef typename Impl::FullCPU FullCPU; 569297SN/A typedef typename Impl::Params Params; 579105SN/A 589105SN/A // Typedefs from the CPUPol 599105SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 609105SN/A typedef typename CPUPol::RenameStruct RenameStruct; 619297SN/A typedef typename CPUPol::TimeStruct TimeStruct; 629105SN/A typedef typename CPUPol::FreeList FreeList; 6310314Snilay@cs.wisc.edu typedef typename CPUPol::RenameMap RenameMap; 649105SN/A // These are used only for initialization. 659297SN/A typedef typename CPUPol::IEW IEW; 6610917Sbrandon.potter@amd.com typedef typename CPUPol::Commit Commit; 6710919Sbrandon.potter@amd.com 689105SN/A // Typedefs from the ISA. 699105SN/A typedef TheISA::RegIndex RegIndex; 709105SN/A 7110314Snilay@cs.wisc.edu // A deque is used to queue the instructions. Barrier insts must be 729105SN/A // added to the front of the deque, which is the only reason for using 7310969Sdavid.hashe@amd.com // a deque instead of a queue. (Most other stages use a queue) 749105SN/A typedef std::list<DynInstPtr> InstQueue; 759105SN/A 769105SN/A public: 77 /** Overall rename status. Used to determine if the CPU can deschedule 78 * itself due to a lack of activity. 79 */ 80 enum RenameStatus { 81 Active, 82 Inactive 83 }; 84 85 /** Individual thread status. */ 86 enum ThreadStatus { 87 Running, 88 Idle, 89 StartSquash, 90 Squashing, 91 Blocked, 92 Unblocking, 93 BarrierStall 94 }; 95 96 private: 97 /** Rename status. */ 98 RenameStatus _status; 99 100 /** Per-thread status. */ 101 ThreadStatus renameStatus[Impl::MaxThreads]; 102 103 public: 104 /** DefaultRename constructor. */ 105 DefaultRename(Params *params); 106 107 /** Returns the name of rename. */ 108 std::string name() const; 109 110 /** Registers statistics. */ 111 void regStats(); 112 113 /** Sets CPU pointer. */ 114 void setCPU(FullCPU *cpu_ptr); 115 116 /** Sets the main backwards communication time buffer pointer. */ 117 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 118 119 /** Sets pointer to time buffer used to communicate to the next stage. */ 120 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 121 122 /** Sets pointer to time buffer coming from decode. */ 123 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 124 125 /** Sets pointer to IEW stage. Used only for initialization. */ 126 void setIEWStage(IEW *iew_stage) 127 { iew_ptr = iew_stage; } 128 129 /** Sets pointer to commit stage. Used only for initialization. */ 130 void setCommitStage(Commit *commit_stage) 131 { commit_ptr = commit_stage; } 132 133 private: 134 /** Pointer to IEW stage. Used only for initialization. */ 135 IEW *iew_ptr; 136 137 /** Pointer to commit stage. Used only for initialization. */ 138 Commit *commit_ptr; 139 140 public: 141 /** Initializes variables for the stage. */ 142 void initStage(); 143 144 /** Sets pointer to list of active threads. */ 145 void setActiveThreads(std::list<unsigned> *at_ptr); 146 147 /** Sets pointer to rename maps (per-thread structures). */ 148 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 149 150 /** Sets pointer to the free list. */ 151 void setFreeList(FreeList *fl_ptr); 152 153 /** Sets pointer to the scoreboard. */ 154 void setScoreboard(Scoreboard *_scoreboard); 155 156 /** Squashes all instructions in a thread. */ 157 void squash(unsigned tid); 158 159 /** Ticks rename, which processes all input signals and attempts to rename 160 * as many instructions as possible. 161 */ 162 void tick(); 163 164 /** Debugging function used to dump history buffer of renamings. */ 165 void dumpHistory(); 166 167 private: 168 /** Determines what to do based on rename's current status. 169 * @param status_change rename() sets this variable if there was a status 170 * change (ie switching from blocking to unblocking). 171 * @param tid Thread id to rename instructions from. 172 */ 173 void rename(bool &status_change, unsigned tid); 174 175 /** Renames instructions for the given thread. Also handles serializing 176 * instructions. 177 */ 178 void renameInsts(unsigned tid); 179 180 /** Inserts unused instructions from a given thread into the skid buffer, 181 * to be renamed once rename unblocks. 182 */ 183 void skidInsert(unsigned tid); 184 185 /** Separates instructions from decode into individual lists of instructions 186 * sorted by thread. 187 */ 188 void sortInsts(); 189 190 /** Returns if all of the skid buffers are empty. */ 191 bool skidsEmpty(); 192 193 /** Updates overall rename status based on all of the threads' statuses. */ 194 void updateStatus(); 195 196 /** Switches rename to blocking, and signals back that rename has become 197 * blocked. 198 * @return Returns true if there is a status change. 199 */ 200 bool block(unsigned tid); 201 202 /** Switches rename to unblocking if the skid buffer is empty, and signals 203 * back that rename has unblocked. 204 * @return Returns true if there is a status change. 205 */ 206 bool unblock(unsigned tid); 207 208 /** Executes actual squash, removing squashed instructions. */ 209 void doSquash(unsigned tid); 210 211 /** Removes a committed instruction's rename history. */ 212 void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid); 213 214 /** Renames the source registers of an instruction. */ 215 inline void renameSrcRegs(DynInstPtr &inst, unsigned tid); 216 217 /** Renames the destination registers of an instruction. */ 218 inline void renameDestRegs(DynInstPtr &inst, unsigned tid); 219 220 /** Calculates the number of free ROB entries for a specific thread. */ 221 inline int calcFreeROBEntries(unsigned tid); 222 223 /** Calculates the number of free IQ entries for a specific thread. */ 224 inline int calcFreeIQEntries(unsigned tid); 225 226 /** Calculates the number of free LSQ entries for a specific thread. */ 227 inline int calcFreeLSQEntries(unsigned tid); 228 229 /** Returns the number of valid instructions coming from decode. */ 230 unsigned validInsts(); 231 232 /** Reads signals telling rename to block/unblock. */ 233 void readStallSignals(unsigned tid); 234 235 /** Checks if any stages are telling rename to block. */ 236 bool checkStall(unsigned tid); 237 238 void readFreeEntries(unsigned tid); 239 240 bool checkSignalsAndUpdate(unsigned tid); 241 242 /** Either serializes on the next instruction available in the InstQueue, 243 * or records that it must serialize on the next instruction to enter 244 * rename. 245 * @param inst_list The list of younger, unprocessed instructions for the 246 * thread that has the serializeAfter instruction. 247 * @param tid The thread id. 248 */ 249 void serializeAfter(InstQueue &inst_list, unsigned tid); 250 251 /** Holds the information for each destination register rename. It holds 252 * the instruction's sequence number, the arch register, the old physical 253 * register for that arch. register, and the new physical register. 254 */ 255 struct RenameHistory { 256 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 257 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 258 : instSeqNum(_instSeqNum), archReg(_archReg), 259 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg) 260 { 261 } 262 263 /** The sequence number of the instruction that renamed. */ 264 InstSeqNum instSeqNum; 265 /** The architectural register index that was renamed. */ 266 RegIndex archReg; 267 /** The new physical register that the arch. register is renamed to. */ 268 PhysRegIndex newPhysReg; 269 /** The old physical register that the arch. register was renamed to. */ 270 PhysRegIndex prevPhysReg; 271 }; 272 273 /** A per-thread list of all destination register renames, used to either 274 * undo rename mappings or free old physical registers. 275 */ 276 std::list<RenameHistory> historyBuffer[Impl::MaxThreads]; 277 278 /** Pointer to CPU. */ 279 FullCPU *cpu; 280 281 /** Pointer to main time buffer used for backwards communication. */ 282 TimeBuffer<TimeStruct> *timeBuffer; 283 284 /** Wire to get IEW's output from backwards time buffer. */ 285 typename TimeBuffer<TimeStruct>::wire fromIEW; 286 287 /** Wire to get commit's output from backwards time buffer. */ 288 typename TimeBuffer<TimeStruct>::wire fromCommit; 289 290 /** Wire to write infromation heading to previous stages. */ 291 typename TimeBuffer<TimeStruct>::wire toDecode; 292 293 /** Rename instruction queue. */ 294 TimeBuffer<RenameStruct> *renameQueue; 295 296 /** Wire to write any information heading to IEW. */ 297 typename TimeBuffer<RenameStruct>::wire toIEW; 298 299 /** Decode instruction queue interface. */ 300 TimeBuffer<DecodeStruct> *decodeQueue; 301 302 /** Wire to get decode's output from decode queue. */ 303 typename TimeBuffer<DecodeStruct>::wire fromDecode; 304 305 /** Queue of all instructions coming from decode this cycle. */ 306 InstQueue insts[Impl::MaxThreads]; 307 308 /** Skid buffer between rename and decode. */ 309 InstQueue skidBuffer[Impl::MaxThreads]; 310 311 /** Rename map interface. */ 312 RenameMap *renameMap[Impl::MaxThreads]; 313 314 /** Free list interface. */ 315 FreeList *freeList; 316 317 /** Pointer to the list of active threads. */ 318 std::list<unsigned> *activeThreads; 319 320 /** Pointer to the scoreboard. */ 321 Scoreboard *scoreboard; 322 323 /** Count of instructions in progress that have been sent off to the IQ 324 * and ROB, but are not yet included in their occupancy counts. 325 */ 326 int instsInProgress[Impl::MaxThreads]; 327 328 /** Variable that tracks if decode has written to the time buffer this 329 * cycle. Used to tell CPU if there is activity this cycle. 330 */ 331 bool wroteToTimeBuffer; 332 333 /** Structures whose free entries impact the amount of instructions that 334 * can be renamed. 335 */ 336 struct FreeEntries { 337 unsigned iqEntries; 338 unsigned lsqEntries; 339 unsigned robEntries; 340 }; 341 342 /** Per-thread tracking of the number of free entries of back-end 343 * structures. 344 */ 345 FreeEntries freeEntries[Impl::MaxThreads]; 346 347 /** Records if the ROB is empty. In SMT mode the ROB may be dynamically 348 * partitioned between threads, so the ROB must tell rename when it is 349 * empty. 350 */ 351 bool emptyROB[Impl::MaxThreads]; 352 353 /** Source of possible stalls. */ 354 struct Stalls { 355 bool iew; 356 bool commit; 357 }; 358 359 /** Tracks which stages are telling decode to stall. */ 360 Stalls stalls[Impl::MaxThreads]; 361 362 /** The barrier instruction that rename has stalled on. */ 363 DynInstPtr barrierInst[Impl::MaxThreads]; 364 365 /** Records if rename needs to serialize on the next instruction for any 366 * thread. 367 */ 368 bool serializeOnNextInst[Impl::MaxThreads]; 369 370 /** Delay between iew and rename, in ticks. */ 371 int iewToRenameDelay; 372 373 /** Delay between decode and rename, in ticks. */ 374 int decodeToRenameDelay; 375 376 /** Delay between commit and rename, in ticks. */ 377 unsigned commitToRenameDelay; 378 379 /** Rename width, in instructions. */ 380 unsigned renameWidth; 381 382 /** Commit width, in instructions. Used so rename knows how many 383 * instructions might have freed registers in the previous cycle. 384 */ 385 unsigned commitWidth; 386 387 /** The index of the instruction in the time buffer to IEW that rename is 388 * currently using. 389 */ 390 unsigned toIEWIndex; 391 392 /** Whether or not rename needs to block this cycle. */ 393 bool blockThisCycle; 394 395 /** The number of threads active in rename. */ 396 unsigned numThreads; 397 398 /** The maximum skid buffer size. */ 399 unsigned skidBufferMax; 400 401 /** Enum to record the source of a structure full stall. Can come from 402 * either ROB, IQ, LSQ, and it is priortized in that order. 403 */ 404 enum FullSource { 405 ROB, 406 IQ, 407 LSQ, 408 NONE 409 }; 410 411 /** Function used to increment the stat that corresponds to the source of 412 * the stall. 413 */ 414 inline void incrFullStat(const FullSource &source); 415 416 /** Stat for total number of cycles spent squashing. */ 417 Stats::Scalar<> renameSquashCycles; 418 /** Stat for total number of cycles spent idle. */ 419 Stats::Scalar<> renameIdleCycles; 420 /** Stat for total number of cycles spent blocking. */ 421 Stats::Scalar<> renameBlockCycles; 422 /** Stat for total number of cycles spent stalling for a barrier. */ 423 Stats::Scalar<> renameBarrierCycles; 424 /** Stat for total number of cycles spent running normally. */ 425 Stats::Scalar<> renameRunCycles; 426 /** Stat for total number of cycles spent unblocking. */ 427 Stats::Scalar<> renameUnblockCycles; 428 /** Stat for total number of renamed instructions. */ 429 Stats::Scalar<> renameRenamedInsts; 430 /** Stat for total number of squashed instructions that rename discards. */ 431 Stats::Scalar<> renameSquashedInsts; 432 /** Stat for total number of times that the ROB starts a stall in rename. */ 433 Stats::Scalar<> renameROBFullEvents; 434 /** Stat for total number of times that the IQ starts a stall in rename. */ 435 Stats::Scalar<> renameIQFullEvents; 436 /** Stat for total number of times that the LSQ starts a stall in rename. */ 437 Stats::Scalar<> renameLSQFullEvents; 438 /** Stat for total number of times that rename runs out of free registers 439 * to use to rename. */ 440 Stats::Scalar<> renameFullRegistersEvents; 441 /** Stat for total number of renamed destination registers. */ 442 Stats::Scalar<> renameRenamedOperands; 443 /** Stat for total number of source register rename lookups. */ 444 Stats::Scalar<> renameRenameLookups; 445 /** Stat for total number of committed renaming mappings. */ 446 Stats::Scalar<> renameCommittedMaps; 447 /** Stat for total number of mappings that were undone due to a squash. */ 448 Stats::Scalar<> renameUndoneMaps; 449}; 450 451#endif // __CPU_O3_RENAME_HH__ 452