rename.hh revision 2107
12623SN/A/* 22623SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292623SN/A// Todo: 302623SN/A// Fix up trap and barrier handling. 312623SN/A// May want to have different statuses to differentiate the different stall 322623SN/A// conditions. 332623SN/A 342623SN/A#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__ 352623SN/A#define __CPU_O3_CPU_SIMPLE_RENAME_HH__ 362623SN/A 372623SN/A#include <list> 382623SN/A 392623SN/A#include "base/statistics.hh" 402856Srdreslin@umich.edu#include "base/timebuf.hh" 412856Srdreslin@umich.edu 422856Srdreslin@umich.edu// Will need rename maps for both the int reg file and fp reg file. 432856Srdreslin@umich.edu// Or change rename map class to handle both. (RegFile handles both.) 442856Srdreslin@umich.edutemplate<class Impl> 452856Srdreslin@umich.educlass SimpleRename 462856Srdreslin@umich.edu{ 472856Srdreslin@umich.edu public: 482856Srdreslin@umich.edu // Typedefs from the Impl. 492856Srdreslin@umich.edu typedef typename Impl::CPUPol CPUPol; 502623SN/A typedef typename Impl::DynInstPtr DynInstPtr; 512623SN/A typedef typename Impl::FullCPU FullCPU; 522623SN/A typedef typename Impl::Params Params; 532623SN/A 542623SN/A typedef typename CPUPol::FetchStruct FetchStruct; 552623SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 562680Sktlim@umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 572680Sktlim@umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 582623SN/A 592623SN/A // Typedefs from the CPUPol 602680Sktlim@umich.edu typedef typename CPUPol::FreeList FreeList; 612623SN/A typedef typename CPUPol::RenameMap RenameMap; 622623SN/A 632623SN/A // Typedefs from the ISA. 642623SN/A typedef TheISA::Addr Addr; 652623SN/A typedef TheISA::RegIndex RegIndex; 662630SN/A 672623SN/A public: 682623SN/A // Rename will block if ROB becomes full or issue queue becomes full, 692623SN/A // or there are no free registers to rename to. 702623SN/A // Only case where rename squashes is if IEW squashes. 712623SN/A enum Status { 722623SN/A Running, 732630SN/A Idle, 742623SN/A Squashing, 752623SN/A Blocked, 762623SN/A Unblocking, 772623SN/A BarrierStall 782623SN/A }; 792623SN/A 802623SN/A private: 812631SN/A Status _status; 822631SN/A 832631SN/A public: 842623SN/A SimpleRename(Params ¶ms); 852623SN/A 862623SN/A void regStats(); 872623SN/A 882623SN/A void setCPU(FullCPU *cpu_ptr); 892623SN/A 902623SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 912623SN/A 922839Sktlim@umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 932798Sktlim@umich.edu 942623SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 952623SN/A 962623SN/A void setRenameMap(RenameMap *rm_ptr); 972623SN/A 982623SN/A void setFreeList(FreeList *fl_ptr); 992623SN/A 1002623SN/A void dumpHistory(); 1012623SN/A 1022623SN/A void tick(); 1032623SN/A 1042798Sktlim@umich.edu void rename(); 1052623SN/A 1062623SN/A void squash(); 1072623SN/A 1082623SN/A private: 1092623SN/A void block(); 1102623SN/A 1112798Sktlim@umich.edu inline void unblock(); 1122623SN/A 1132798Sktlim@umich.edu void doSquash(); 1142798Sktlim@umich.edu 1152798Sktlim@umich.edu void removeFromHistory(InstSeqNum inst_seq_num); 1162839Sktlim@umich.edu 1172798Sktlim@umich.edu inline void renameSrcRegs(DynInstPtr &inst); 1182839Sktlim@umich.edu 1192798Sktlim@umich.edu inline void renameDestRegs(DynInstPtr &inst); 1202798Sktlim@umich.edu 1212839Sktlim@umich.edu inline int calcFreeROBEntries(); 1222798Sktlim@umich.edu 1232798Sktlim@umich.edu inline int calcFreeIQEntries(); 1242839Sktlim@umich.edu 1252839Sktlim@umich.edu /** Holds the previous information for each rename. 1262798Sktlim@umich.edu * Note that often times the inst may have been deleted, so only access 1272798Sktlim@umich.edu * the pointer for the address and do not dereference it. 1282623SN/A */ 1292623SN/A struct RenameHistory { 1302623SN/A RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg, 1312798Sktlim@umich.edu PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg) 1322623SN/A : instSeqNum(_instSeqNum), archReg(_archReg), 1332798Sktlim@umich.edu newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg), 1342798Sktlim@umich.edu placeHolder(false) 1352798Sktlim@umich.edu { 1362798Sktlim@umich.edu } 1372623SN/A 1382798Sktlim@umich.edu /** Constructor used specifically for cases where a place holder 1392798Sktlim@umich.edu * rename history entry is being made. 1402798Sktlim@umich.edu */ 1412798Sktlim@umich.edu RenameHistory(InstSeqNum _instSeqNum) 1422798Sktlim@umich.edu : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0), 1432798Sktlim@umich.edu prevPhysReg(0), placeHolder(true) 1442798Sktlim@umich.edu { 1452798Sktlim@umich.edu } 1462798Sktlim@umich.edu 1472798Sktlim@umich.edu InstSeqNum instSeqNum; 1482798Sktlim@umich.edu RegIndex archReg; 1492798Sktlim@umich.edu PhysRegIndex newPhysReg; 1502798Sktlim@umich.edu PhysRegIndex prevPhysReg; 1512623SN/A bool placeHolder; 1522623SN/A }; 1532623SN/A 1542623SN/A std::list<RenameHistory> historyBuffer; 1552623SN/A 1562623SN/A /** CPU interface. */ 1572623SN/A FullCPU *cpu; 1582623SN/A 1592680Sktlim@umich.edu // Interfaces to objects outside of rename. 1602623SN/A /** Time buffer interface. */ 1612680Sktlim@umich.edu TimeBuffer<TimeStruct> *timeBuffer; 1622680Sktlim@umich.edu 1632680Sktlim@umich.edu /** Wire to get IEW's output from backwards time buffer. */ 1642623SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 1652623SN/A 1662623SN/A /** Wire to get commit's output from backwards time buffer. */ 1672623SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 1682623SN/A 1692623SN/A /** Wire to write infromation heading to previous stages. */ 1702623SN/A // Might not be the best name as not only decode will read it. 1712623SN/A typename TimeBuffer<TimeStruct>::wire toDecode; 1722623SN/A 1732623SN/A /** Rename instruction queue. */ 1742623SN/A TimeBuffer<RenameStruct> *renameQueue; 1752683Sktlim@umich.edu 1762623SN/A /** Wire to write any information heading to IEW. */ 1772623SN/A typename TimeBuffer<RenameStruct>::wire toIEW; 1782623SN/A 1792623SN/A /** Decode instruction queue interface. */ 1802623SN/A TimeBuffer<DecodeStruct> *decodeQueue; 1812623SN/A 1822623SN/A /** Wire to get decode's output from decode queue. */ 1832623SN/A typename TimeBuffer<DecodeStruct>::wire fromDecode; 1842623SN/A 1852623SN/A /** Skid buffer between rename and decode. */ 1862623SN/A std::queue<DecodeStruct> skidBuffer; 1872623SN/A 1882623SN/A /** Rename map interface. */ 1892623SN/A SimpleRenameMap *renameMap; 1902623SN/A 1912623SN/A /** Free list interface. */ 1922683Sktlim@umich.edu FreeList *freeList; 1932623SN/A 1942644Sstever@eecs.umich.edu /** Delay between iew and rename, in ticks. */ 1952623SN/A int iewToRenameDelay; 1962644Sstever@eecs.umich.edu 1972644Sstever@eecs.umich.edu /** Delay between decode and rename, in ticks. */ 1982623SN/A int decodeToRenameDelay; 1992623SN/A 2002623SN/A /** Delay between commit and rename, in ticks. */ 2012623SN/A unsigned commitToRenameDelay; 2022623SN/A 2032623SN/A /** Rename width, in instructions. */ 2042623SN/A unsigned renameWidth; 2052623SN/A 2062623SN/A /** Commit width, in instructions. Used so rename knows how many 2072623SN/A * instructions might have freed registers in the previous cycle. 2082663Sstever@eecs.umich.edu */ 2092663Sstever@eecs.umich.edu unsigned commitWidth; 2102835Srdreslin@umich.edu 2112683Sktlim@umich.edu /** The instruction that rename is currently on. It needs to have 2122623SN/A * persistent state so that when a stall occurs in the middle of a 2132623SN/A * group of instructions, it can restart at the proper instruction. 2142623SN/A */ 2152623SN/A unsigned numInst; 2162623SN/A 2172623SN/A Stats::Scalar<> renameSquashCycles; 2182683Sktlim@umich.edu Stats::Scalar<> renameIdleCycles; 2192623SN/A Stats::Scalar<> renameBlockCycles; 2202623SN/A Stats::Scalar<> renameUnblockCycles; 2212623SN/A Stats::Scalar<> renameRenamedInsts; 2222641Sstever@eecs.umich.edu Stats::Scalar<> renameSquashedInsts; 2232641Sstever@eecs.umich.edu Stats::Scalar<> renameROBFullEvents; 2242623SN/A Stats::Scalar<> renameIQFullEvents; 2252623SN/A Stats::Scalar<> renameFullRegistersEvents; 2262630SN/A Stats::Scalar<> renameRenamedOperands; 2272623SN/A Stats::Scalar<> renameRenameLookups; 2282623SN/A Stats::Scalar<> renameHBPlaceHolders; 2292623SN/A Stats::Scalar<> renameCommittedMaps; 2302623SN/A Stats::Scalar<> renameUndoneMaps; 2312623SN/A Stats::Scalar<> renameValidUndoneMaps; 2322623SN/A}; 2332623SN/A 2342623SN/A#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__ 2352623SN/A